JPH09214490A - Arbitration circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To constitute the arbitration circuit only of the hardware, reading one of the arbitrated timing information rearranged with plural sets of input timing information received between input clocks without aborting any information according to priority through reading by a read clock. SOLUTION: A timing information detection section 52 detects presence of input timing information and its number. Pulse generating means 53, 54 are operated synchronously with an n-multiple clock and generate an enable pulse and a write clock according to priority based on the result of the timing information detection section 52. An enable circuit 51 enables input timing information in response to the enable pulse. An FIFO circuit 55 writes the timing information after enable by the enable circuit 51 in response to the write clock WCLK and reads the written content synchronously with a read clock RCLK as arbitrated timing information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbitration circuit, and more particularly to an arbitration circuit applied to a PDS subscriber line system tester.

[0002]

2. Description of the Related Art A PDS subscriber line system, as shown in FIG. 3, includes a parent device 10 with first to nth child devices 21 to 2.
In this system, n (n is an integer of 2 or more) is connected by a star coupler (SC) 30. In the tester 40 in this system, the parent device 10 is the first to nth child devices 21.
It is for generating continuous data to be transmitted to ~ 2n.

The tester 40 includes the first to nth child devices 21.
~ 2n corresponding to the first to n-th timing generator 41
To 4n, the first to n-th timing generation units 41 to 4n generate the transmission timing information (input timing information) in a burst at an arbitrary phase. The transmission timing information (input timing information) generated by the first to n-th timing generation units 41 to 4n is the arbitration circuit 5
The first to n-th data generating units 61 to 6n are arbitrated so that they do not collide with each other at 0, and the arbitrated timing information is used.
Of the first to n-th data generators 61 to 6n.
Generate continuous data from.

Further, since the amount of data for each child device 21 to 2n changes according to the instruction, the first to nth timing generators 41 to 4n can change the amount of transmission timing information.

FIG. 4 shows the configuration of a conventional PDS subscriber line system tester 40 '. The conventional PDS subscriber line system tester 40 'includes a processor 70 that performs an arbitration operation with software 71, and first to nth data generators 61 to 6.
n and. That is, the processor 70 constitutes the circuit portion of the first to n-th timing generators 41 to 4n and the arbitration circuit 50 shown in FIG. That is,
The processor 70 uses the first to n-th data generators 61 to 6
By controlling the data transmission to n, the parent device 2
It prevents the collision of data against 0.

[0006]

As is well known, the processor 70 comprises, as hardware, a CPU, a ROM storing the software 71, a RAM, a DCXO, an address DEC and the like. As described above, the circuit scale is increased only by the hardware for mounting the software 71, but the development scale of the software 71 is increased because the development of the software 71 is also added.

As a prior art in which arbitration processing is performed on hardware, for example, Japanese Patent Laid-Open No. 64-67665.
The "common bus arbitration circuit" disclosed in Japanese Patent Publication is known. In this prior art, by arbitrating bus use permission in a system in which bus request signals from a plurality of bus masters are output asynchronously with the system clock, a plurality of data does not collide on the system bus, and I try to prevent the bus from being locked.

However, according to this prior art, in a system in which data is transmitted between a plurality of computers (processors) sharing a system bus via the system bus, a plurality of bus masters access to a common system bus (bus The present invention relates to a technique for arbitrating (use request), and is configured by hardware to perform an arbitration process necessary when a plurality of data are sent from a plurality of timing generators to a single device at arbitrary phases. The field of application is different from that of the present invention, which is a technique to be realized in.

An object of the present invention is to rearrange a plurality of pieces of input timing information inputted during an input clock so as not to discard any of them, and to read arbitrated timing information according to the priority by reading with a read clock. It is to provide an arbitration circuit having a hardware configuration that enables individual reading.

[0010]

In the arbitration circuit according to the present invention, a maximum of n pieces (n is an integer of 2 or more) of input timing information input at arbitrary timing in synchronization with an input clock are discarded. It is an arbitration circuit that rearranges data without any rearrangement and can read one piece of arbitrated timing information according to the priority by reading with a read clock having the same clock width as the input clock. A timing information detection unit that detects the number of input timing information; operates in synchronization with an n-fold clock having a frequency that is n times the clock frequency of the input clock, and prioritizes based on the result of the timing information detection unit. Enable clock with a width of 1/4 the clock width of the following input clock and write clock with the same clock width as the n-fold clock Pulse generating means for generating input timing information in response to an enable pulse; timing information after enabling by the enable circuit is written in response to a write clock, and the written content is read by a read clock. A FIFO circuit that reads out as arbitrated timing information;
It is characterized by having.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing an arbitration circuit according to an embodiment of the present invention, which is used for the arbitration circuit 50 in the PDS subscriber line system tester 40 shown in FIG. The illustrated arbitration circuit 50 shows an example when n = 4.

That is, the arbitration circuit 50 includes the first to fourth
A circuit for receiving the input timing information 1 to 4 from each of the timing generating sections 41 to 44, performing arbitration processing, and then transmitting the arbitrated timing information 1 to 4 to the first to fourth data generating sections 61 to 64, respectively. Is.

The arbitration circuit 50 includes an enable circuit 51,
It has a timing information detection unit 52, a pulse generation unit 53, an up / down counter 54, and a FIFO circuit 55.

The timing information detecting section 52 detects the presence or absence of each input timing information from the input timing information 1 to 4, and simultaneously detects the number of pieces of the input timing information.

The pulse generator 53 operates in synchronization with an n-fold clock having a frequency n times the clock frequency of the input clock, and the result detected by the timing information detector 52 and the counter of the up / down counter 54 described later. Enable pulse and write clock WCLK based on
And up / down counter control pulses are generated.

More specifically, the pulse generator 53 is
The enable pulse of each input timing information is generated according to the priority of the timing information written in the IFO circuit 55, and is sent to the enable circuit 51. This enable pulse is generated under the following conditions 1 to 3.

Condition 1: An enable pulse is generated according to the priority of input timing information. Here, the input timing information 1, 2, 3, 4 is generated in this order.

Condition 2: When there is no input timing information having a higher priority than itself, the enable pulse is generated by justification.

Condition 3: The pulse width of the enable pulse is
Since the input timing information needs to be written in the FIFO circuit 55 by the time the next input timing information arrives, the width is ¼ of the clock width of the input clock.

The pulse generator 53 also generates a write clock WCLK for writing the input timing information in the FIFO circuit 55. The write clock WCLK is
It is necessary to send the same number of clocks as the input timing information input at the same time. However, even if there is no input timing information, it is necessary to write "0" in the FIFO circuit 55, so one clock is generated. More specifically, when the input timing information is 0, the pulse generator 53 generates one write clock WCLK (however, when the up / down counter 54 is “1”, this pulse is masked). When the input timing information is 1, the pulse generator 53 sets the write clock WCLK to 1
Occurs individually. When there are two pieces of input timing information, the pulse generator 53 generates two write clocks WCLK.
When there are three pieces of input timing information, the pulse generator 53 generates three write clocks WCLK. When there are four pieces of input timing information, the pulse generator 53 generates four write clocks WCLK.

The pulse generator 53 further counts up pulses or up / down counters 54 for counting up the up / down counter 54 according to the number of simultaneously input input timing information detected by the timing information detecting portion 52. A countdown pulse for counting down is generated. To elaborate,
When the input timing information is 0, the pulse generator 53 generates one countdown pulse (however, up / down
If the down counter 54 is "0", this pulse is masked). When the input timing information is one, the pulse generator 53 does nothing. When there are two pieces of input timing information, the pulse generator 53 outputs 1 count-up pulse.
Occurs individually. When there are three pieces of input timing information, the pulse generator 53 generates two count-up pulses. When there are four pieces of input timing information, the pulse generator 53 generates three count-up pulses.

The up / down counter 54 performs up / down operation by the count-up pulse or count-down pulse generated by the pulse generator 53, and supplies the count value to the pulse generator.

In any case, the combination of the pulse generator 53 and the up / down counter 54 operates in synchronization with the n-fold clock, and based on the result of the timing information detector 52, the enable pulse according to the priority order, It functions as a pulse generating means for generating an n-fold clock and a write clock having the same clock width.

With the above configuration, the arbitration circuit 50 performs the following operation. Input timing information is m (m ≦ n)
Suppose there is a collision. In this case, m pieces of input timing information are sequentially written in the FIFO circuit 55, the up / down counter 54 is up by (m-1), and the FIFO circuit 5
For the reading of 5, the number of bits written to is monitored. When the value of the up / down counter 54 is “1” or more and the input timing information is 0, the FI
Writing to the FO circuit 55 is prohibited and the up / down counter 54 is decremented by -1. In this way, the number of writes and the number of reads are controlled to always match.

FIG. 2 shows a time chart for explaining the operation of the arbitration circuit 50 when four pieces of input timing information are received at the same time. In FIG. 2, description 1 shows a state in which the input timing information 1 to 4 are simultaneously input to the arbitration circuit 50. Explanation 2 shows the timing information 1 to 4 after enabling and the write clock WCLK supplied to the FIFO circuit 55. The explanation 3 shows the arbitrated timing information 1 to 4 read by the read clock.

In the above embodiment, the case of n = 4 has been described, but it goes without saying that the same can be applied to the case where n is 2, 3 or 5 or more.

[0028]

As described above, according to the present invention, a plurality of pieces of input timing information input during an input clock are rearranged without being discarded, and read by a read clock, arbitrated timing information according to priority. The arbitration circuit that can read one of the above can be configured only by hardware. Therefore, the development scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an arbitration circuit according to an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the arbitration circuit shown in FIG.

FIG. 3 is a block diagram showing a PDS subscriber line system and a PDS subscriber line system tester to which an arbitration circuit according to the present invention is applied.

FIG. 4 is a block diagram showing a conventional PDS subscriber line system tester.

[Explanation of symbols]

 50 Arbitration Circuit 51 Enable Circuit 52 Timing Information Detection Unit 53 Pulse Generation Unit 54 Up / Down Counter 55 FIFO Circuit

Claims (3)

[Claims] 1. A maximum of n pieces (n is an integer of 2 or more) of input timing information input at arbitrary timings in synchronization with an input clock are rearranged without discarding any of them, and have the same clock width as the input clock. An arbitration circuit capable of reading out one piece of arbitrated timing information according to a priority order by reading with a read clock having, and detecting the presence or absence of the input timing information and the number of pieces of input timing information input at the same time. The timing information detector operates in synchronization with an n-fold clock having a frequency n times the clock frequency of the input clock, and based on the result of the timing information detector, An enable pulse having a quarter width of the clock width and a write clock having the same clock width as the n-fold clock are generated. Pulse generation means, an enable circuit for enabling the input timing information in response to the enable pulse, timing information after enabling by the enable circuit is written in response to the write clock, and the written content is the read clock And an FIFO circuit for reading out the arbitrated timing information as the arbitration completed timing information. 2. The pulse generation means operates in synchronization with the n-fold clock, and based on the result of the timing information detection section and a count value, the enable pulse, the write clock, a count-up pulse, and a countdown. The arbitration circuit according to claim 1, comprising a pulse generation unit that generates a pulse, and an up / down counter that performs an up / down operation by the count-up pulse and the count-down pulse and outputs the count value. . 3. The pulse generator generates one write clock and one countdown pulse when the input timing information is 0, and the input timing information is m (1 ≦ m). The arbitration circuit according to claim 2, wherein in the case of ≤n), the write clock is generated m times and the count-up pulse is generated (m-1) times.