JPH043239A - Bus controller - Google Patents

Abstract

PURPOSE:To constitute the bus controller so that the bus control is executed by a small hardware quantity, and also, each user device can use rationally the bus by giving the use permission of the bus in order at every certain time to each user device from the bus controller. CONSTITUTION:In a bus controller 10a for executing the control of the bus using right of plural user devices 21 - 2n connected to one bus, a timing setting means 11 for counting the time for giving the bus using right to one user device 21 - 2n and setting the timing is provided. Also, a bus use permitting signal generating means 12 for transmitting successively bus use permitting signals 31 - 3n to each user device 21 - 2n in accordance with the sequence determined in advance at every set timing is provided. That is, each user device 21 - 2n executes a communication by using the bus by receiving the respective bus use permitting signals 31 - 3n, and does not transmit a bus use request signal to the bus controller 10a by itself. In such a way, the hardware quantity is decreased, and also, the bus can be used rationally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a bus control device in an information processing device.

〔overview〕

The present invention provides a bus control device that controls the right to use the bus for a plurality of user devices connected to one bus. By sequentially transmitting a bus use permission signal to each user device according to a predetermined order at each set timing, bus control can be performed with a small amount of hardware, and it can be streamlined for each user device. The system allows bus usage rights to be granted to the public at any time.

[Conventional technology]

As shown in FIG. 5, when user devices 21 to 2n that use a plurality of buses are connected to one bus 50, it is conceivable that a request to use the bus 50 is made from a plurality of user devices 21 to 2n. . In such a case, control is required to select one user device from among the user devices that have issued bus use requests and allow that user device to use the bus.

Conventionally, the above-mentioned control has been performed as follows.

First, a bus control device 1 that controls the bus in the bus system.
0, and each user device 21 to 2n sends a bus use request signal for requesting bus use to the bus control device 10 via the bus use request signal lines 41 to 4n, respectively, and the bus control device 10 The bus use permission signal lines 31 to 3n each provide a bus use permission signal for giving permission for use.
to each user device 21 to 2n.

Actually, when each user device 21-2n wants to use the bus, it sets the bus use request signal line 41-4n to logic "1" level. The bus control device 10 has a plurality of user devices 21
From day 2 onward, when a bus use request signal is raised, a bus use permission signal is sent to the user device with the highest priority among those for which the bus use request signal was raised, according to a predetermined priority order. Lines 31-3n
The bus 50 is granted the right to use the bus by setting it to logic "1" level.

[Problem to be solved by the invention]

The bus control device described above uses a method in which the user device that it wants to use issues a bus use request signal, and the bus control device selects only one user device with the highest priority among them. Both bus control devices had the disadvantage of having a complicated structure. Furthermore, even when there is a request to use the bus, a user device with a low priority is kept open for a long time, which has the disadvantage that it cannot be handled rationally.

An object of the present invention is to provide a bus control device that reduces the amount of hardware and allows each user device to use the bus rationally by eliminating the above-mentioned drawbacks.

[Means to solve the problem]

The present invention provides a bus control device that controls the right to use the bus for a plurality of user devices connected to one bus. and bus use permission signal generation means for sequentially transmitting bus use permission signals to each user device in a predetermined order at each of the set timings.

Further, the present invention can include timing control means for controlling the timing set by the timing setting means.

Further, in the present invention, the timing control means may include means for controlling the timing of each user device according to the bus usage state of each user device.

[Effect]

The timing setting means measures the time for granting bus usage rights to one user device and sets the timing. The bus use permission signal generating means sets the bus use permission signal line to the logic "1" level and transmits the bus use permission signal to each user device according to a predetermined order at each set timing. . Upon receiving this bus use permission signal, each user device communicates using the bus, and does not itself transmit a bus use request signal to the bus control device.

Therefore, the hardware required for bus usage requests including bus usage request signal lines that were required in the past is no longer required, the amount of hardware is reduced, and each user device is given an equal opportunity to use the bus, allowing for rational bus usage. becomes possible.

Furthermore, by allowing the timing setting by the timing setting means to be controlled in accordance with the bus usage status of each user device, more rational bus usage becomes possible.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the essential parts of a first embodiment of the present invention, and FIG. 2 is a block diagram showing a system to which the same is applied.

According to FIG. 2, the system of this embodiment includes a bus 50 including a bus control device 10a and a plurality of n user devices 21 to 2n.
are connected to the bus control device 10a and the user devices 21 to 2.
Bus use permission signal lines 31 to 3n are connected between them, respectively.

According to FIG. 1, the bus control device 10a includes a timing setting means 11 that measures the time to grant bus usage rights to one user device and sets the timing, which is a feature of the present invention. At each timing,
A bus use permission signal generating means 12 is provided for transmitting a bus use permission signal to each user device 21 to 2n in a predetermined order.

Next, the operation of the third embodiment will be explained.

Note that the buses are given to the user devices 21 to 2n in the order of numbers 21 to 20.

The bus control device 10a uses the timing setting means 11 to measure the time during which the bus is given to one user, and outputs a timing signal 60 for setting the timing.

When the bus use permission signal generating means 12 first receives the timing signal 60 from the timing setting means 11, it sets only the bus use permission signal line 31 for the user device 21 to logic "1" level. The user device 21 transfers data using the bus 50 if the bus use permission signal line 31 becomes logic “1” level and the device needs to use the bus 50, and leaves it as is if it is not necessary. .

Furthermore, when the bus use permission signal generation means 12 next receives the timing signal 60 from the timing setting means 11,
The bus use permission signal line 31 is set to logic “0” level, and the bus use permission signal line 32 for the user device 22 is set to the logic “0” level.
to the logical "1" level. As a result, the user device 22
uses the bus 50 if it is necessary to use the bus 50.

In the same way as above, the bus use permission signal generation means 12:
Each time the timing signal 60 is received from the timing setting means 11, the bus use permission signal lines 31 to 3n are sequentially set to the logic "1" level. In addition, each user device 21 to 2
n uses the bus 50 only while the bus use permission signal lines 31 to 3n for its own device are at logic "1" level.

FIG. 3 is a block diagram showing the main parts of a bus control device according to a second embodiment of the present invention.

The bus control device 10b of the second embodiment further controls the timing set by the timing setting means 11, which is a feature of the present invention, compared to the bus control device 10a of the first embodiment shown in FIG. A timing control means 13 is provided for controlling the timing.

This timing control means 13 changes the length of time that one user device uses the bus, for example, in accordance with the usage status of the bus 50 ascertained within the bus control device. This has the advantage of allowing more rational bus usage.

FIG. 4 is a block diagram showing the main parts of a bus control device according to a third embodiment of the present invention.

In the second embodiment shown in FIG. 3, the bus control device 10C of the third embodiment functions as the timing control means 13 according to the bus usage status of each user device 21 to 2n, which is a feature of the present invention. A timing control means 13a including means for controlling timing for each user device 21 to 2n is provided.

According to the third embodiment, the bus usage time is set in accordance with the bus usage status of each user device 21 to 2n.
This has the advantage that buses can be used more rationally.

〔Effect of the invention〕

As explained above, the present invention enables bus control with a small amount of hardware by allowing the bus control device to sequentially grant permission to use the bus to each user device at a certain time interval. There is also the effect that each user device can use the bus rationally.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of a first embodiment of the present invention. FIG. 2 is a block diagram showing an example of a system using the same. FIG. 3 is a block diagram showing the main parts of a second embodiment of the present invention. FIG. 4 is a block diagram showing the main parts of a third embodiment of the present invention. FIG. 5 is a block configuration diagram showing an example of a system using a conventional example. 10, ioa-10c...bus control device, 11...
Timing setting means, 12...Bus use permission signal generation means, 13.13a...Timing control means, 21-
2n...User device, 31-3n...Bus use permission signal line, 41-4n...Bus use request signal line, 50.
...Bus, 60...Timing signal.

Claims (1)

[Claims] 1. In a bus control device that controls the right to use the bus for a plurality of user devices connected to one bus, the timing is set by measuring the time for granting the right to use the bus to one user device. A bus control system comprising: timing setting means; and bus use permission signal generation means for sequentially transmitting bus use permission signals to each user device in a predetermined order at each of the set timings. Device. 2. The bus control device according to claim 1, further comprising timing control means for controlling the timing set by said timing setting means. 3. The bus control device according to claim 2, wherein said timing control means includes means for controlling timing for each user device according to the bus usage status of each user device.