JPH0210459A - Bus use right determining system - Google Patents

Abstract

PURPOSE:To efficiently transfer data by limiting the number of cycles to admit the continuous bus use and admitting an absolute precedence independently of priority levels of bus use of respective modules with respect to this continuous bus use. CONSTITUTION:An arbiter 10 consists of a continuous bus use limiting means 11, a continuous bus use request means 12, a continuous bus use permitting means 13, and a fundamental arbiter 14. Plural modules 15-17 are connected to this arbiter 10. The continuous bus use limiting means 11 limits the number of bus cycles, during which each of modules 15-17 which is permitted to use the bus can use the common bus, to a certain value. The continuous bus use request means 12 requests the continuous use of the common bus in preference to the other modules based on the continuous bus use request signal of one of modules 15-17 which is permitted to use the bus. The continuous bus use permitting means 13 permits the use of the common bus within the range of the certain number of cycles in response to the continuous use request.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention provides a method for determining the right to use a bus. Figure 3 shows a method for determining bus usage rights (conventional technology) that aims to distribute bus usage rights in a well-balanced manner to each module by allowing continuous use of the common bus in preference to other modules. In the figure, A and C
FIG. 1 is a block diagram showing an example of a configuration of a shared memory access method, and is a block diagram illustrating an example of a system in which data is transferred via a common bus. In the figure, 1.
Reference numeral 2 denotes an address bus driver that connects and connects the module A or C with the address bus 3 that is a common bus, and 4.5 represents a data bus driver that connects and connects the module A or C with the data bus 6 that is the common bus. Reference numeral 7 denotes a bus right control module (hereinafter referred to as arbiter) which allocates the right to use the common bus for each bus cycle in response to a common bus use request from module A or C. REQ A and RE in the diagram
QC is a common bus use request signal from each module, G
NT A and GNT C indicate common bus use permission signals for each module. 8 indicates a shared memory that each module accesses via a common bus.

As shown in FIG. 3, in a system in which a plurality of modules transfer data via a common bus, the bus usage right determination method has conventionally been as follows: (a) An individual bus usage request line (REQ A) is sent for each bus cycle.

REQ C, etc.), permission line (GNT A, GNT C, etc.) to determine the right to use the bus [hereinafter referred to as the conventional method (
1)], (This method is mainly used when transferring 0 units of data at once.The module that has acquired the right to use the bus monopolizes the bus until the necessary transfer is completed, and then releases the bus. method [hereinafter referred to as conventional method (
2)] and (c) an improved method of (a) and (b) described later [hereinafter referred to as conventional method (3)] are known.

FIG. 4 is a drawing showing the result of determining the right to use the bus in conventional method (1). The permission signal (GNT ) is drawn corresponding to each bus cycle. Note that, for example, "5 cycles" within 0 in the figure indicates a block data transfer request for 5 bus cycles. Furthermore, the common bus use priority order is A, B (not shown), and C.

Conventional method (1) is used when there is a request to transfer more block data at once than the amount of data that can be transferred in one bus cycle to a module with a lower priority [Figure 4 (4-4)]
(4-5) In this case, only the transfer of modules with high priority is given priority, and modules with low priority can only occasionally use the bus and it takes a very long time to transfer one block. There was a problem.

FIG. 5 is a diagram showing the bus usage right determination result in conventional method (2), and the meanings of symbols in the diagram are the same as in FIG. 4. It is also the same that the priorities are in the order of A, B, and C. The results are different in Figure 5 (5-5) compared to Figure 4.

In conventional method (2), the module that has acquired the right to use the bus monopolizes the bus until the transfer is completed, so if a module with a lower priority transfers a large amount of data [Fig.
5-5)], there was a problem in that even if there was an urgent transfer request from a module with a high priority, the bus could not be used until the transfer was completed.

Therefore, in order to solve the problems of conventional methods (1) and (2), in addition to the bus usage priority of the modules, the bus usage request level is divided into multiple stages, and the priority of the modules and the bus usage A method [conventional method (3)] has been considered in which the right to use the bus is determined based on the request level.

FIG. 6 is a diagram showing the final priority determined by the priority among modules and the bus use request level, and shows the case where the bus use request level is in three stages. In the conventional method (3), the priority order can be changed as appropriate depending on the content of the data. Therefore, even if a module has a low priority among modules, by issuing a bus use request with a high priority level (for example, C), a module with a high priority can issue a bus use request with a low priority level (for example, A3). If you do this, you can obtain the right to use the bus, and even if a module with a lower priority tries to transfer a large amount of data, if a module with a higher priority makes a bus usage request with the same request level, it will be given priority. Data transfer can be performed by interrupting the data transfer of a module with a lower rank.

(Problems to be Solved by the Invention) However, although conventional method (3) solves the problems of conventional methods (1) and (2) by increasing the degree of freedom in determining bus usage rights, on the other hand, , Arrival priority control and module bus request control become complicated, the amount of circuitry required for control increases, and the number of signal lines related to bus priority control also increases to perform multiple levels of bus requests. ,
There was a problem in that the configuration was complicated both in terms of hardware and software.

The present invention eliminates the above-mentioned problems, enables continuous transfer of data for a pre-specified number of cycles by adding only a small number of signal lines, and enables efficient bus usage rights allocation. It provides:

(Means for Solving the Problems) The present invention provides a method for determining bus usage rights for each bus cycle in response to common bus usage requests from a plurality of modules. continuous bus use limiting means for limiting the number of bus cycles that a module can use the common bus in succession, and a module that has been granted permission to use the bus issues a request for continuous use and is given permission to use the common bus continuously in priority over other modules; and continuous bus use permission means for granting permission to use the common bus within the limit of the number of bus cycles in response to the continuous use request. It is a method.

(Operation) The bus use right determination method of the present invention (hereinafter sometimes referred to as the present invention method) is such that each module has a priority order of bus use, and each module issues a request for use of the bus. Accordingly, in addition to the bus usage right system that determines the bus usage right for each bus cycle, various means having the following functions are provided.

The continuous bus use limiting means limits the number of bus cycles in which a module that has been granted permission to use the bus can continuously use the common bus to a certain number of times.

The continuous bus use requesting means requests continuous use of the common bus in preference to other modules based on the continuous bus use request signal (CREQ) of the module that has been granted permission to use the bus.

Further, the continuous bus use permission means grants use of the common bus within the range of the number of bus cycles in response to the continuous use request, and generates a continuous bus use permission signal.

Therefore, in the method of the present invention, when data transfers that are not block data conflict, the conventional method (1) is applied,
If any of the competing data transfers is related to block data, the same bus usage right determination result as when the conventional method (2) is applied is obtained only for a fixed number of bus cycles.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram illustrating the configuration of a system related to the bus usage right determination method of the present invention.

In the figure, reference numeral 10 denotes an arbiter, which consists of a continuous bus use restriction means 11, a continuous bus use request means 12, a continuous bus use permission means 13, and a basic arbiter 14 having the same configuration as the arbiter based on the conventional method (1). ing. 15~
Reference numeral 17 denotes a plurality of modules that use a common data bus, each with an individual bus use request line 15. ．． 161. ...17
．． and individual bus usage permission lines 15□, 16□,...17
Equipped with □. Reference numeral 18 denotes a continuous bus use request line, which is composed of one wired-OR signal line. 19 indicates continuous bus use permission means 13 and each module 151゜164
．． ...This is a continuous bus line that connects 17□. In addition, BREQ+ etc. in the figure are individual bus use request signals, BG
NT+ and the like indicate an individual bus use permission signal, CREQ a continuous bus use request signal, and CGNT a continuous bus use permission signal. The basic arbiter 14 uses individual bus use request lines 15. ．． 1
6. ,...17. The bus control system gives permission to only one module to use the bus according to the priority order of each module's usage rights. The continuous bus use request line 18 is connected to the individual bus use permission line 15 by a certain module. ．． 16. ,...17
．． This is a signal line for requesting continuous use of the bus in the next bus cycle after being granted the right to use the bus. Further, the continuous bus use permission line 19 is a signal line for permitting a module that has made a continuous bus use request to use the bus in the next bus cycle as well.

FIG. 2 is a circuit diagram showing an embodiment of the arbiter 1o in FIG. 1.

As shown in the figure, the continuous bus use limiting means 17 includes a counter 21 and a flip-flop 22. The counter 21 counts the number of continuous bus use permissions (bus cycle number), and when continuous bus use permission is requested exceeding a pre-specified limit number of times, the counter 21 sets the carrier output to "1" and Disable continuous bus use requests,
The bus usage right determination operation is restarted based on the new bus usage request. The continuous bus use requesting means 12 uses the gate 153
．． 165. ...17s, 23, 24, flip-flop 25, etc. The flip-flop 25 is a flip-flop that maintains that the module has acquired the right to use the bus through any of the individual bus permission lines 151, 16□, ... 17, or the continuous bus permission line 19 in the previous cycle. It is a pool. When the output of this flip-flop 25 is "1", the continuous bus use request is valid. Further, the continuous bus use permission means 13 includes an AND gate 26 to which the outputs of the continuous bus use restriction means 11 and the continuous bus use request means 12 are input.

Next, the operation of the armature 10 shown in FIG. 2 will be explained with reference to the timing chart shown in FIG. 7.

First, in a certain bus cycle, when a certain module, for example, the module 17 in FIG. If the line 18 is active and the carry output of the counter 21 is "0" due to a continuous bus use request within the limited number of cycles, the output of the AND gate 26 becomes "1", and the continuous bus use permission line 1
9 becomes active (■), and the module is given the right to use the bus continuously in the next cycle (■).
.

In this way, once a continuous use request is granted, even if there is an individual bus use request from another module in the cycle, AND gates 153, 163.・・・
173 invalidates the input signal of the basic arbiter 14, and the individual bus use permission line 15. ．． 16. ,...171
The right to use the bus is not granted to the module, and the priority use of the module that is allowed to use the module continuously is ensured.

Therefore, if the CGNT signal becomes active in a certain cycle and continuous use is permitted, the flip-flop 25 is set to rlJ via the gate 23, and if there is a continuous bus use request in that cycle and the request is within the limited number of cycles. If so, continuous use of the same module is permitted.

Then, when the same module is allowed to use the bus for a predetermined number of cycles or a limited number of cycles consecutively, the carry output of the counter 21 becomes "1", and the output of the AND gate 26 becomes "o". Continuous bus use permission becomes non-active (■). At this time, if any module, such as the module 15 in FIG. Priority control similar to conventional method (1) is performed, and the individual bus use permission line 152 of the module with the highest priority becomes active, giving the module the right to use the bus (■).

Note that the operation of the arbiter 10 when there is no continuous bus use request is the same as that of the conventional method (1), so a description thereof will be omitted.

FIG. 8 is a diagram showing the bus usage right determination result in the method of the present invention, and the meanings of symbols in the diagram are the same as in FIG. 3. It is also the same that the priorities are in the order of A, B, and C.

However, according to the method of the present invention, the right to use the continuous bus is limited to three cycles.

When comparing the conventional methods (1) and (2) with the method of the present invention, the method of the present invention is different in the following points.

■Continuous bus use is limited to a certain number of times, so one module will not monopolize the bus for a long time.

■However, as long as it is within the number of feet, a module with a lower priority can use the bus continuously in preference to other modules, so even a module with a lower priority can be interrupted by a module with a higher priority. Block data can be transferred without any hassle.

(2) Therefore, by appropriately selecting the limit number of times according to the content of the transferred data, it is possible to allocate bus usage rights to each module in a well-balanced manner.

(Effects of the Invention) As explained in detail above, according to the present invention, in the conventional method (1), continuous bus use is allowed by limiting the number of cycles, and for the continuous bus use, priority is given to the bus use of each module. Since absolute priority is recognized regardless of the order, continuous data transfer over multiple cycles is possible, and the necessary data transfer can be performed at once in one communication between modules that send and receive data, making it easy to see from the module side. The time required for one communication can be reduced, and additional transfer procedure control that occurs when one communication is divided into several transfer cycles can be eliminated. Further, data transfer of a module with a high priority is less likely to be made to wait due to data transfer of a module with a low priority, and efficient data transfer is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of a system related to the bus right determination method of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the arbiter 1o in FIG. 1, and FIG. 3 is the configuration of a shared memory access method. A block diagram showing an example, FIG. 4 is a diagram showing the bus usage right determination result in the conventional method (1), FIG. 5 is a diagram showing the bus usage right determination result in the conventional method (2), and FIG. 6 is a diagram showing the bus usage right determination result in the conventional method (2). FIG. 7 is a flowchart of the operation of the circuit of FIG. 2, and FIG. 8 is a diagram showing the result of determining the right to use the bus in the system of the present invention. 10...Arbiter, 11...Continuous bus use restriction means, 13...Continuous bus use permission means, 15+, 16+,...17. ...Individual bus use request line, 152.162. ...17□...Individual bus use permission line, 18...Continuous bus use request line, 19...Continuous bus use permission line. Bus cycle Bus cycle Bus cycle Pass cycle BREQ. REQn AND+73 Figure 6 Counter 21 ND26 GNT BGNT. Figure 7

Claims (1)

[Scope of Claims] In a bus usage right determination method in which bus usage rights are determined for each bus cycle in response to requests for use of a common bus from a plurality of modules, modules that have been granted permission to use the bus successively request access to the common bus. continuous bus use limiting means for limiting the number of bus cycles that can be used; and continuous bus use for a module that has been granted permission to use the bus to issue a request for continuous use and obtain permission to use the common bus in priority over other modules. A bus use right determining method comprising: a requesting means; and a continuous bus use permission means for granting permission to use the common bus within the limit of the number of bus cycles in response to the continuous use request.