JPH03282955A - Bus arbitration circuit - Google Patents

Abstract

PURPOSE:To remove the use of useless time at the time of accessing a bus from a CPU and to improve the processing capacity of the bus arbitration circuit by applying a bus request to a specific sequencer which does not correspond to a master when a bus request is not inputted from the master. CONSTITUTION:When none of bus requests BR1 to BRn are inputted, a priority encoder 40 transfers a bus request to a sequencer 500. After checking the input of a bus ground from other sequencers, the sequencer 500 outputs a bus ground BG0. When any one of the bus requests BR1 to BRn is inputted, the encoder 40 immediately aborts the output of the bus ground BG0 to the sequencer 500 and drives the sequencer corresponding to a selected bus request. Thereby, a bus ground is outputted from the sequencer concerned.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to improving the performance of bus arbitration in computer systems.

<Prior Art> Conventionally, there has been a computer system configured such that a plurality of masters are connected to one bus and the bus is shared to transfer commands and data. An example of such a system is shown in FIG.

Multiple (here n+1) masters 100°10
, ,． 10n are connected to one bus 201.

30 is a bus arbiter, which upon receiving a bus use request signal (bus request) from each master, determines the bus use status and, if available, sends a bus use permission signal to permit the master to use the bus. (Bass Grant). Only the master who has obtained the right to use the bus can use the bus 20.

The following steps are required when using the bus: When a bus request is issued from the master in question, the bus arbiter 30 determines the bus usage status, and if a master with a higher priority than the master in question is not using the bus, it issues the right to use the bus to the master in question. If this is the case, the master will not be given the right to use the bus.

Therefore, the master in question is granted the right to use the bus (
With the bus grant, I was able to use the bus for the first time.

<Problem to be solved by the invention> However, in computer systems, things that use the bus frequently, such as the central processing unit (CPU),
There is a problem in that the above-mentioned overhead for using the bus affects the processing capacity of the system.

The object of the present invention has been made in view of the above points, and is to eliminate wasted time when the CPU accesses the bus,
An object of the present invention is to provide a bus arbitration circuit that can improve processing performance.

<Means for Solving the Problems> The present invention for achieving such an object is based on bus requests (BRl.

It has a function to select and output the bus request with the highest priority among n masters (BR, , , BR), and also has a special function when none of these n masters has issued a bus request. a priority encoder (40) having a function of outputting a bus request; and a priority encoder (40) that outputs a bus grant upon receiving a bus request, the priority encoder (40) outputting a bus grant in response to the bus request from the master outputted from the priority encoder (40). n sequencers (501,
,,50) and the priority encoder (40
), all of the n sequencers (501, 50) access the bus 1°.
It is characterized by being equipped with a special sequencer (50°) that outputs the lowest priority bus grant when the n-ground is not being sent out.

In the present invention, when a bus request from a master is input to the priority encoder, a bus request with a high priority is selected and the bus request is given to the sequencer corresponding to the master, and the bus request is sent from the master to the sequencer corresponding to the master. If no request is input, the bus request is given to a special sequencer that is not compatible with the master.

By assigning the bus grant sent from this special sequencer to the most frequently used master, such as the CPU, that master can access the bus without bus arbitration. This eliminates wasted time when accessing the bus and improves processing performance.

<Example> The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a bus arbitration circuit according to the present invention. In the figure, 50. 50
, ,． 50 is the sequencer and 0 1'
n Bus request (BR) from master (not shown)
, BR, , , BR) comes, then ba1 2
This generates a sequence up to outputting 0 1 n of n sgellants (BG, BG, . . . , BG).

In particular, the sequencer 500 performs control to output bus grant 0 (BGo>) when a bus request is not input or a bus grant is not output to another master.

40 is a priority encoder, which selects the highest priority among the input bus requests.
It has the ability to select the highest value.

It is assumed that the priority of bus requests is that BRl is the lowest and BRn is the highest.

The output of the priority encoder 4o is inputted to each sequencer, and in particular, the sequencer 500 inputs the output of the priority encoder 40 as well as the output of each sequencer 5o1゜50, . The output from 50n is also input.

The sea urchin is turning.

The operation in such a configuration will be explained next.

- When none of the bus requests BR, BR, ..., BRn2 is input, the priority encoder 4o passes the bus request to the sequencer 5oo. Sequencer 50o confirms that there is no bus grant from another sequencer and outputs bus grant BGo. It is desirable to allocate this bus grant to the CPU, for example.

■Bus request BR, BR,,,,BR.

2, the priority encoder 40 immediately sends the bus grant B to the sequencer 5oo.
The GO output is stopped and the sequencer corresponding to the selected bus request is operated. This causes the sequencer to output a bus grant.

■When the sequencer that operated in (■) above finishes its operation, it starts the next arbitration. At this time, if any one of BR1 to BR1 is input, the operation is repeated from (2) above, and if not, the operation moves to (2) above.

<Effects of the Invention> As explained in detail above, the present invention has the following effects.

By assigning the bus grant BGO to the CPU, the CPU can access the bus without performing bus arbitration. Bus arbitration requires at least one clock cycle, but by using the bus arbitration circuit of the present invention, that time can be saved.The more frequently the bus is used, the greater the difference becomes. It also improves performance as a.

[Brief Description of the Drawings] Fig. 1 is a configuration diagram showing an embodiment of a bus arbitration circuit according to the present invention, and Fig. 2 shows an example of a conventional system configuration in which a plurality of masters are connected to one bus. It is a diagram. 40...Priority encoder, 500. 50, , . 500...Sequencer. 1. Figure 1 t, %9° possible 2::.

Claims (1)

[Claims] A bus arbitration circuit in which n masters are connected to one bus, and which accepts bus requests from each master and generates bus grants in descending order of priority, the bus arbitration circuit comprising: n masters connected to one bus; Bus request (BR_1, BR
It has the function of selecting and outputting the bus request with the highest priority among the bus requests (_2,...BR_n), and also outputting a special bus request when none of these n masters has issued a bus request. a priority encoder (40) having a function of outputting a bus grant; n sequencers (501,
...50n) and the priority encoder (4
A special sequencer that receives a special bus request from 0) and outputs a bus grant with the lowest priority when none of the n sequencers (50_1, . . . 50_n) is sending out a bus grant. (500), wherein a bang grant from the special sequencer (500) is assigned to the most frequently used master.