JPH023851A - Direct memory access device - Google Patents

Abstract

PURPOSE:To efficiently transfer data irrespective of the use state of a bus by providing plural request delay means which respectively delay requests given from a memory access control means to a bus jurisdiction control means for a set time. CONSTITUTION:Memory access means 14-1 to 14-n are provided for respective channels and the bus jurisdiction acquisition of the corresponding channel can be requested. When the acquisition of jurisdiction is allowed to the channel, the bus 10 is used and memory access is attained. Requests given form the memory access means 14-1 to 14-n to the bus jurisdiction control means 12 are respectively delayed by the set time by the request delay means 16-1 to 16-n. Consequently, the requests of high priority, which have been generated later, are delayed and even a channel with low priority, which has been generated earier, can use a space generated by delay and can obtain bus jurisdiction. Thus, efficient memory access in which bus jurisdiction is not occupied by the channel with high priority is attained.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art Problems to be Solved by the Invention Means for Solving the Problems Action Examples Effects of the Invention [Summary] Between multiple channels and memory The purpose of this technology is to provide a direct memory access (DMA) device that enables efficient data transfer regardless of the bus usage status. Bus control Il! for the channel with the highest priority among the channels involved in the request! A bus control right management means is provided for each channel, and
a plurality of memory access means for requesting acquisition of bus control over a corresponding channel, and performing direct memory access for the channel using the bus when acquisition of the control right for the channel is permitted; a plurality of request delay means each delaying the request given to the bus mastership management means by a set time.

[Industrial Field of Application] The present invention relates to a direct memory access device in which data is transferred between a plurality of channels and a memory using a DMA method.

This device can be used in systems that control a large number of lines, where each line is a separate channel.

Channels on which DMA transfer can be performed are determined in accordance with the priority order of obtaining the right to use the bus, and data transfer is often performed in single-step mode.

[Prior Art] FIG. 4 shows an example of a line control device that performs DMA transfer in single-step mode, in which a memory 40 (main memory) and an I10 register 42 of channel 1.2.3.4 are used.
DMA controller 44-L 44-2.44-
3.44-4, respectively.

and I10 register 42-1.42-2.42-3.
42-4 and other devices via the lines, and by performing the above data transfer, the data of each line is written to the memory 40,
Data in memory 40 is sent to each line.

It also acquires the right to use bus 46 and transfers data to memory 4.
Channels 1.0 and 0. 2. 3 or 4 is determined by the priority encoder/decoder 48, and the priority encoder/decoder 48 determines the channel for which the right to use can be acquired according to a truth table whose contents are shown in FIG.

These channels 1. 2. From the line side of 3.4 ■10
DMA controller 44-1.44-2.44-3 via register 42-1.42-2.42-3.42-4
．． 44-4 to the input/output request signal l10REQ1. l10R
EQ2. When l10REQ3゜l10REQ4 is given, the DMA controller 44-1.44-2.44-3
．． 44-4 to priority encoder/decoder 4
Request signal BREQ1.8 to acquire bus control right. BREQ2
゜BREQ3. BREQ4 is issued.

Bus 4 with its priority encoder/decoder 48
When the channel that can acquire control of 6 is determined according to the contents of Figure 5, the DMA of the corresponding channel is determined.
Controller 44-1.44-2.44-3 or 44-
Permission signal for acquiring bus control to 4 PRN-1, PRN-2
, PRN-3 or PRN-4 are output.

51st! 1 indicates that acquisition of bus control is permitted with a value of ``1'' and is not permitted with a value of ``0'', which can also be understood from the same figure (D>, (E), and (F)). As shown in the table, bus mastership is acquired by channel 1.channel 2.
．． Channel 3. Priority is given to channel 4.

The operation of this conventional example is explained in FIG. 6, where the bus 4
6 is empty when the bus signal BUSY in FIG. 6A is at H level.

And in the same figure (B), (C), (D), (E),
Request signal BREQI for acquiring bus control.

BREQ2. BREQ3. BREQ4 is sent sequentially from the DMA controller 44-1.44-2.44-3.44-4, and in this case, DMA transfer is performed first with channel l, which has the highest priority. It will be done.

When the DMA transfer is completed, channel 2 has the highest priority, so next, DMA transfer is performed with channel 2 as shown in FIG. 3(G).

When the data transfer with channel 2 is completed, the request signal REQI to acquire bus control is repeatedly issued from channel 1 in the single step mode as shown in (B) of the same figure, so as shown in (F) of the same figure. DMA transfer is started again in a leap with channel 1.

Therefore, as shown in (D) and (E) in the same figure, channel 3
, 4 to request signals BREQ3 and BRE for acquiring bus mastery.
Despite Q4 being issued, the same figure (H), (
As in 1), for those channels 3 and 4, the permission signal PRN3. PRN4 is not emitted, and D
MA transfer is not performed.

[Problem 3 to be solved by the invention As mentioned above, in the past, each channel and memory 40
When a single-step mode DMA transfer is started between the two channels, the bus 46 is occupied by a channel with a higher priority.

Therefore, a channel with a low priority for obtaining the right to use the bus cannot obtain the right to control the bus and cannot perform DMA transfer.

Therefore, even if a lower priority channel requests data transfer, only a small number of higher priority channels actually transfer data, reducing the overall efficiency of data transfer. do.

The present invention has been made in view of the above-mentioned conventional problems,
The purpose is to provide a direct memory access device that enables efficient memory access without allowing a channel with a higher priority to occupy control of the bus.

[Means for Solving the Problems] In order to achieve the above object, an apparatus according to the present invention is configured as shown in FIG.

In the bus control right management means (12) in the same figure, among the channels related to the request for bus control right acquisition, the bus control right management means (12)
Bus control management is performed in which a channel with a higher rank is allowed to acquire control of the bus 10.

Also, memory access means 14-1, 14-2...14
-n (44-1, 44-2, 44-3゜44-4...
- 44-15) is provided for each channel and can request acquisition of bus control of the corresponding channel, and when the channel is permitted to acquire the control, direct memory access can be performed using the bus 10.

And memory access means 14-1, 14-2...
14-n to the bus mastership management means 12, the request delay means 16-1, 16-2, . . . 16-
n, each is delayed by a set time.

[For 1] In the present invention, a request to acquire bus mastership for each channel is delayed, and therefore a later request with a higher priority is delayed.

Therefore, even a channel with a low priority that occurs first can acquire the right to use the bus by using the gap created by the above delay, and depending on the delay time setting, it is possible for each channel to access memory equally. .

[Embodiment] Hereinafter, a preferred embodiment of the apparatus according to the present invention will be described based on the drawings.

An example of a line control device is illustrated in FIG. 2, and in this example, the number of channels is 15.

Channel 1 is for HLD and is 48Kbp
It supports 4 lines of s.

Also channel 2. Channel 3...Channel 15 is a CD
It is said to be for T, and can support up to three lines in a 44-bit format of 1200 bps, for a total of 32 lines.

Here, the DMA controllers 44-1.44-2.44-3...44-15 for channels 1, 2.3...15
The bus mastership acquisition request signal BREQ1.
2.3φψ number 15 is delay circuit 50-1.50-2.50
-3...50-15 to the priority encoder/decoder 48, respectively.

These delay circuits 50-1.50-2.50-3...5
The signal delay time due to 0-15 is channel 1.2.3.
. . 15 is set so that bus control rights are equally distributed among the 15 terminals. Next, an example of the setting will be explained.

When accessing 16 bits = 1 word at a time in leapfrog with channel l, channel 1 has at least 83μ, as shown by the formula: 1000
It is necessary to acquire bus control rights every Sec.

Also, since CDT44bit is 2 words, 1
As shown by the formula: 000X100OX (44/2)200X3 =61 1 1 (μ5ec), channels 2.3...15 need to acquire bus control at least every 8111t1 sec.

If bus performance is required such that the bus occupation time required for each channel to perform input/output is roughly 2 μsec, then
In order to equally distribute bus control rights to 15 lines, a delay time of 30 μsec is required, as shown by the formula: 2×15=30(μ5ec).

The delay time (=30μ5ec) is the shortest access cycle of HDL and CDT (=83μSeC+=6111gs
ec) The request signal BREQI for acquiring bus mastery is shorter, thus 30 μsec.

BREQ2. By delaying BREQ3...BREQ15, it becomes possible to equally distribute bus control rights to all channels while satisfying the required performance.

The operation of this embodiment is explained in FIG. 3, which shows channels 1, 2, . 3.4 Bus control will be equally distributed.

Here, similarly to the conventional example, the same figures (B) and (C) are shown.

As shown in (D) and (E), the request signal BR for acquiring bus control right
EQ1. BREQ2. BREQ3. BREQ4 are generated sequentially, but they are delayed by the delay circuits 50-1, 50-2, .
50-3. Since it is delayed by 50-4, the same figure (B)
, (C), the request signals BREQI and BREQ2 are delayed by the required time (signals BREQ3, BREQ...
) Therefore, when the memory access of channel 1 is performed as shown in (F) in the same figure, and the memory access of channel 2 is performed as shown in (G) of the same figure,
), the request signals BREQI are delayed, so the competing request signals BREQ3 . B
Among REQ4, access to channel 3 with high priority is same 1! I (H) is allowed.

Even when the memory access is completed, the request signal BREQ1. BREQ2 is shown in the same figure (B).

As shown in (C), the signal BREQ4 is delayed from the signal BREQ4 in (E) of the same figure, so channel 4, which has the lowest priority, is allowed to acquire bus control as shown in (I) of the same figure, and this channel 4 memory accesses are performed.

Furthermore, during the access, the same t! The channel 1 request signal BREQI delayed as t (B) is provided to the priority encoder/decoder 48, so that channel 1 memory access occurs after channel 3.4.

As explained above, according to this embodiment, by delaying the request to acquire bus control by a predetermined period of time, the bus 46 is not occupied by a small number of specific channels (1, 2, . . . ). It becomes possible to equally distribute bus control rights to all channels 1, 2, 3, . . . -15.

Therefore, channels with different priorities l, 2゜3...
15 can equally access the memory, making it possible to perform data communication efficiently.

Further, according to this embodiment, the delay circuits 50-1. 50-2
．． 50-3...150-10 is DMA control -
La 44-1. 44-2. 44-3 dispute
Since it is provided on the 11444-15 side and not on the priority encoder/decoder 48 side, the delay time setting of the delay circuits 50-1.50-2.50-3...50-15 must be set to the corresponding line. This can be done easily depending on the situation.

In addition, delay time 50-1.50-2.50-3...5
A means corresponding to 0-15 is used as a priority encoder.
It is also possible to provide it on the decoder 48 side.

[Effects of the Invention] As explained above, according to the present invention, a request to acquire bus control is delayed by a predetermined period of time, so that direct memory access is performed between a plurality of channels and memory in a single step mode. Even in this case, a channel with a low priority can perform memory access, and therefore it is possible to avoid concentration of memory access on a channel with a high priority and improve the efficiency of data transfer of [i].

[Brief explanation of the drawing]

Figure 1 is a diagram explaining the principle of the invention, Figure 2 is a diagram explaining the configuration of the embodiment, Figure 3 is a diagram explaining the operation of the embodiment, Figure 4 is a diagram explaining the configuration of the conventional device, and Figure 5 is bus control. FIG. 6 is an explanatory diagram of the acquisition priority order, and FIG. 6 is an explanatory diagram of the operation of the conventional device. 40...Memory 42-1.42-2.42-3.42-4・Conflict・42-
15...I10 register 44-1.44-2.44-3.44-4・Φ・44-
15...DMA controller 46...φ bus 4th...Priority encoder fist decoder 50-1.50-2.50-3...-50-15...
・Delay circuit

Claims (1)

[Scope of Claims] A bus control right management means (12) for permitting the channel with the highest priority to acquire control of the bus (10) among the channels requested to obtain bus control; a plurality of memories that are provided in a corresponding channel and request acquisition of bus control of a corresponding channel, and perform direct memory access of the channel using a bus (10) when acquisition of control of the corresponding channel is permitted; Access means (14-1, 14-2...14-n), and memory access control means (14-1, 14-2...1)
a plurality of request delay means (16-1, 16-2, . . . , 16-n), each of which delays the request given from 4-n) to the bus mastership management means (12) by a set time; A direct memory access device characterized by: