JPS6280753A - Bus control system - Google Patents

Abstract

PURPOSE:To prevent a transfer request with high priority from being waited by interrupting burst data transfer and transferring the using right of a common bus to the other control device when the using right of the common bus is acquired and a transfer request is generated from the other control device having higher priority even during the transfer of burst data. CONSTITUTION:If an I/O control part 3-2 turns on a transfer request line RQ3 and requests data transfer during the transfer of burst data from an I/O control part 3-1, a microprocessor part 1 determines the priority every end of data transfer and applies the using right of the common bus 4 to a transfer requesting source. Thereby, the transfer request of the I/O control part 3-2 is accepted at the end of data transfer from the I/O control part 3-1. Since the priority of the control part 3-2 is higher than that of the control part 3-1, a common bus 4 use acknowledge line AK3 is turned on and the using right is applied to the control part 3-2.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a bus control system, and particularly to an information processing system having a common bus that is shared by a plurality of control devices for data transfer and whose usage rights are centrally managed by a management device. Regarding bus control method.

[Background of the invention]

Examples of methods for controlling the right to use the common bus include a method of allocating the right to use the common bus in a time-sharing manner, a method of fixedly determining the priority order of the right to use the common bus, and a method disclosed in Japanese Patent Laid-Open No. 56-971.
As described in Japanese Patent No. 29, a method of dynamically allocating common buses by sequentially switching the priorities of common buses in a cyclical manner is known.

However, some control devices transfer data in bursts, so even if there is a transfer request from a control device with a higher priority, the user must wait until the burst data transfer that has been granted the right to use the common bus is completed. The issue of priority processing sinking has not been resolved.

[Purpose of the invention]

An object of the present invention is to obtain the right to use the common bus, and to interrupt the burst data transfer if there is a transfer request from another control device with a high priority even during burst data transfer, and to give the other control device the right to use the common bus. The purpose of this method is to provide a bus control method in which high-priority transfer requests are not forced to wait.

[Summary of the invention]

The present invention provides an information processing system in which a plurality of control devices have a common bus that is shared for data transfer and a management device centrally manages usage rights, in which the management device determines priorities for transfer requests from any control device. , gives the applicable control device the right to use the common bus. Among the control devices, a control device that transfers burst data has two transfer request lines, and turns on the first transfer request line to transfer data. After this data transfer is completed, the first transfer request line is turned off, and in order to perform the primary data transfer, the second transfer request line is turned on and turned off after the data transfer is completed. In this way, the first and second two transfer request lines are alternately turned on and off, and the management device determines the priority according to the on and off of the transfer request lines and grants the right to use the common bus. As a result, the right to use the common bus can be occupied and burst data transfer can be performed. If there is a transfer request from another control device with a higher priority, the right to use the common bus of the control device that was transferring burst data is canceled based on the priority determination, thereby interrupting the burst data transfer and The feature is that the right to use the common bus is given to other control devices with higher priority.

[Embodiments of the invention]

An embodiment of the present invention will be described below.

FIG. 1 is a diagram showing an example of the configuration of an information processing system to which the present invention is applied. In FIG. 1, a microprocessor section 1. Memory section 2. Input/output control units 3-1 and 3-
2 are interconnected via a common bus 4. Data transfer between these units is performed via a common bus 4.

The right to use the common bus for these data transfers.

It is centrally managed by the microprocessor section 1.

When a transfer request is received from the input/output control units 3-1 and 3-2, the microprocessor unit 1 determines the priority of the transfer request if a common bus can be used, and requests the source of the transfer request to use the common bus. The common bus is made to wait for transfer requests from other input/output control units until the data transfer is completed.

The input/output control unit 3-1 is an input/output control unit that transfers burst data, and uses a transfer request line (RQI).

The microprocessor section 1 has two common bus use permission lines (AKI, AK2) corresponding to the two common bus use permission lines (AKI, AK2). The input/output control unit 3-2 is an input/output control unit that does not transfer burst data, and has a transfer request line (
RQ3) is one line, and the corresponding common bus use permission line (AK3) from the microprocessor section 1 is one line. Regarding the priority of the right to use the common bus 4, the input/output control section 3-2 has a higher priority than the input/output control section 3-1. Now, the input/output control section 3-1 turns on the transfer request line (RQI) to perform data transfer, and requests the microprocessor section 1 to use the common bus. The microprocessor unit 1 turns on the use permission line (AKI) in response to the transfer request line (RQI) to permit use of the common bus 4.

The input/output control unit 3-1 starts data transfer using the common bus 4 upon receiving the enable line (AKI) ON. When the data transfer is completed, the input/output control section 3-1 turns off the transfer request line (RQI), turns on the transfer request line (RQ2), and again requests the microprocessor section 1 to use the common bus. The microprocessor unit 1 has a transfer request line (RQ
2), the use permission line (AK2) is turned on as a response to permit use of the common bus 4. Input/output control section 3
-1 starts data transfer using the common bus 4 upon receiving the use permission line (AK2) ON. When the data transfer is completed, the input/output control unit 3-1 connects the transfer request line (RQ2)
Turn off.

In this way, the transfer request line (RQI,
By turning RQ2) on and off alternately and continuously, the common bus 4 can be occupied and burst data transfer can be performed.

While the input/output controller 3-1 is performing burst data transfer in this state, the input/output controller 3-2 turns on the transfer request line (RQ3).

When a data transfer is requested, the microprocessor unit 1 determines the priority every time the data transfer is completed and grants the transfer request source the right to use the common bus 4. When the transfer request is completed, the transfer request from the input/output control unit 3-2 is accepted, and the transfer request from the input/output control unit 3-2 is accepted.
-2 has a higher priority than the transfer request of the input/output control unit 3-1, so the permission line (AK3) for use of the common bus 4 is turned on and the right to use the common bus 4 is given to the input/output control unit 3-2.

According to the method described above, the burst data transfer of the input/output control unit 3-1, which is a control device that transfers burst data, is interrupted, and the right to use the common bus is given to the input/output control unit 3-2, which is another control device. be able to. This is effective in preventing transfer requests from other high-priority control devices from sinking due to burst data transfer.

〔Effect of the invention〕

As described above, according to the present invention, even if there is a control device that transfers burst data among a plurality of control devices connected to a common bus, transfer requests from other control devices with higher priority On the other hand, it is possible to interrupt the data transfer in berth 1 and hand over the right to use the common bus, which reduces the waiting time before using the common bus and improves the response performance of high-priority processing, which is extremely effective. It is true.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an information processing system that is a subject of the present invention, and also shows the configuration of an embodiment of the present invention. ■...Microprocessor section, 2...Memory section. 3-1.3-2...Input/output control unit, 4...Common bus/do:?・6'

Claims (1)

[Claims] In an information processing system having a common bus that is shared by a plurality of control devices for data transfer and whose usage rights are centrally managed by a management device, the management device assigns priorities to transfer request signals from the plurality of control devices. is provided with a circuit that gives the corresponding control device the right to use the common bus and holds the right to use the common bus until the transfer request signal is released, and at least one of the control devices has two transfer request signal lines and transmits data. A bus control method characterized in that a transfer request signal is alternately turned on and off for each transfer, and the management device gives the right to use the common bus to another control device with a higher priority when switching the transfer request signal.