JPS6133560A - Data transfer circuit - Google Patents

Abstract

PURPOSE:To prevent a bus from long occupation and to improve the using efficiency of the bus by transferring data intermittently when the large volume of data are to be transferred. CONSTITUTION:An oscillator 5 of which oscillation frequency and duty ratio can be set from the external is formed. When a transfer request signal is outputted from a memory or an I/O, AND between a bus using request signal outputted from a data transfer control circuit 4 and an oscillation output from the oscillator 5 is found out by an AND gate 6 and outputted as a bus request signal. Only in the period that the AND is ''1'', the bus is used and data is transferred, and in the ''0'' period, the bus is made idle to be used for other devices.

Description

TECHNICAL FIELD The present invention relates to a data transfer circuit, and more particularly to a bus data transfer circuit in a microcomputer system.

Conventional microcomputer systems usually use a configuration in which devices such as a CPU, a memory, and a processor 10 are connected on a common bus. In other words, as shown in FIG. The CPU 1, the memory 2, and the data transfer control circuit (DirectMemory Access
Memory spanning I via Controller) 4
lo 3 is connected. bus 9 and memory or I
There is an address/data control line between the LO3, a bus control line between the bus 9 and the data transfer control circuit 4, and a bus control line between the data transfer control circuit 4 and the memory or f103. In FIG. 3, for example, when N words of data are to be transferred from the memory or the memory 103 to the memory 2, there are three conventional transfer methods:

(1) For each word transfer, a bus access request is sent to CPU1 (
(or a bus arbiter (not shown)), and if permission is granted, the sending is stopped; (li) sending a bus access request by dividing it into a certain number of data blocks, and dividing it into N
(iii) Once the right to use the bus is obtained, the bus is used exclusively to transfer all data at once.

FIGS. 4 and 5 are explanatory diagrams of the transfer method (i) above.

Now, when trying to transfer a large amount of data (N words) from the memory or rlo 3 to the memory 2, the memory master first sends a transfer request signal (REQUEST) from the memory to the data transfer control circuit 4 (see Fig. 4). .

(See Figure 5). Accordingly, the data transfer control circuit 4
A bus request signal (BREQ) is sent out for each word. C.P.
By sending a bus permission signal (BPRN) from U1 (or a bus arbiter not shown) to the data transfer control circuit 4, data is transferred from the memory or Ilo 3 to the memory 2 via the address/data control line. Transfer one word of data.

As shown in FIG. 5, data transfer is executed by repeating this N times.

However, in the method (i) above, it takes N times to acquire the right to use the bus, and the waiting time between those attempts becomes long. That is, as shown in FIG. 5, data transfer is performed at the same time as the bus permission signal (BPRN) is received, but a waiting time for waiting for a vacant bus is inserted every time one word of data is transferred. As a result, bus usage efficiency deteriorates.

In addition, according to the method (100) above, bus
In the method of issuing an access request, it is necessary to count data for each data block, resulting in a large overhead.

Furthermore, in the method (iii) above, in which the bus is used independently, the bus usage efficiency increases, but other control devices connected to the bus cannot use the bus during that time.
Processing is inhibited.

Purpose An object of the present invention is to provide a data transfer circuit that can improve the problems of the conventional art and that can improve bus usage efficiency without monopolizing the bus for a long time even when transferring a large amount of data. Our goal is to provide the following.

Configuration In order to achieve the above object, the data transfer circuit of the present invention has the following features:
In a processing system having a bus structure used by two or more bus masters, an oscillator whose oscillation frequency and duty ratio can be set arbitrarily from the outside, and the oscillation output of the oscillator and bus usage requests from the bus masters. It is characterized in that it has means for performing a logical product with a signal, and data is transferred using a bus only when the result of the logical product is n1)I.

Hereinafter, the configuration of the present invention will be explained using examples.

FIG. 1 is a block diagram of a data transfer circuit showing one embodiment of the present invention, and FIG. 2 is an operation time chart of FIG. 1.

In FIG. 1, 4 is a data transfer control circuit, 5 is an oscillation circuit whose oscillation frequency and duty ratio can be set, 6 is an AND gate, 9 is a common bus, and there is also a third bus (not shown). As shown in the figure, the memory is ■/103
, memory 2, and CPU 1 are connected.

In the present invention, an oscillator 5 whose oscillation frequency and duty ratio can be set externally is provided, and when a transfer request signal (REQUEST) is received from the memory or the device 103, a bus use request signal (REQUEST) is sent from the data transfer control circuit 4.

BREQ) and the oscillation output from the oscillator 5 are ANDed to obtain a bus request signal (BREQ'). The bus is used to transfer data only during the period when the AND result is "1", and the bus is freed for other devices (bus master) during the to-on period. In other words, even if a bus usage permission (BPRN) is sent, data is transferred intermittently without monopolizing the bus continuously, so that the bus is always interrupted by another device (bus master) on the way. Be able to accept usage requests.

As shown in FIG. 2, the load on the bus varies depending on the situation, but it can be used at a rate of tz/(tx + tz).

The oscillator 5 has an oscillation frequency '/(Lx+
t2) (Hz) and duty ratio t2/
By setting (t1+t2), t1=ato" and t2=="l"' are output as the oscillation output OSC.

Here, the period t1=''0'' is the time to release the bus for another bus mask (for example, CPU1).
, t2="1" is the time during which this data transfer circuit uses the bus.

When the transfer request signal (REQtJEsT) is input, the data transfer control circuit 4 outputs the bus request signal (BREQ). As shown in Figure 2, the bus request signal (BRE
Q) does not need to be separated into individual words. However, in order to automatically output an intermittent request signal, the output signal from the oscillation circuit 5 (OSC) and the bus request signal (B REQ ) are ANDed and the bus request signal (BRE(r) As a result, the output (OSC) of the oscillation circuit 5 becomes “1”.
Data transfer is performed for a period t2, and the output (OSC
) during period t] of tlOII, data transfer is interrupted and the bus is handed over to another bus master.

As is clear from a comparison of the time charts in Figures 2 and 5, in Figure 5 a waiting time is inserted for each word transferred, whereas in Figure 2 a wait time is inserted for each word transferred (in Since only a waiting time is inserted each time data is transferred, bus usage efficiency is improved. Furthermore, since data is transferred only during the t2 period of the output of the oscillation circuit 5, and the number of words during that period is fixed, there is no need to count the number of block transfers. Furthermore, by making the oscillation frequency and duty ratio of the oscillation circuit 5 variable, data transfer can be performed in accordance with the frequency of use of the bus.

Effects As explained above, according to the present invention, even when transferring a large amount of data, the data is transferred intermittently, so the bus is not monopolized for a long time, and therefore other buses
It is possible to improve bus usage efficiency without interfering with the master.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data transfer circuit showing an embodiment of the present invention, FIG. 2 is an operation time chart of FIG. 1, and FIG. 3 is a block diagram of a microcomputer system.
Figure 4 is a block diagram of a conventional data transfer circuit;
The figure is an operation time chart of FIG. 4. 1: CPU, 2: Memory, 3: Memory or Ilo, 4
: data transfer control circuit, 5: oscillator, 6: AND gate, 9: common bus. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Wait time Data transfer in progress

Claims (1)

[Claims] In a processing system having a bus structure used by two or more bus masters, an oscillator whose oscillation frequency and duty ratio can be set arbitrarily from the outside, and the oscillation output of the oscillator and a bus use request signal from the bus masters are provided. What is claimed is: 1. A data transfer circuit comprising: means for calculating a logical product; and data is transferred using a bus only when the result of the logical product is "1".