JPS6079455A - Bus controlling system - Google Patents

Abstract

PURPOSE:To suppress to the minimum a drop of a performance caused by an extension of a bus length by connecting two common buses through a register, and assigning a use right of the bus by using two control signals for controlling a transfer between both the buses. CONSTITUTION:A main storage device 1, a bus controller 2, and bus controller operation processors 3, 4 are connected to a common bus 7, input/output control devices 4-6 are connected to the second common bus 8, and a repeating register 9 is connected between both the buses 7, 8. Bus use right request signal lines 10, 11 are connected to the bus controller 2 from each device. When a bus use right is requested, the bus controller 2 gives a bus use right to the device having the highest priority order in accordance with a prescribed rule. In this state, in order to transfer a data to the device connected to the common bus 8 from the device connected to the common bus 7, the first control signal for activating the common bus 8 is used, and in the contrary case, the second control signal is used, and a performance drop caused by an extension of a bus length is suppressed to the minimum by controlling this signal in accordance with an assignment of a bus use right.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus control method in an information processing device.
As shown in the figure, a large number of main memory units (hereinafter referred to as MMU), bus controllers, arithmetic processing units (hereinafter referred to as EPU), input/output control units (hereinafter referred to as 10P), etc. are connected to one common node.

This method generally allows easy connection of many of the above devices. There is no problem when there are few connected devices, that is, when the bus length is short.However, as the number of connected devices increases, the bus length becomes longer, and as a result, waveforms may become distorted due to bus signal reflections, etc. This method has the disadvantage that the delay time including the delay time increases and the bus transfer speed decreases.

Moreover, this increase in delay time is the same whether the distance between two devices on the bus requiring bus transfer is large or small.

Referring to FIG. 1, even if there are frequent bus transfers between MMU 1 and BPU3, which have a small distance between devices, and almost no bus transfers between MMU1 and 10Pn6, which have a large distance between devices, MMYi and EPU3 Since the bus transfer speed of the EPU 3 of the entire system is not required, its mere existence contributes to the lengthening of the bus and reduces the bus transfer speed of the entire system. We should pay particular attention to the layers.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a bus side diagonal system that can eliminate the above-mentioned drawbacks and minimize the performance deterioration caused by the length of the bus.

Structure of the Invention The method of the present invention includes: a main storage device, at least one arithmetic processing device, a plurality of input/output control devices, and among the main storage device, the arithmetic processing device, and the plurality of input/output control devices. At least some parts are connected in common n
a first common bus connected to the first common bus, a relay register connected to the first common bus, and a second common bus to which the relay register and the rest of the plurality of input/output control devices are connected in common. , for activating the second common bus in order to transfer information from any device connected to the first common bus to any input/output control device connected to the second common bus. a first control signal line for transmitting a first control signal; and an arbitrary device connected to the i1 common bus from one of the input/output control devices connected to the second common bus. a second control signal line for transmitting a second control signal for activating the common bus of the Ml in order to transfer information; It is characterized by control.

Examples of the invention Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 2, one embodiment of the present invention.

MMUI, bus controller 2. EPU3. ．． 10PO
4. First common bus 7°l0PI connected to devices 1-4.5.・l0Pn6. These devices 5-6
a second common bus connected to 8. A relay register 9 connected to the first common bus 7 and the second common bus 8. EP
U3. A bus right request signal line 10° that transmits bus right request signals from l0PO4, l0P15, and l0Pn6 to the bus controller 2, and a bus right request signal line 11 that transmits a bus right request signal from MMU1 to the bus controller 2. It consists of

The bus controller 2 connects each device 1-6 including MMU1.
It receives n bus right-to-use request signals given through bus right-to-use request signal lines lO and 11 from Grant the right to use the bus.

Next, the configuration of the relay register 9 shown in FIG. 2 will be explained in detail using FIG. 3.

Referring to FIG. 3, the relay register 9 has terminals 31,
32,33 and 34,7 lip flops 35 and 3
6. Bus drivers 37-1 and 37-2. and bus drivers 38-1 and 38-2.

The terminal 31 is connected to a first common bus, and the terminal 32 is connected to a second common bus. The terminal 33 is m
Similarly, the terminal 34 is a receiving terminal for the second control signal.

A flip-flop (hereinafter referred to as F/F) 35 is a relay register for bus transfer from the first common bus 7 to the second common bus 8; The F/F 36 is a relay register for bus transfer from the second common bus 8 to the if common bus 7. Each serves to store information on the bus during bus transfer between the first common bus 7 and the second common bus 8.

The control signal il is a signal for activating bus transfer from the first common bus 7 to the second common bus 8. During bus transfer from the first common bus 7 to the second common bus 8, True tri-state bus driver 37-1. and 37-
2'(j enable.

When the bus is transferred from the second common bus 8 to the first common bus 7, it is set to false, and the bus 2 IPA 37-1. and 37
-2 is disabled.

The second control signal is a signal for activating bus transfer from the second common bus 8 to the first common bus 7, and is a signal for activating bus transfer from the second common bus 8 to the first common bus 7. , true and trough state bus drivers 38-1 and 38-2
enable.

On the other hand, during bus transfer from the first common bus 7 to the second common bus 8, the flag is set to false to disable the bus drivers 38-1 and 38-2.

In FIG. 2, the result of bus usage right allocation, for example, MM
When bus transfer from Ul to l0P15 is required, the desired bus transfer can be performed by setting the first control signal to true and the second control signal to false. Also, l0P
When bus transfer from n6 to MMU 1 becomes necessary, desired bus transfer can be performed by setting the second control signal to true and the first control signal to false.

Now, the position of the relay register 9 in Fig. 2 is set so as to maximize the performance of the devices connected to the common bus 7 of Ml, such as MMU1, EPU3゜l0PO4, etc., which require the minimum necessary and high bus transfer speed. Set at a suitable location (bus length).

In this way, bus transfer between devices connected to the first common bus can be performed at high speed without being affected by devices connected to the second common bus.

According to the invention, the first common bus 7 and the second common bus 8
and a first common bus 7 via a relay register 9.
It has a control signal for activating the second common bus 32 in order to transfer data from any device connected to the input/output control device connected to the second common bus 8. , and to transfer data from one of the input/output control devices 4, 5, and 6 connected to the second common bus 8 to any device connected to the common bus 7 of the IL.
The bus has a second control signal that activates the common bus 7, and by controlling the control signal in accordance with the bus usage right allocation 2, performance degradation due to bus length extension is minimized. Is possible.

Effects of the Invention The present invention provides control signals 1. for connecting a first common bus and a second common bus via a relay register to control transfer between the first common bus and the second common bus. By providing the signal 2 and controlling this signal in accordance with the allocation of bus usage rights, it is possible to minimize the deterioration in performance due to the extension of the bus length.

[Brief explanation of drawings]

FIG. m1 is a diagram showing a conventional bus system, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing a detailed configuration of the relay register of the embodiment shown in FIG. In Fig. 3, 31.. old terminal connected to the first common bus, -32.. terminal connected to the second common bus, 33.. control of ml. signal receiving terminal,
34...Second control signal receiving terminal, 35.36
...Flip-flop, 37-1.37-2.
38-1゜38-2... Bus driver.

Claims (1)

[Scope of Claims] A main storage device, at least one arithmetic processing device, a plurality of input/output control devices, and at least one of the main storage device, the arithmetic processing device, and the plurality of input/output control devices. A common bus of il that is commonly connected to the first common bus, a relay register j that is connected to this first common bus, and this relay register and the rest of the plurality of input/output side devices are commonly connected. The second one to do 1! bus, and any device connected to said first common bus and any input/output signal connected to said second common bus. ) A first control signal line that transmits a first control signal for activating the common bus of the PEN 95. In order to transfer information from one of the input/output control devices connected to the second common bus to any device f′ connected to the first common bus, A second control signal line for transmitting a control signal of m2 is controlled to control the first and second control signals in accordance with assignment of the right to use a bus.