JPH02144652A - Bus arbitration system - Google Patents

Abstract

PURPOSE:To rationalize the arbitration of bus using right by changing bus acquisition priority in accordance with data volume stored at present in a first in first out (FIFO) storage device to apply the bus using right. CONSTITUTION:When three bus masters compete with each other and the bus master 1 (21) with the highest priority frequently requests the bus and occupies it, the bus master 3 (23) can not process the output data of an I/O device 4, so that unprocessed data are stored in the FIFO 3. When the number of data stored in the FIFO 3 exceeds a certain fixed value (stored volume generating the probability of data loss), a data storage state signal LS is turned to '1' and the bus priority is changed. Thereby, the bus master 3 (23) can process the data of the I/O device 4 without losing it.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for arbitrating bus usage rights between a plurality of bus usage devices, bus usage rights when a bus usage device having a first-in, first-out storage device is included among the plurality of bus usage devices. day and evening transfers through a common bus, with the aim of streamlining the mediation of In a system in which at least one of the 3f number of bus-using devices has a first-in, first-out storage device, the first-in, first-out storage device is provided with a circuit that generates a signal indicating the data accumulation state, and the first-in, first-out storage device is provided with a circuit that generates a signal indicating the data storage state, and A bus arbitration circuit that arbitrates bus use; A priority determination circuit that changes bus acquisition priority according to the value of a de-bust status signal output from the first-in, first-out storage device;
According to the data currently stored in the first-in, first-out 2 storage device, the lotus W11% f! E Configure the system to change the priority and grant bus usage rights.

[Industrial application field]

The present invention relates to data transfer processing on a data transfer bus, and particularly relates to data transfer processing when there are a plurality of bus-using devices, and one or more of the bus-using devices has a first-in, first-out storage device.

[Prior Art] As shown in Fig. 5, there is a method for arbitrating bus usage between devices using the bus in a system in which a plurality of devices use a bus to transfer data to and from memory. There is a method that uses a bus arbitration circuit. Each device using the bus receives a bus request signal BR when there is a request to use the bus.
I, BR2, and BR3, and when there are multiple bus requests at the same time, the bus arbitration circuit determines the bus usage device to be given the right to use the bus according to the priority, and sends the bus permission usage permission signal BGI or BGI to the next bus usage device. Send BO2 or BO2.

In such a system, if one of the bus-using devices has a first-in first-out storage device (hereinafter abbreviated as FIFO), the following problem occurs.

That is, in a device such as an image scanner, which needs to transfer a large amount of data at high speed during image scanning, a FIFO is provided for buffering, and the right to use the bus is obtained to transfer the data to memory.

In a data transfer circuit that transfers FIFO data,
When the data transfer speed of an input/output device (hereinafter abbreviated as Ilo) increases, or when a device using the bus with a higher priority than this circuit (issues a bus use request to the bus arbitration circuit, obtains permission to use the bus, and uses the bus) I1 is a device that transfers data using the I1
If 0 data is not transferred to memory and exceeds the FKFO's allowable storage amount, data will be lost.

In the conventional technology, the priority of each bus master is determined by assuming such a special state. That is, it was decided to give a high priority to the data transfer circuit having FiFO.

[Problem to be solved by the invention]

According to the above-mentioned conventional technology, since the priority of each bus master is fixed, the transfer circuit having FIFO is Must have higher priority than other bus masks,
Another problem is that the bus efficiency of other bus masks decreases during normal operation when the bus priority is set to cope with special operations (for example, during image data transfer).

An object of the present invention is to solve these conventional problems and provide a bus arbitration system with high bus efficiency.

[Failure to solve the problem]

FIG. 1 is a block diagram showing the configuration of the present invention.

In the figure, 1 is a bus arbitration circuit.

2. 2z and 2s are bus masters (bus use!
Bus master 2. is first-in-first-out storage (FIFO) 3
is connected, and temporarily stores data output from the input/output device 4.

The FIFO3 is equipped with a circuit that generates a data storage state signal Ls.

Reference numeral 11 denotes a bus use device determining circuit, which changes the bus acquisition priority according to the value of the charge storage state signal Ls output from the first-in, first-out storage device 3 and determines the right to use the bus.

[For production]

As shown in FIG. 1, three bus masters 2. .

2□, 2. When the bus needs to be used, the bus request signals BR] and BR] are sent to the bus arbitration circuit, respectively.

Send BR2 and BR3. When there is a plurality of bus masters that have raised the bus request signal, the bus arbitration circuit 1 determines a bus mask from among them based on the priority, and sends out a bus use permission signal BGI, BO2, or BO2. The bus master receives the bus use permission signal and uses the bus to transfer data.

The bus use device determination circuit 11 in the bus arbitration circuit l determines the bus use device to which the right to use the bus is granted.
Check the value of the data accumulation status signal Ls from
0" (data accumulation is below a certain value), for example, bus master 1>bus master 2>bus master 3, and 1" (data accumulation exceeds a certain value), bus master 3>bus master 1>bus master 2. Change to

If three bus masks compete and the high-priority master t(2+) makes frequent bus requests and monopolizes the bus, bus master 3 (L) cannot process the output data of input/output device 4. , unprocessed data is stored in FIFO3. When the number of data stored in the FIFO 3 exceeds a certain value (storage ff1 at which there is a possibility of data loss), the data storage state signal Ls becomes "1" and the bus priority is changed as described above. Thereby, the bus mask 3C2,) can process the data of the input/output device 4 without loss.

〔Example〕

The gist of the present invention will be explained in more detail below with reference to embodiments shown in FIGS. 2 to 4.

FIG. 2 is a diagram showing the configuration of an embodiment of the present invention.

This embodiment constitutes a system that processes and edits image data generated by an image scanner.

Reference numeral 21 denotes a memory refresher circuit that refreshes the memory 50. 22 is an image data processor that edits image data. 23 is an image data expansion/compression processor that processes image data.

24 is a memory 5 independent of the operation of the processors 22 and 23.
0 and a first-in first-out storage device (F I FO) 30.
MAC).

Memory refresh circuit 21, image data editing processor 22, image data expansion/compression processor 23
and DMAC 24 are bus masters that transfer data to and from the memory 50 through the bus, and for convenience, these are M 1 (21), M2 (22), M3 (2
3), M4 (24).

30 is a first-in, first-out memory bag W (FIFO) that temporarily stores the output data of the image scanner;
It has a capacity of 64 stages (64 bytes), and the data can be stored in 3
When the second stage (32 bytes) is exceeded, a half-full signal Hf signal which has a 1" roar is generated. In this embodiment, this half-full signal Hf is used as the data accumulation state signal Ls.

lO is a bus arbitration circuit, which includes a bus mask determination circuit 11,
Bus request register 12 and bus use permission register 13
It is equipped with

The bus mask determination circuit 11 sets the normal state (
When Hf=0), Ml>M2>M3>M4, and in the special state (Hf=1), Ml>M4>M2>
It is set to be M3. That is, since memory refresh must be performed within a certain interval, it is given the highest priority, and the DMAC is given a lower priority than the processor in a normal state, and is changed to a higher priority than the processor in a special state.

When two or more bus request signals (BRI to 4) are "1" in the bus request register 12, the Hr times signal from the FIFO 30 is checked, the priority is determined according to the value, the bus master is determined, and the bus is used. The corresponding bit of the permission register 13 is set to "1'°.

The bus master's bus permission signal corresponding to that bit is 1''
becomes.

Now, when the image data editing processor 22 (M2) is operating and accessing data on the memory 50, the image scanner 40 performs a scanning operation and the image data is DMA-transferred by the DMAC 24, the memory refresh circuit 2NM1) , image data editing processor 22 (M2), and 1) MAC 24 (M4), a bus competition occurs.

At this time, the image data editing processor 22 (M2)
I) M A C24C due to frequent lotus requests.
24(), the DMA transfer speed decreases.

Therefore, as shown in the time chart of FIG. 3, image data is accumulated in the FIFO 30, and the half-full signal Hf exceeds 32 hides at a point not indicated by pl in FIG.
0” to “1°”.

As a result, the bus master determination circuit 11 changes the bus acquisition priority to the special state (lIf-1).

Therefore, the priority of M4 becomes higher than M2, and the bus occupancy rate for DMA transfer improves, so that the data in the FIFO 30 is transferred without being lost. (If 'a' is the usual priority, BO2 is a broken line (#A in the diagram)
Therefore, M4 can only be transferred after M2. ) When the amount of data stored in FIFO30 decreases, P2 in Figure 3
At the point indicated by , the number is 32 bytes or less, and the half-full signal H
f becomes °'0'', and the priority of DMAC24 (M4) becomes low.

FIG. 1 is a flowchart showing the operation of the bus arbitration circuit in one embodiment of the present invention. (2) Checking the bus request register to identify whether there is a bus request. If there is a bus request, proceed to step (2), and if there is no bus request, return to step (2).

(2) Identify whether there are two or more bus requests. If there is one bus request, proceed to step (2); if there are two or more, proceed to step (2).

■Determine the requested bus mask as the person granting the right to use the bus.

(2) Identify whether the half-full signal Hf from the FIFO is "1". If it is ``l'', proceed to step ■ and 0'''
If so, proceed to step ■.

■Set the bus acquisition priority to "special status".

■Set the bus acquisition priority to "normal state".

■Determine the bus mask with the highest bus acquisition priority as the bus use right granter among the 7 bus stars for which the bus request was made.

- Set "1" to the bit corresponding to the person who has granted bus usage rights in the bus usage permission register.

(2) Identify whether the bus request of the bus mask during bus use in the bus request register has fallen to "0".

If it becomes "0", proceed to step (2), and if it remains "l", repeat this step.

Clear the 0φ lotus use permission register °゛l゛ and return to step ①.

[Effect of invention]

As is clear from the following explanation, according to the present invention, 1. bus arbitration is performed, and the bus use priority is changed using the data storage status signal of FIFO in the 1st route; ,
Then, FI F It is also said that lotus can be processed with high utilization efficiency.21.It has great industrial effects.

[Brief explanation of the drawing]

FIG. 1 is a one-by-one diagram showing the structure of the present invention. The second diagram shows the configuration of an embodiment of the present invention, and the third diagram shows an example of the operation according to one embodiment of the present invention. A flowchart showing the operation, FIG. 5 is a diagram showing an example of the bus arbitration circuit. In the figure, 1.10 is a bus arbitration circuit, 2, . 2t, 2. is a bus-using device, 3.30 is a first-in first-out storage device (F I FO), and 4
is an input/output device, 40 is an image scanner, 5
．． 50 is a memory, 11 is a bus use device (bus mask) determining circuit, 21 is a memory refresh circuit (Ml), 22 is an image data editing sensor (M2), and 23 is a 1 image data expansion/compression processor ( M3), 24 is DMAC (M
4), Ls is a data accumulation state signal, and Hf is a half-full signal. A block diagram showing the configuration of the present invention. A flow chart showing the operation of an embodiment of the present invention! A diagram showing an example of an IS bus arbitration circuit.

Claims (1)

[Claims] In a system in which at least one of a plurality of bus-using devices (2_1, 2_2, 2_3) that transfer data through a common bus has a first-in, first-out storage device (3), the first-in, first-out storage device (3) The bus arbitration circuit (1) includes a circuit that generates a signal (Ls) indicating the data accumulation state, and the bus arbitration circuit (1) arbitrates bus usage between the respective bus usage devices (2_1, 2_2, 2_3). A bus use device determination circuit (11) is provided which determines the right to use the bus by changing the bus acquisition priority according to the value of the data storage status signal (Ls) output from the device (3), and the first-in first-out storage device (3) A bus arbitration method characterized in that the bus acquisition priority is changed in accordance with the amount of currently stored data to grant the right to use the bus.