JPS626359A - Bus control system - Google Patents

Abstract

PURPOSE:To attain the common control of a proper common bus among units in a bus control system by changing periodically the priority of own unit when the unit having an access information stack uses no access information stack. CONSTITUTION:When a unit UA is unable to use an access information stack 17, the unit UA turns on and off alternately a priority control line PRIC in a fixed cycle via a priority control circuit 14. The circuit 14 of the unit UA holds the ON state of the line PRIC and then turns off the PRIC after the end of the processing when the circuit 14 knows an access request given from another unit to the unit UA for a period when the PRIC is kept on. While other units UB and UC are unable to acquire the bus using right when the PRIC is kept on. Then the highest order unit acquires the bus using right while the PRIC is kept off.

Description

[Detailed description of the invention] 〔overview〕 Among multiple units that share a common bus.

When a unit that has a stack that temporarily holds access request information cannot use that stack.

By periodically changing the priority of bus usage, it is possible to operate normally without using the stack.

[Industrial application field]

The present invention relates to a bus control method in a computer system, and particularly to a bus control method with priority control for sharing a bus by a plurality of units.

[Conventional technology]

FIG. 4 conceptually shows an example of a conventional system in which a plurality of units transmit data via a common bus.

In the figure, 40 is a common bus, and 41 to 43 are units UA, UB connected to the common bus 40, respectively.
UC, 44 represents a bus control line, 45 to 47 are priority control circuits, and 48 represents an access information stack.

When each of the units UA, UB, and UC needs to transmit data with other units.

A request signal is sent to other units via the bus control line 44 to request use of the bus.

Unit 1 - UA, UB, UC priority control circuits 45.4
6.47 examines the request signal of its own unit and the request signal from other units, and when its own unit has the highest priority, acquires the right to use the bus and uses the bus in the first cycle.

Transmit data.

The priority for bus use requests can be set in various ways, such as the level of the request source unit and the level of the access destination unit, but here, UA has the highest priority, followed by UB and UC. It is assumed that there is

Furthermore, in the illustrated example, an access information stack 48 is provided within the unit UA. This is used to temporarily hold access information when the unit UA is unable to immediately process the access when the unit UA is accessed by another unit.

This access information stack 48 has a plurality of storage locations, and stores access information from a plurality of units to the unit U.
A is held in the order of access until it can be processed.

As a result, other accessing units that have acquired the right to use the bus for accessing unit UA and have transferred access information can use the common bus without waiting until the processing is completed if unit UA cannot immediately process the access. This can increase the efficiency of common bus use.

Next, explanation will be given using a specific example.

FIG. 5 is a time chart showing the operation of the common bus when the stack is available.

In the figure, BUSBY (■) is a control signal indicating whether or not to use the common bus in the next cycle.

UA-REQ, UB-REQ, and UC-REQ in (2) are request signals indicating access requests from units UA, UB, and UC, respectively, and CBUS (2) indicates the data transfer status on the common bus.

UA-PROC (2) indicates the processing status of the unit UA.

Further, T, , T, . . . represent each bus cycle.

In the illustrated example, the common bus that was being used by unit UA in cycles T,,T, becomes vacant in cycle T2 (BUSBY=OFF in TI), and unit UB requests (UBB) to access unit UA. −
REQ=ON) and a request of unit UC for access to the same unit UA (UC-REQ=ON)
compete for the right to use the bus, and the higher-ranking UB wins. Next T
Data is transferred between UB and UA on the common bus in two cycles (CBUS=ON).

Data transfer ends in T2 cycle (CBUS=OFF)
, T3 cycle to T, cycle, processing is performed in unit tlA (UA-PROC=ON), and the resulting data is transferred in T, cycle (CBUS=ON).

T, the common bus is opened in the cycle (BUSBY=
OFF). In addition, at T2, the next access request to unit UA occurs in unit UC, and the bus usage right limit (is granted to unit UC and the data is transferred at T3, but since it is being processed within UA, it is held in the stack and the previous access request is After the processing is completed, it is read out by the stack and processed.

[Problem that the invention seeks to solve]

As is clear from the example of the time chart in FIG. 5, there are units, such as unit UA, that have an access information stack and that make access requests frequently.

If the access information stack cannot be used due to a failure, etc., the previous bus control method will not work.
There was a problem with the system going down.

[Means for solving problems]

The present invention is applicable when a unit having an access information stack does not use the access information stack.

By periodically changing the priority of the own unit,
Restrict access requests from other units to your own unit,
The right to use the bus is secured in advance for access requests from the own unit to other units.

Whenever a request for its own unit is received, it is processed immediately.

FIG. 1 is a diagram showing the basic structure of the present invention in an exemplary manner.

In the figure, 10 is a common bus, 11, 12, and 13 are units represented by UA, UB, and UC, respectively, and 14, 1
5.16 is a priority control circuit, 17°18.19 is an access information stack, 20 is a priority side WE5sPRIC, 21,
22, 23 [-request signal line UA-RQ for the retsure units UA, UB, and TJC to issue access requests;
UB-RQ.

It is UC-RQ. Although the access information stack is provided in each unit, it may be provided in only some units.

The priority control line PRIC is controlled by any unit 7) when the access information stack becomes unavailable in that unit.

Units UA, UB, UC connected to common bus 10
When accessing other units, the corresponding request signal lines UA-RQ, UB-RQ,
Turn on UC-RQ.

Priority control line PRIC and request signal line UA-RQ
, UB-RQ, UC-RQ are each unit UA, UB,
It is commonly connected to the priority control circuits 14, 15, and 16 in the UC, and is used for priority control of bus usage rights. Here, the highest priority is given to the signal on the priority control line PRIC.

[Effect]

The operation will be explained using an example in which the unit UA cannot use the access information stack 17. At this time, the unit UA alternately turns on and off the priority control line PRTC at a constant cycle via the priority control circuit 14.

The priority control circuit 14 of U
During the period when PRIC is turned on, when the unit (unit) UA learns of an access request from another unit to the UA using the access information (address) on the common bus, the ON state of PRIC is maintained as it is, and it is turned off at the end of processing. That is, the unit UA acquires the right to use the bus and executes processing with the access source unit. Also, priority control′
When fIAPRIC is ON, the priority is the highest, and other units UB and UC cannot acquire the right to use the bus.

On the other hand, during the period when PRIC is OFF, the priority control circuit in each unit uses the remaining signals UA-R except for PRIC.
Priority control is performed between Q, UB-RQ, and UC-RQ, and the highest-ranking unit acquires the right to use the bus.

That is, according to the present invention, the unit with the stack is
When the stack is not in use, access requests can be received preferentially only periodically for a certain period of time, and if there is an access request for the own unit during that period, the right to use the bus is secured and the request is processed.

In addition, during the remaining period excluding a certain period in which units that do not use the stack receive access requests preferentially, access requests to other units are processed in the normal priority order.

〔Example〕

FIG. 2 is a block diagram of a system according to an embodiment of the present invention.

In the figure, 10 is a common bus, 11, 12, 13 are units UA, UB, UC, 14 is a priority control circuit, and 17 is an access information stack.

21, 22, and 23 are request signal lines UA-RQ, UB-RQ, and UC-RQ for requesting bus use when UA, UB, and UC access other units, and 24 indicates request signal lines when the bus is in use. Bus busy signal line BUS representing
BY, 25 is an input/output control circuit. Unit U for convenience
Although the priority control circuit 14, access information stack 17, and input/output control circuit 25 are shown only in A, it is assumed that the other units UB and UC have similar configurations.

Unison) UA, UB, UC are each common bus 10
When it becomes necessary to transmit data between other units using the corresponding request signal line (UA-RQ,
UB-RQ, UC-RQ). A certain priority order is set in advance for each request signal line.

The bus busy signal line BUSBY is turned on while the common bus 10 is being used by any unit.

In a normal state in which the access information stack 17 is operable, the priority control circuit 14 performs a normal priority control operation and the bus busy signal line BUSBY is turned off.

That is, the common bus 10 is empty, and bus use is requested by multiple units including the own unit,
If corresponding request signal lines are turned on at the same time, priority control is performed between those request signal lines,
If its own unit has the highest priority, it acquires the right to use the bus and turns on BUSBY.

Next, the operation when a failure occurs in the access information stack 17 of the unit UA and its use is stopped will be described.

At this time, the input/output control circuit 25 is instructed not to use the stack. The input/output control circuit 25 uses the bus busy signal line BU
When SBY is OFF, it is controlled ON/OFF at a predetermined period of the bus cycle.

In this operating state, the bus busy signal line BUSBY is given the same function as the priority control line PRIC in FIG.

While this BUSBY is ON, the unit UA looks at the information on the common bus and determines whether the access is for itself.

As a result, the priority control circuit 14 controls the input/output control circuit 25 when the unit that turns on the request signal makes an access request to the unit UA and the unit UA receives the request while the BUSBY is ON.
= ON until the request processing is completed.

On the other hand, during the period when BUSBY is OFF, the right to use the bus is contested under two normal priority controls.

The units that have acquired the right to use the bus are UA and UB.

Regardless of the UC, BUSBY is kept ON when the bus is used continuously.

FIG. 3 is a time chart showing an example of the operation of the common bus when the access information stack is stopped in the embodiment system of FIG.

In the bus cycles T+, T3, Ts, . and the remaining To and Tt.

T, , -+7) period is a period in which BUSBY=OFF and priority control of access requests from other units is performed.

In the illustrated example, at ■, a UB access request to UA occurs at To, the priority order is controlled by normal control, and ■ is T,
The access information for the UA is transferred to the bus in step (3). DA detects this information and selects B[
JSBY and T2 are also held ON, and the bus is occupied by the UA. At this time, a UC access request to UB occurs at ■, but BUSBY is O at Tt and Ts.
N+7), the right to use the bus was not obtained, and UA received U
The right to use the bus is obtained at T4 after the access processing from B is completed, and the access information is transferred at T. T again.

In T, an access request to the UA is also generated at UB, but in this T, the access request to the UA is not accepted by the UA because BUSBY=ON.

[Effects of the Invention] According to the present invention, even when a unit having an access information stack cannot use the stack, appropriate common bus sharing control can be performed between each unit in the system.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a configuration diagram of an embodiment system of the present invention, and FIG. 3 is a time chart showing an example of common bus operation of the embodiment system shown in FIG. 2. FIG. 4 is a block diagram of the conventional system, and FIG. 5 is a time chart showing an example of the operation of the conventional system shown in FIG. 4 when the unit stack is not used. In FIG. 10: Common lot 11 = 137 Units UA, UB, UCl4: Priority control circuit 17: Access information star/7ri 20: Priority control line PRIC 21 to 23: Request signals vAUA-RQ, UB-R
Q, UC-RQ

Claims (1)

[Claims] A common bus (10) is shared by a plurality of units including a unit (11) having an access information stack (17) that temporarily holds access information for its own unit when immediate processing is not possible. In a computer system configured to grant bus usage rights to the unit with the highest priority among the units requesting use, a priority control line (20) having the highest priority is provided, and an access information stack (17) is provided. When the unit (11) having the access information stack is unable to use its own access information stack due to a failure, debugging, etc., or when it wants to operate without using it, the priority control line (20) with the highest priority is
is turned ON/OFF at a predetermined period, and the above priority control line (2
If no access request is received for the own unit (11) during the period when 0) is ON, the priority control line (20) is turned OFF, and when it is received, the priority control line (20) is turned OFF.
The N state is maintained as it is, the right to use the bus is obtained preferentially, and when the access processing is finished, the priority control line (2
0) to OFF, and on the other hand, while the priority control line (20) is OFF, normal priority control is performed on other units, and some functions of units that use the common bus are disabled as described above. A bus control method that allows the system to operate normally without the use of.