JPS6143369A - Multi-processor system - Google Patents

Abstract

PURPOSE:To improve the processing efficiency by providing a DMA (direct memory access) controller to a primary processor and connecting both element processors at data transmission and reception sides to the primary processor. CONSTITUTION:Plural element processors 13,20...2n are connected to a primary processor 1. A register 17 for bus transfer request is provided to each of processors 13,20...2n. At the same time, a DMA controller 4 is provided to the processor 1 to perform the transfer of data among local memories 15 of processors 13, 20...2n. Then the element processors at both data transmission and reception sides are connected to the processor 1.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a multiprocessor system that efficiently processes data using a plurality of processor configurations.

(Prior Art) In a conventional multiprocessor system, data is stored from the local memory of one processor to another.

In multiprocessing where the main task is to transfer data to local memory, the sending side either takes exclusive use of the bus or issues a request to the master processor to use the bus. However, with this method, if the bus is busy or multiple bus use requests are issued at the same time, it is necessary to clear the path exclusive tank again. Even if the transfer processor does not transfer data,
If the processing can be continued, the above-mentioned waiting for the dedicated bus tank would not be necessary, and the processing time of the processor would be wasted.

(Problems to be Solved by the Invention) This invention eliminates the need for the sending side to take path exclusive rights in the prior art, eliminates wasteful waiting time for acquiring bus exclusive rights, and achieves high processing efficiency. It provides a multiprocessor system.

(Means for Solving the Problem) The present invention provides a register for path transfer requests in each element processor in a multiprocessor configuration consisting of a main processor and a plurality of element processors, and also provides a register between the local memory 9 of each element processor. By providing the main processor with a DMA controller that performs data transfer functions, and linking the data sending element processor and the receiving element processor to the main processor, data transfer between element processors (divided job transfer) is possible. This improves processing efficiency as much as possible.

(Function) In a configuration provided with the above means, when the load on a certain element processor increases, data and DMA commands to be sent to other element processors are set, and a transmission request register is set. D
The above problem is solved by allowing the MA controller to transfer data from the transmitting element processor to the receiving element processor.

(Embodiment) The drawing is a circuit diagram showing an embodiment of a multiprocessor system according to the present invention, in which 1 is a main processor that controls the whole, 2 is a main processor, 1 is a CPU, and 3 is a local CPU of the main processor 1. Memory, 4 is a DMA controller that controls data transfer between each element processor, 5 is a register that stores the number of transferred bytes, 6 is a register that stores the sending processor number and its local memory address, 7 is the receiving processor number 8 is a control unit that controls DMA transfer, 9 is a register that stores CPU 2 and DMA
A multiplexer for the controller 4 to select and access an external processor, 1o a system address bus, 11 a system data bus, 12 a system control path, 13, 20 . , 2n are element processors constituting the multiprocessor system, 14 is an element processor 13 (DCPU), 15 is a local memory for storing programs and various data, and 16 is a CPU 14
and a multiplexer for the main processor 1 to selectively access the local memory 15, 17 a register for storing a transmission request, 18 a write control unit for the register 17,
19 is a control unit for the CPU 2 to read the register 17; Further, the configurations of the other element processors 20 to 2n are also the same as that of the element processor.

Main processor 1 manages the status of each element processor 13.20-2n. When starting execution from the initial state, the main processor 1 sets an initialization signal on the control path 12, and each element processor sets its own register 17 and enters an idle state. The main processor 1 sets the execution start address to a fixed address in the local memory 15 of any one of the element processors (in the present invention, the element processor 13), and performs If l) for that processor. The element process.

Since the register 17 of step 13 has already been set, that processor becomes busy first. Also, depending on the timing, the register 17 may not yet be set when polling is performed, but in this case, by repeating the number polling, the register 17 becomes busy after that.

The element processor 13 is not in a busy state from the initial state,
It is assumed that the other element processors 20 to 2n are in an idle state and the element processor 13 starts operating. The status of each of these element processors 1'3, 20 to 2n is managed by queues in the local memory 3 of the main processor 1. If there is an element processor in an idle state, the main processor 1 divides the job from the busy processor and transfers it to the idle processor, and divides the job to be transferred to the busy processor (element processor 13). Poll to see if it exists.

The busy processor 13 is in a state where it is either possible or impossible to accept boring requests from the main processor 1.
If the busy processor 13 is in a state where it can accept transfer, the register 12 is turned on. Therefore, when the busy processor 13 is polled, the control unit 19 opens the gate 51 and interrupts the CPU 14 at the same time as the state of the register 17 is read into the main processor 1 via the data bus 11. (In the figure, INT indicates an interrupt signal input section.) The processor 13 enters interrupt processing and sets the contents to be transferred to the main processor 1 at a fixed address in the local memory 15.

In this case, the content to set is "Job division undetermined"
Either "Job can be divided" or "Job can be finished".
Set the corresponding state as the status. Therefore,
When the main processor 1 polls the transmission request register 17 of the busy processor and the register 17 is set, it looks at the fixed address in the local memory 15, and the status contents of the fixed address are "Job division undetermined" and "Job division "Available" or "Job division completed."

Next, each case will be explained.

The "job division undetermined" state is a state where data to be transferred has not yet been set in the local memory 15 and no DMA command has been set.

Therefore, in this case, the main processor 1 repeats polling at regular intervals and repeatedly reads the status contents of the fixed address.

Next, the "job splittable" state means that a busy processor (element processor 13 in this explanation) splits the job and transfers the job to another element processor due to an increase in the load while executing its own job. Indicates that it is ready for transfer.

If the job is in a splittable state, a DMA command is set at the address following the fixed address where the status is stored. CPU 1 reads the DMA command and executes the DMA command.
The command read end code is set in the controller 4 and at the address following the fixed address. D
Register 5 of the MA controller 4 stores the number of transferred bytes, and register 6 stores the processor number of the sending side (in this case, the processor number of the element processor 13, which is the busy processor) and its local memory 15 address. The receiving processor number is stored in the reso staff. In this case, since the state of each element processor is managed in the local memory 3, the CPU 2 determines which processor is to be the receiving processor. (In this description, it is referred to as the element processor 20.)
When the DMA controller receives a transfer request command, the DMA controller
Start A transfer operation. When the transfer of the specified number of bytes of data from the element processor on the transmitting side to the element processor on the receiving side is completed, the DMA controller 4 interrupts the CPU 2. CPU 2 is the element processor 2 on the receiving side
0 from an idle state to a busy state, a job transfer completion code is set at a fixed address in the local memory 15 of the element processor 20 on the receiving side, and a DMA command, which is transfer data information, is set at the following address. The register 17 of the element processor 20 to which the data was transferred and the job was given is in the ON state! 11 (which is ON at the time of initialization), an interrupt occurs when the main processor 1 performs monthly polling, so the CPU 14 of the element processor 20 checks the fixed address of its own local memory 15 to determine whether the job is being executed. Know that you have been transferred. C of main processor l
The PU 2 writes a transfer completion code to a fixed address in the element processor 13, reads the fixed address at the next polling interrupt, and, knowing that the divided transfer of the job has been completed, turns off the transfer request register 17 and transfers its own job. Continue. (If the completion of job division transfer is unrelated to the continuation of its own job, it executes its own job without waiting for the completion of job division transfer.) Also, when the element processor 13 requests job division, other elements If all the processors are busy and there are no idle element processors, the CPU 2 writes a code indicating that the job cannot be accepted at a fixed address in the local memory 15 of the busy processor that has issued the job division request. When the busy processor reads the fixed address and finds that it cannot accept the call, it rewrites the address to an unspecified code and continues the job. The busy processor itself decides whether to leave the register 17 ON or turn it OFF.

Next, the "job finished" state is set when the busy processor 13 finishes the job, but prior to that, completion information is set in the address following the fixed address in the local memory 15. The main processor 1 connects the busy processor 13 to the idle queue of the management table in the local memory 3 and puts it in an idle state. Thereafter, the g-processor 13 keeps its register ON and enters an idle state waiting for a job from another element processor.

(Effects of the Invention) As explained above, the present invention provides a transmission request register in each element processor, and the main processor polls each element processor to sense the state of the transmission request register.
Depending on this state, the main processor divides the job and transfers it from the element processor requesting split transfer of the job to the idle processor among all the element processors it manages, so the element processor transfers the data. There is no need to request exclusive access to the bus when executing a job, and the user can concentrate on executing the job. In other words, in each element processor, when the processor load reaches a certain level or more, it is only necessary to set the transmission request register and set the data and DMA command to be transferred.
If processing can continue even if the element processor on the transfer side does not transfer data, there is no need to wait;

This has the advantage that processing time is not wasted.

[Brief explanation of the drawing]

The drawing is a circuit diagram showing an embodiment of a multiprocessor system according to an embodiment of the present invention. 1... Main processor, 2.14... CPU, 3,1
5...Local memory, 4...DMA controller, 5゜6.7.17...Register, 8,Z,! ?
, 19...control unit, 9, 16...-q rutisolexa, 13, 20-2n...9g7'rosetsusa, 10
...Address bus (ABUS), 11...Data bus (DBUS), 12...Control path (CBUS)
). Patent applicant: Oki Electric Industry Co., Ltd. Procedural amendment (voluntary) 60.3.22 Showa year, month, day

Claims (1)

[Claims] In a multiprocessor system comprising a plurality of element processors each having a CPU and a local memory, and one main processor that manages all of the element processors, a DMA controller that controls data transfer between the local memories of each of the element processors; The main processor is provided with a multiplexer for connecting to each element processor, and also has a register for requesting transmission to the main processor, and an interrupt to its own CPU if the contents of the register are in the ON state at the time of polling from the main processor. Each of the plurality of element processors is provided with means for connecting its own local memory to its own CPU or the main processor and other element processors, A multiprocessor system characterized in that data is transferred between each element processor and between each element processor.