JPS5812615B2 - Microprocessor controlled workstation adapter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a workstation adapter controlled by a microprocessor, in particular, by distributing the functions of processing control on the data processing device side and processing control on the workstation side, and controlling the processing with separate microprocessors. The present invention relates to a microprocessor-controlled workstation adapter designed to increase efficiency and flexibility.

A workstation is a device that includes, for example, a display device, a keyboard, or a printer.

The user can be thought of as using the workstation to process information while having a conversation with the host data processing device.

The workstation adapter is a device that controls the workstation, and is a device that can connect and control a plurality of display devices, such as eight display devices, under its control.

Conventionally, the above-mentioned workstation adapters were provided with data, registers, various control registers, etc., and were all configured by hardware logic.

Therefore, the amount of hardware increases.

Furthermore, even when a configuration in which processing is performed by a microprocessor is adopted, all control is performed by a single processor, which not only makes the control method considerably more complicated, but also The load on the system has increased significantly, it has been difficult to expand or improve its functions, and it has been difficult to speed up processing through multiprocessing.

The present invention solves the above-mentioned drawbacks and provides a workstation adapter that has high processing efficiency and high flexibility and reliability by using two microprocessors to organize data transfer between a workstation and a data processing device. is intended to provide.

Therefore, the microprocessor-controlled workstation adapter of the present invention is a workstation adapter that performs interface control regarding data transfer between a workstation and a data processing device, accepts a data transfer request from the data processing device, and processes the data. A first microprocessor that controls and processes data transfer completion reports to the processing device and data transfer request reports from the workstation side. The first microprocessor constantly monitors the workstation by polling, controls the startup of data transfer to the workstation based on an interrupt from the first microprocessor, and also controls the start-up of the workstation from the workstation side or data transfer 4. A second microprocessor that processes a report to that effect to the first microprocessor by a termination interrupt, and exchanges information regarding data transfer that is commonly accessed by the first microprocessor and the second microprocessor. a second control storage having a buffer for data to be transferred from the workstation to the data processing device or from the data processing device to the workstation; The present invention is characterized in that it includes a control ROM that is interposed between the first microprocessor and the data processing device and controls signals.

This will be explained below with reference to the drawings.

The figure shows the configuration of an embodiment of the present invention.

In the figure, 1 is a first microprocessor, 2 is a second microprocessor, and 3 is a control ROM. 4 is a register, 5 is a first control storage, 6 is a second control storage, 7 is a channel interface section, 8 is an I/O
controller, 9 device driver/receiver, 10
11 represents a display device, 11 represents a control flag, and 12 represents a data buffer.

From the data processing device (not shown) to the display device 10
A write data transfer request for one of the WR
When the ITE command is issued, the command is transmitted to the control ROM 3 via the channel interface unit 7.

The control ROM 3 may be considered as a collection of various gates.

The control ROM 3 interrupts the first microprocessor 1 and notifies it of the WRITE data transfer request.

The control program for the first microprocessor 1 is
It may be stored in the control storage 5 of.

When the first microprocessor 1 receives an interrupt from the control ROM 3, it similarly interrupts the second microprocessor 2 and sends the response from the second microprocessor 2 to the first control storage 5 in an idle routine. Wait while monitoring the control flag 11 provided inside.

This control flag 11 includes, for example, a ready flag and an attention flag.

The control program for the second microprocessor 2
can be stored in the control storage 6 of.

The second microprocessor 2 always uses the plurality of display devices 1 connected thereunder unless there is a special processing request.
Attention, etc. are monitored by sequentially polling 0, etc., but when there is an interrupt from the first microprocessor 1 as described above, the control flag 11 is prepared when the currently ongoing processing is finished. The completion flag is turned on and the request from the first microprocessor 1 is responded to.

When the first microprocessor 1 detects a response from the second microprocessor 2, it notifies the control ROM 3 via the register 4.

The control ROM 3 processes the WRITE data to be directly transferred to the data buffer 12 in the second control storage 6 via the channel interface section 7 under gate control.

The data transfer is performed using direct memory access (DMA).
), during this time the second microprocessor 2 can perform other processing, such as polling the display device 10.

Transfer byte count is the first control storage 5
is maintained.

When the transfer to the data buffer 12 is completed, the control ROM
3 to the first microprocessor 1, and from the first microprocessor 1 to the second microprocessor 2.

The second microprocessor 2 instructs the I/O controller 8 to transfer WRITE data from the data buffer 12 in the second control storage 6 to the display device 10.

When the data transfer to the display device 10 is completed, the I/O controller 8 transfers the data to the second microprocessor 2.
An interrupt is generated to report the completion of data transfer.

The second microprocessor 2 notifies the first microprocessor 1 of the completion of data transfer by turning on the control flag 11 of the first control storage 5.

Note that if any error occurs during data transfer, the abnormality display bit of the control flag 11 is similarly turned on to notify that fact.

The first microprocessor 1 starts the control ROM 3,
A data transfer completion report is sent to the data transfer request source of the data processing device via the channel interface unit 7, and the execution processing of the WRITE command is completed.

The processing for executing the READ command is also almost the same as the processing for executing the WRITE command.

When the data processing device issues a READ command, the control ROM 3 detects it and the first microprocessor 1
Interrupts.

Similarly, the first microprocessor 1 issues an interrupt to the second microprocessor 2 indicating that there is a READ request.

The second microprocessor 2 sends the data buffer 12 in the second control storage 6 from the display device 10 to the receiver 9 to the /0 controller 8.
Instructs to transfer READ data to.

The I/O controller 8 interrupts the second microprocessor 2 when the data transfer is completed and also reports the completion status, so the second microprocessor 2
is the control flag 11 in the first control storage 5
The data ready notification bit is turned on, and the end status is stored in the first control storage 5.

The first microprocessor 1 detects that the data ready bit is turned on under an idle routine and starts the control ROM 3.

The control ROM 3 sends READ data from the data buffer 12 to the request source through the channel interface section 7 under gate control.

Note that a transfer byte counter is provided in the first control storage, and the byte counter is updated by the first microprocessor every time one byte is transferred.

Once all READ data has been transferred, the corresponding REA
D Command execution processing ends.

As explained above, according to the present invention, the second microprocessor 2 accepts a processing request from the first microprocessor or I/O controller by interrupt, and also sends an operation to the first microprocessor or I/O controller. Since the instruction is given by push-out control, multiple processing becomes possible and processing speed can be increased.

In addition, various conventional control registers can be absorbed into the first control storage, and data transfer control can also be performed by microprogramming, improving flexibility and reducing the amount of hardware. Can be done.

[Brief explanation of drawings]

The figure shows the configuration of an embodiment of the present invention. In the figure, 1 is the first microprocessor, 2 is the second microprocessor, 3 is the control ROM 14 is a register, 5 is the first control storage, 6 is the second control storage, and 7 is the channel interface unit. , 8 is I/
O controller, 9 is device driver/receiver, 1
0 represents a display device, 11 represents a control flag, and 12 represents a data buffer.

Claims (1)

[Claims] 1. A workstation adapter that performs interface control regarding data transfer between a workstation and a data processing device, accepts a data transfer request from the data processing device, and sends a data transfer completion report to the data processing device and the workstation adapter. a first microprocessor that controls and processes data transfer request reports from the station side; and a first microprocessor that constantly monitors the workstation by polling and starts data transfer to the workstation by an interrupt from the first microprocessor. a second microprocessor that performs control and processes a report to the first microprocessor in response to an interrupt from the workstation indicating completion of startup or completion of data transfer; a first control storage commonly accessed by the second microprocessor and used for sending and receiving information related to data transfer; a second control storage containing a buffer of data to be processed; and a control ROM interposed between the first microprocessor and the data processing device to control signals. microprocessor-controlled workstation adapter.