JPS57106973A - Work station adapter under microprocessor control - Google Patents

Work station adapter under microprocessor control

Info

Publication number
JPS57106973A
JPS57106973A JP18333680A JP18333680A JPS57106973A JP S57106973 A JPS57106973 A JP S57106973A JP 18333680 A JP18333680 A JP 18333680A JP 18333680 A JP18333680 A JP 18333680A JP S57106973 A JPS57106973 A JP S57106973A
Authority
JP
Japan
Prior art keywords
work station
microprocessor
microprocessor control
under microprocessor
adapter under
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18333680A
Other languages
Japanese (ja)
Other versions
JPS5812615B2 (en
Inventor
Masami Wakabayashi
Toyokazu Nagahara
Hiroyuki Tsujita
Kazuhiko Momoi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18333680A priority Critical patent/JPS5812615B2/en
Publication of JPS57106973A publication Critical patent/JPS57106973A/en
Publication of JPS5812615B2 publication Critical patent/JPS5812615B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To improve processing efficiency by making traffic arrangements of data trnsfer between a work station and a data processor by using two microprocessors. CONSTITUTION:Processing control over a data processor side and that over a work station side are decentralized, and exercised by using individual microprocessors 1 and 2. The 2nd microprocessor 2 accepts a processing request from the 1st microprocessor 1 or an I/O controller 8 by interruption, and indicates the operation of the 1st microprocessor 1 or I/O controller 8 under thrust control. Consequently, multiprocessing is possible and speeded up.
JP18333680A 1980-12-24 1980-12-24 Microprocessor controlled workstation adapter Expired JPS5812615B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18333680A JPS5812615B2 (en) 1980-12-24 1980-12-24 Microprocessor controlled workstation adapter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18333680A JPS5812615B2 (en) 1980-12-24 1980-12-24 Microprocessor controlled workstation adapter

Publications (2)

Publication Number Publication Date
JPS57106973A true JPS57106973A (en) 1982-07-03
JPS5812615B2 JPS5812615B2 (en) 1983-03-09

Family

ID=16133933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18333680A Expired JPS5812615B2 (en) 1980-12-24 1980-12-24 Microprocessor controlled workstation adapter

Country Status (1)

Country Link
JP (1) JPS5812615B2 (en)

Also Published As

Publication number Publication date
JPS5812615B2 (en) 1983-03-09

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