JPS62254257A - Interruption control system for data transfer device - Google Patents

Abstract

PURPOSE:To allow an interruption given by an other processor in a non-time- constrained part by dividing the processor handling into a time-constrained part and a non-time-constrained part in response to the constraint of the processing time. CONSTITUTION:A time-constrained part must finish the processing within fixed period of time on the protocol between a host processor 20 and a data transfer device 10. While a non-time-constrained part performs the processing that has no time limit. When an interruption is received from the processor 20, a processor 11 starts processing by means of an address received from a processing address register 141 and at the same time stores the address which is reset to a register 142 or 143 when the job is through. If an interruption is received from another processor while the non-time-constrained part is working, the processing of said non-time-constrained part is interrupted and the processing of the time-constrained part is carried out. When this processing is over, the interrupted processing of the non-time-constrained part is restarted.

Description

[Detailed Description of the Invention] [Summary] In a data transfer device connected to a plurality of host processors, this data transfer device performs processing of a process requested by the host processors based on the processing time constraint. In this time-unrestricted part, interrupts from other processors are allowed to reduce the waiting time of the host processor.

[Industrial application field]

Exchanging and processing mutual processes between two or more processor systems is often done from the standpoint of effective resource utilization. At this time, there are various methods for transmitting and receiving data between processors, but the present invention is independent and
The present invention relates to a data transfer device that is connected between respective channel devices of a plurality of host processors that operate asynchronously and is activated by a processing request interrupt from the host processor to transfer data between these processors.

[Conventional technology]

Since such a data transfer device has affinity for two or more host processors at the same time, operations between a plurality of originally independent and asynchronous processor systems may interfere with each other.

For example, when connected to two information processing devices, if an abnormal state is detected in the other processor while executing a processing request from one processor, the system that detected the abnormality will normally first contact the white system. This prompts all connected devices to stop processing and initialize, but this also initializes the data transfer device, causing the processing requested by one of the processors to be interrupted.
There may be cases where it becomes invalid.

FIG. 2 shows a data transfer device 100 and two host processors 110 and 120 to which the interrupt control method of the present invention is applied.
The data transfer device 100 is connected to workstation channels 111 and 121 of the host processors 110 and 120, and is also connected to other workstations such as an image reader 130, a control console 131, a printer 132, etc. may be connected. This data transfer device 100 will appear as a workstation to both host processors.

Controlling a workstation from a workstation channel typically occurs as follows.

A host processor provides commands and, if necessary, data to a workstation, such as a data transfer device, through a workstation channel, and the workstations transmit information indicating their status or requested data according to a protocol. back to the host processor via the workstation channel, but if
If this protocol is not followed, the host processor recognizes that some kind of abnormality has occurred.

FIG. 3 shows the sequence from the start of the write command to the end of the sequence in chronological order, and the operations will be explained in association with the symbols given in this figure: (1) A write command is issued from the workstation channel.

■ This command generates an interrupt to the workstation.

■ The workstation recognizes the write command activation and sends back an acknowledgment of the command.

■ The host processor polls until the workstation indicates that it is ready to accept data.

■ When the workstation is ready to accept data, it issues a ready signal for boring from the host processor.

■ When the host processor recognizes this ready signal, it sends a ready recognition signal to the workstation, which generates an interrupt to the workstation.

■ The workstation returns an acknowledgment of the ready recognition signal.

■ Data is transferred from the host processor through a workstation channel.

■ In response to an interrupt caused by data transfer from the host processor, the workstation acknowledges the data and notifies the transfer completion status to the workstation channel.

[Phase] When the workstation channel recognizes that the data transfer has ended, it sends out a completion confirmation signal.

■ The completion confirmation signal generates an interrupt to the workstation.

@ The workstation returns an acknowledgment of the completion confirmation signal.

As described above, in this example, a total of four interrupts (■, ■, ■, and 0) occur from the workstation channel to the workstation.

Conventionally, in an information processing device connected to multiple host processors, until the execution of a process requested by one host processor, that is, the series of processes shown in FIG. A processing request from the processor could not be accepted.

[Problem that the invention seeks to solve]

An object of the present invention is that in a conventional information processing apparatus such as the data transfer apparatus described above, until the processing requested by one host processor is completed, another host processor does not perform any work on this information processing apparatus. However, it is possible to eliminate wasteful interrupt control and prevent inconsistencies between multiple host processor systems that operate asynchronously. The purpose of this invention is to provide a new interrupt control method that can be used.

[Means for solving problems]

FIG. 1 is a block diagram showing the basic configuration of the present invention, in which a data transfer device 10 is connected to workstation channels 21 of host processors 20z and 202, respectively.
Serial interface 121 connected to i, 21z
．． 122, these serial interfaces 12
From there, other workstations 221, 222, etc. may be further connected in a cascading manner.

The bus 13 from the microprocessor 11 of the data transfer device 10 has the serial interface 121.
122 is connected, and the interrupt vector register 14
, a stack pointer 15, a process stack 16 and a flag register 17 are connected, but it will be obvious that these may be constructed by dividing the random access memory area within the microprocessor 11.

This interrupt vector register 14 is a register that stores the start address of a program that performs processing when an interrupt occurs, and the processing address register 141 in this interrupt vector register is generated by activation from a workstation channel. This is a register for giving a vector address at the time of an interrupt, and is a return address register A14.
2 and return address register B 141 are for storing return addresses to which the host processors 201 and 202 return when processing requests from the host processors 201 and 202, respectively, are completed.

The process stack 16 is a register that saves information resources such as data and programs necessary for process processing, and there are two sets of stacks 161 and 162 for process A from the host processor 201 and process B from the host processor 202. The interrupt flag register 17 is provided with the host processor 201 or 202.
This is an interrupt flag register that stores a flag indicating which interrupt is coming from.

Furthermore, as an embodiment of the present invention, a suspension flag is stored that indicates that execution of a process requested from one host processor is temporarily permitted while a process requested from one host processor is being executed. A register 18 was provided.

Note that when performing direct memory access, direct memory access controllers 191 and 192 can be provided for each of the processors 20s and 20z, but since they are not directly related to the present invention, their explanation will be omitted.

[For production]

If we consider the interrupt from the workstation channel and the workstation processing for that interrupt as one processing unit, as shown in the sequence shown in Figure 3, the fourth
As shown in Figure a, it is represented by a combination of a time constraint part and a time non-constraint part, and the series of sequences shown in Figure 3 above are each started by interrupting a plurality of processing units as shown in Figure 4. This means that

The time constraint section indicated by diagonal lines in FIG. In response to an interrupt, the workstation must return the Akurufuji within a certain period of time, and if the Akurufuji is not returned, it will be recognized that an abnormality has occurred in the workstation, etc. The time-unconstrained section is a section that performs processing without such processing time constraints.

In the initial state, the process stack A 61 contains the start address for executing the process when the process A is dependent on the host processor 201, and the process stack B 162 contains the start address of the host processor 202.
When Processor B receives a processing request from Processor B, the start address for the processing is stored.

When there is an interrupt from any host processor 20,
The processor 11 starts processing with the processing start address from the processing address register 141, identifies the host processor that caused the interrupt, and stores this in either register 141 or 142 corresponding to that host processor in the return address register 14. In addition to storing the address to return to when the interrupt work is finished,
A flag is set on the side of the interrupting processor in the interrupt flag register 17, and the interrupting process is stored in the stack pointer 15, thereby popping up the process stack 16 and executing this process.

When the processing of the time constraint section is completed, the processor 11 returns to the operation of the control section that performs its own processing based on the address stored in the return address register 14, checks for the presence or absence of interrupts from other processors, or detects abnormalities. If there is no interrupt, the non-time-constrained part is processed again, but if there is an interrupt from another processor, the time-constrained part of that process is processed.

If there is an interrupt from another processor while processing a non-time-constrained part, that process will be interrupted and the time-constrained part of the interrupted process will be processed. The address is set in the processing address register 141 prior to starting the processing of the time-unconstrained portion.

If such an interrupt occurs, once the processing of the time-restricted part is completed, the processing of the previously interrupted time-restricted part will be resumed, but at this time, the start address of the time-restricted part of the interrupted process will be restarted. is stored on the corresponding process side of the process stack, so this process can be executed simply by switching the stack pointer to this process side.

As one embodiment of the present invention, as shown in FIG. 4C, a reset instruction, an initialization instruction, etc. in the time-unconstrained part of the sequence shown in FIG. A suspension point P is set in advance before an instruction that affects the processing of the processor 11, and when the processing progresses to this suspension point, the processor 11 checks whether or not there is a suspended process. By giving priority to the process if there is one, it is possible to prevent the process of the suspended process from being invalidated. Set the flag to be sent to the corresponding process.

〔Example〕

FIG. 5 shows the operation of the embodiment of the data transfer device 10 according to the present invention, in which the top stage is a control unit that is processed by the processor 11 itself, and the shaded part is the initial state, which will be described later. The boxed portion indicates the period during which interrupts or abnormalities from other host processors are detected. The middle row is an example of an operation mode in which the work of process A requested by the processor 201 is processed, and the lower row is an example of an operation mode in which the work of process B is processed as requested by the processor 202.

The operation shown in FIG. 5 will be explained with reference to the configuration shown in FIG. 1. The initial state indicated by I in FIG. , ■ is the period during which the processor 11 checks for interrupts from other host processors or system abnormalities, ■ is the time constraint part described above, and ■ is the same (
It is a time-free part, and the subscripts A and B of ■ and ■ are process A.
.

Indicates that the processing is for B.

Furthermore, FIG. 5a shows an example in which there is an interrupt from process B of the processor 202 during processing of the non-time constrained section of process A from the processor 20s. This figure shows an example where there is an interrupt from process B of the processor 202 during the processing of . It is.

(1) In the initial state alt shown in FIG. 5a, the start addresses of processes corresponding to processing requests from host processor 201 and host processor 202 are set to It is set in the start address storage area, and interrupts from the host processor 20 are monitored while the control section is processing.

(2) When there is an interrupt from the host processor 201, the processor 11 identifies which host processor the interrupt is from during the period (1) in FIG. Set the address to return to when processing of work due to this interrupt is completed in the interrupt vector register return address register A142, and set the stack pointer 15 to the A side to indicate that the interrupt is for process A from the host processor 201. Then, pop up the stack A161 for process A.

Process A is processed during the period ①A after the completion of the process, and this process is performed by the time constraint section.

(3) Even if there is an interrupt request for process B from another host processor 202 as shown in FIG.
Process A continues.

(4) Then, the time constraint unit 1 [[When the processing of A is finished, the return address register A142 of the interrupt vector register 14
By returning to the stored address, the process is temporarily interrupted and the process returns to control section 2, which stores the start address of the time-free section IVA following this time-constrained section mA in the stack 161 for process A. . This control part ■2
In this step, the presence or absence of an interrupt from another host processor or the presence or absence of an abnormality is checked.

(5) If there are no interruptions or abnormalities, the fifth
As shown in FIG.
2, and since this processing is a non-time-restricted process, interrupts from other host processors can be tolerated, so an interrupt from another host processor can be set in the processing address register 141 of the interrupt vector register 14. After setting the start address of the process to start when
Processing I of the non-time-constrained part for the host processor 201
Return to V A s.

This return is executed by popping up the start address of the time-independent portion IVA stored in the stack 161 on the process A side with the stack pointer 15 on the A side.

(6) If an interrupt from process B of the processor 202 occurs during the processing of this time-unconstrained part IVA, the process is interrupted, returns to control unit 3, and starts processing of time-constrained part II [B of process B. do.

(7) When the processing of this time constraint unit IB is finished, the process returns to control unit 4 and checks whether there is any suspended work, whether there is an interrupt from another processor, or whether there is an abnormality. Since the processing IVA of the section is interrupted, this processing NA1 is executed.

(8) When this process IVA1 is finished, the control unit
Returning to step 5, process the non-time constrained part IVB of process B in the same way as in (7) above, and when that is completed, the control part
Returning to step 6, if there is no interrupt from the processor 20, (
Initial situation as mentioned in 1)! Maintain Ix to prepare for the next interrupt.

The sequence when there is an interrupt from the process B of the processor 202 during the processing of the HA shown in FIG.
Since the states (1) to (4) above are the same, their explanation will be omitted, and the processing after (5) will be explained.

(5)' Assuming that there is an interrupt request from another host processor 202 during the processing of the above-mentioned time constraint section I[A or during the processing of the above-mentioned time non-constraint section IV A t, the 5th
As shown in the figure, the processing of the process A in progress is temporarily interrupted and the process moves to processing I[IB' of the time constraint section of the process B which has issued the interrupt. For this migration, the address stored in the processing address register 141 of the interrupt vector register 14 is used.

(6) When 'processing IB' of the time constraint part of this new interrupt is completed, the process returns to control part ■3' in the same procedure as in (3) above, and the temporarily suspended process A side Processing IVA' of the time-free part is restarted.

(7) 'Processing IVA of the time-unconstrained part of this process A'
When 1[[
Processing IVB of the non-time constrained part of process B from the host processor 202 which has finished the processing of the time constraint part in B'
' starts, and when this process is finished, returns to the control unit US,
If there is no new interrupt from both host processors, the process will complete one cycle (maintaining the initial state BI2 as explained in υ).

As mentioned above, when there are multiple host processors, if an instruction such as initialization is instructed by an interrupt from the other host processor while processing a task assigned to it by one host processor, one of the host processors The processor will be initialized during the process requested by the computer, and data and programs will be lost.

In order to eliminate such drawbacks, one embodiment of the present invention provides a suspension point that suspends a time-unconstrained part, such as a reset instruction or an initialization instruction, as shown in FIG. 4C. P is specified in advance, and at this pending point, a pending flag is set in the corresponding process side of the flag register 18, and interrupt requests from other host processors are handled as described in detail later with respect to FIG. 5C. Check whether there are any unprocessed parts remaining in the non-time-constrained part from other host processors, and if there are any interrupt requests or unprocessed parts, execute these processes first and do the above. Defects can be removed.

FIG. 5C shows a similar processing sequence to that shown in FIG.
This shows an example in which the above-mentioned suspension point is provided in the time-free part IVA' of process A, and the time-free part I in FIG.
When the processor 11 detects a suspension point set in advance in this time-unrestricted portion during the processing of the time-unrestricted portion IVAI” of C in the figure corresponding to VA′, the processing of the processor 11 returns to the control portion “4”. , checks whether there is any work that is interrupting the process, but in this example, the non-time-constrained part IV of process B
Processing B' remains, so perform that processing, and when it is finished, return to the control unit ■5'', and after confirming that there is no other work being interrupted, return to the non-time-constrained unit IVA1 of process A.
The process IVA2'' after the suspension point of ' is executed.

〔Effect of the invention〕

According to the present invention, processing is divided into a time-restricted part and a time-unrestricted part, and the time-unrestricted part allows interrupts from other host processors, thereby significantly shortening the waiting time of host processors. Switching control of complex processes can be easily controlled using few resources, and since there are few resources, the overhead for switching is small and there is almost no time loss.

Then, the hold function allows processes A and B to reset, which would cause inconvenience if they are not synchronized with the process on the other side.
Even when executing erase write commands, etc., these commands are executed after finishing the processing of the other party's process, so it is possible to achieve the special effect of preventing the loss of necessary data or erroneous processing. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of the present invention, and FIG.
FIG. 3 is a block diagram showing an example of a processor system to which the present invention is applied; FIG. 3 is a diagram showing a processing sequence in the processor system to which the invention is applied; FIG. 4 is a diagram explaining the processing sequence according to the invention. , FIG. 5 is a diagram showing an embodiment of a processing sequence according to the present invention. 10 is a data transfer device, 20 is a host processor, 11
is a processor, 12 is a serial interface, 141
142 and 143 are processing address registers, 142 and 143 are return address registers, 15 is a stack pointer, 16 is a process stack, 17 is an interrupt flag register, and 18 is a pending flag register.

Claims (2)

[Claims] (1) Two or more host processor systems (20_1
, 20_2) at the same time, undertakes data transfer between these two processor systems, and whose operation is activated by a processing request interrupt from the host processor system. A process stack (16) for saving information resources necessary for executing a process requested by the host processor system, and a process stack (16) for processing the process when the process is requested by an interrupt from the host processor system. A processing address register (14_1) that stores the start address of the process requested by the host processor, and a return address register (14_2, 14_3) that stores the start address for returning to the processing of the control unit when the process requested by the host processor is finished. and an interrupt flag register (15) that stores the host processor that has issued an interrupt, and when a process is requested to process another process due to an interrupt from another processor while executing a non-time-constrained part of the process. and a register (17) for storing the start address of the process to be performed, and the processor (11) continues the process even if there is an interrupt from another processor while processing the time-restricted part of the process. An interrupt control method characterized in that, during processing of a time-unrestricted portion of a process, the processing of a process interrupted by another processor is performed. (2) By setting a suspension point in advance in the time-unconstrained part of the process, and setting the flag register (18) in the process when the processing of the process progresses and reaches this suspension point, the processor (11) Checks whether there are any unprocessed parts remaining in the time-unconstrained parts of other processes, and if there are unprocessed parts of other processes, these processes are executed first. An interrupt control method according to claim 1, characterized in that: