JPS6111867A - Processing method of abnormality in interface control - Google Patents

Abstract

PURPOSE:To execute simply the processing of abnormality in a channel by storing identifying information at the detection of an error, and executing the channel processing as abnormal end in accordance with said discrimination information. CONSTITUTION:A CPU2 uses a certain channel area in a communication control register 21 through a system bus 3 to execute prescribed data transfer processing. When an error is generated on a system bus 3 or an interface between the system 3 and the communication control register 21, a write data parity check circuit 23 transmits its detecting signal to an FIFO 24. Receiving the detecting signal, the FIFO 24 inputs a channel selecting signal outputted from an address decoder 22 as the channel information to its inside and stores the information. A microprocessor 10 reads out the channel identifying information of the channel generating the error from the FIFO 24 and analyzes the information to execute processing for information the analyzed result to a corresponding command processing task.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an abnormality processing method in interface control by a communication control device or a human output control device, etc., and in particular to a method for handling an abnormality in interface control by a communication control device, an input/output control device, etc. has multiple data processing channels (hereinafter referred to as channels) and performs multiple data transfers, data transmission, etc. between communication systems or other computers according to instructions (hereinafter referred to as commands) from the central processing unit (hereinafter referred to as CPU). When performing via one of the channels, the frame for either channel
When an error occurs in the interface control, abnormality processing can be easily performed on the communication control device or input/output control device side, as well as on the CPU side that controls it, for the channel where the error occurred. Regarding the method.

[Conventional technology]

A communication control device or input/output control device that performs this type of interface control usually has a built-in microprocessor, and upon receiving commands from the CPU, the built-in microprocessor controls the interface section and controls the communication system or other devices. It is used to transmit data to and from a computer.

FIG. 4 shows a specific example of a communication control device, in which the communication control device 1 has a CPU 2
It receives predetermined commands and data from the computer via the system bus 3, and sends the predetermined data to a corresponding communication system or other computer.゛Here, the communication control device 1 has an internal microprocessor (μP) 10 and a microprocessor bus 1.
1. Communication register 12, CPU interrupt control unit 13, RO
The communication register 12 includes a command register, a status register, and the like. Here, the communication control register 12 plays the role of an interface between the system bus 3 and the microprocessor bus 11.

Then, the microprocessor IO receives the communication register 12.
The CPU 2 reads commands written in the CPU 2, and executes various controls on the communication system or the external interface 16 with other computers according to the contents. . The command processing status and command execution results are then sent to the communication register 12.
is set as status information, and further generates a CPU interrupt signal to the CPU 2 via the interrupt control unit 13 as necessary.

In a device having such a configuration, when the CPU 2 writes data related to a command such as a command and various accompanying command parameters to the communication register 12 via the system bus 3, the CPU 2 communicates with the system bus 3 or with the system bus 3. If a data error occurs at the interface with register 12, an incorrect command or command parameter will be set in communications register 12.

In this case, the microprocessor can detect the abnormality to some extent and refuse command processing, but there is a risk that it will not be able to detect this and execute incorrect control that is different from the original request of the CPUZ side. be.

Therefore, conventionally, a parity check circuit is provided at the interface between the system bus 3 and the communication register 12 to check whether or not there is an error in the data written from the system bus 3 to the communication register 12.

FIG. 5 shows such a system bus 3 and communication register 1.
17 is a block diagram centered on the relationship with 2.
18 is a write data parity check circuit;
This is a μP interrupt control unit for the microprocessor IO. Further, 17a is a write parity error signal line, 1
8a is an interrupt request signal line to the microprocessor IO.

By adopting such a configuration, when a write data parity error is detected by the write data parity check circuit 17 when the CPU 2 sets a command in the communication register 12, an interrupt is sent to the microprocessor 10. , you will be notified to that effect. Therefore, the microprocessor 10 receives this notification and performs processing to prevent execution of the abnormal command processing.

Furthermore, the sacroprocessor 10 can notify the CPU 2 via the CPU interrupt control unit 13 by hardware or software that an abnormality has occurred.
Upon receiving this notification, the UZ side can relatively easily handle this by aborting (truncating) the communication control routine and activating an abnormality handling routine, for example.

[Problem that the invention seeks to solve]

The CPU is used not only to process data through a single channel, but also to control various processes and process data exchange with various computers and communication systems in parallel. Therefore, when processing in such a case, multiple channels are required to handle the processing.

Moreover, since these plurality of channels need to function independently, simply creating a plurality of channels as shown in FIG. 5 will increase the amount of hardware accordingly. In addition, the CPU side also needs to manage multiple channels independently in response to this, and in such cases, simply notifying the CPU of an interrupt to notify an abnormality of write data, etc. In order to transition to the abnormality handling routine, extremely complicated processing must be performed.

As a result, the load on the CPU side for such abnormal processing increases, and furthermore, depending on the number of channels to be processed, it may become difficult to take effective measures.

Therefore, the microprocessor built into the control device also has the disadvantage that it is difficult to cancel the command processing execution on the channel in which the command data error has occurred and to perform effective abnormality processing.

[Purpose of the invention]

In addition to solving these problems or drawbacks of the conventional technology, when a communication control device or input/output control device has multiple channels, when an error occurs in a command, etc. for one of the channels, It is an object of the present invention to provide an abnormality processing method in interface control that allows a communication control device or an input/output control device to easily perform abnormality processing for a channel in which an error has occurred, or on the CPU side that controls the device.

[Means for solving problems]

Means in the interface control abnormality and processing method of the present invention that achieves such objects and solves the above-mentioned problems, etc., is a method for controlling a central processing unit and an interface control device such as a communication control device or an input/output control device. In the information processing system, the interface control device includes an arithmetic processing device and has a plurality of channels, and at least a command related to a command sent from the central processing unit by specifying any channel among the plurality of channels. Error detection is performed on the data, and when an error is detected,
Information specifying a channel or information corresponding thereto is held as identification information, and the arithmetic processing unit processes processing for that channel as abnormally terminated in accordance with this identification information.

[Effect]

When an error is detected in this way, the information specifying the channel or the information corresponding to this is stored and managed as identification information, so the interface control device handles the error corresponding to each channel. Notification processing to the CPU side can be easily performed, and the increase in hardware circuits is also almost negligible.

On the other hand, on the CPU side, since notification of abnormal termination corresponding to the channel can be received, the management becomes easy and there is no need to load the process.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram of an embodiment of an abnormality processing method in interface control to which the present invention is applied;
3 and 3 are flowcharts of data parity error interrupt processing and command processing task processing procedures when the CPU writes a command.

Note that the same parts as shown in FIGS. 4 and 5 are designated by the same reference numerals.

20 is a main block of the communication control device, which includes a CPU
In addition to the interrupt control circuit 13 and the microprocessor 10, a communication control register 21, an address decoder 22, a write data parity check circuit 23, and a memory circuit (FI
FO) 24, and a μP interrupt control section 25 which is an interrupt control section for the microprocessor.

Here, the communication control register 21 has multiple channels CH
Os, CTll5. ..., channels 0, 1, . . . as a dedicated register area corresponding to each CHns. , ・・・
・.

n and t.

Further, the address decoder 22 decodes the address given from the system bus 3 when the communication control register 21 is accessed by the CPU 2. On the other hand, FIFO
24 is a circuit having a first-in/first-out function, which takes in the output signal of the address decoder 22 as data corresponding to each bit position, supplies the information to the microprocessor bus 11, and interrupts the microprocessor 10. Outputs a signal to make a request.

Now, the CPU 2 uses a channel area of the communication control register 21 through the system bus 3, sets commands or command parameters, and performs a predetermined data transfer process. At this time, the address decoder 22 receives an address signal from the system bus 3, decodes it, and sends a channel selection signal (CHOs) to select the corresponding channel.
, CHIs +...

CHns) and supplies the signal to the FIFO 24 as data.

Here, assuming that a data error occurs on the system bus 3 or at the interface between the system bus 3 and the communication control register 21 during such processing, the write data parity check circuit 23
Upon receiving this command setting or command parameter data, a parity check error is detected here. Then, a detection signal is output to the write data parity error signal line 23a and sent to the FIFO 24.

When the FIFO 24 receives this detection signal, the channel selection signal (CHOs, C
HIs, . . . , CHns) as channel information and stores it. In addition, FIFO
24 can sequentially store channel identification information corresponding to each error even if multiple write data parity errors occur, and these stored channel identification information can be stored from the time when the selection signal is first taken in as channel identification information. An instruction signal indicating that valid data is being stored is sent to the instruction signal line 24a until all selection information is read out by the microprocessor 10.
The μP interrupt controller 25 issues an interrupt request to the microprocessor IO via the interrupt request signal line 25a.

Here, the instruction signal indicating that valid data is being stored from the FIFO 24 is set as a 1-bit flag in one interrupt cause register in the μP interrupt control section 25.

Now, when the microprocessor IO detects a command setting for a certain channel by the CPU 2, it accepts the interrupt caused by the above-mentioned write data parity, if any. The interrupt program is executed first, but if there is no such interrupt, the command processing task of the corresponding channel is activated.

Here, when the interrupt processing program is executed, the microprocessor 10 first reads out the channel identification information in which the error occurred from the FIFO 24, analyzes it, and performs processing to notify the corresponding command processing task. conduct. For example, when the control flow of the microprocessor 10 is determined by each command processing task and a predetermined program is executed, it is assumed that there is a dedicated file (herein referred to as a task control file) used to execute the processing. For example, this notification process is performed by setting information indicating that the write data parity error has occurred in this dedicated file.

Then, until all the flags (displayed as flags in the interrupt cause register) indicating that valid data is being stored included in the μP interrupt control unit 25 are reset, that is, such processing is continued until the write data parity error occurs. The process of notifying each command processing task as described above is executed until all the accumulated channel identification information corresponding to the number of occurrences is read out.

Specifically, this process is performed according to the process procedure shown in FIG.

That is, as shown in FIG. 2, in step (2), error occurrence channel identification information is read, and in step (2), it is determined whether or not an error has occurred in channel 0. As a result of this determination, if it is determined that an error has occurred, the process moves to step (2) a, where the command processing task of channel 0 is notified that an error has occurred, and the process moves to step N. On the other hand, as a result of this determination, if no error has occurred in channel 0, the process moves to the next step (2), and in step (2), it is determined whether or not an error has occurred in channel 1.

Similarly, if it is determined that an error has occurred as a result of this determination, the process moves to step a, notifies the command processing task of the channel that an error has occurred, and then proceeds to step N. and move on.

Further, as a result of this determination, if no error has occurred in channel 1, the process moves to the next step, and in the next step, it is determined whether or not an error has occurred in channel 2.

In this way, it is sequentially determined whether a write data parity error has occurred for each channel, and finally,
Similarly, in step M, it is determined whether or not an error has occurred in channel n. If the result of the determination is that an error has occurred, the process moves to step Ma; if no error has occurred, the process moves to step N. and move on.

Now, in step N, it is determined whether channel identification information is being stored in the FIFO 24 by referring to an instruction signal indicating that valid data is being stored. As a result, if this identification information is not stored in the FIFO 24, this process ends. On the other hand, if the result of this determination is that the data is still being stored, the process returns to step (2) and the same process is repeated.

Note that if an error occurs multiple times regarding the same channel, it may be unnecessary to set information to the task control file from the second time onwards.

Now, after the above-described interrupt processing program runs, the command processing task corresponding to the channel that received the command is activated. The started command processing task first refers to its own task control file before determining the flow of control of the microprocessor 10 and starting execution of command processing in accordance with this.

Then, the CPU 2 checks whether a write data parity error has occurred in the command set in the register area corresponding to the own channel of the communication control register 21 by referring to information indicating the occurrence of an error.

If the task control file contains information (flag) indicating that an error has occurred in the previous interrupt processing, the command processing task that recognizes it will perform abnormal processing without executing normal command processing. Move into routine.

The abnormality processing routine specifies that the command processing will be abnormally terminated due to the occurrence of the write data parity error.
It is displayed in the status register section of the register area corresponding to the own channel of the communication control register 21, and if necessary, the CPtJ2 is notified of this by an interrupt.

The command processing task then completes its processing according to the processing procedure shown in FIG.

In FIG. 3, in step ■b, it is determined whether or not there is a write data parity error occurrence notification at the time of command setting, and if there is no write data parity error notification, in step ■b, the corresponding command The microprocessor 10 is controlled by the processing task to execute a regular command processing task.

Then, the process moves to step ■b, sets the normal completion information in the status register, and in step ■b, the CPU'
2, it is determined whether or not a termination interrupt is necessary, and if it is not necessary, this process is terminated.

On the other hand, as a result of this determination, if an end interrupt to the CPU 2 is necessary, the process moves to step ■b, and step ■b'
? 'Perform processing to issue a command processing end interrupt to cPU2. Then, this process ends.

Now, when it is determined in step (b) that there is a notification that a write data parity error has occurred during command setting, in step (b), error information is set in the status register of the communication control register 21,
Similarly, in step 2b, abnormal termination information is set in the status data.

Then, the process moves to step b. Through these steps, the CPU 2 executes the command processing requested by itself by detecting the status of the communication control register 21 or receiving an interrupt from the channel. It is possible to detect that the process was not executed normally and ended abnormally due to the occurrence of a data parity error.

In the above embodiments, the case where processing is performed by checking for write data gritty errors such as commands or command parameters has been mainly explained, but in addition to such things, in addition to commands or command parameters,
It goes without saying that an error check may be performed on the transferred data, and the checking method is not limited to the write data parity check.

Further, although the explanation is centered on an example of a communication control device, the same applies to an input/output control device, and it goes without saying that the present invention can be applied to such devices as well.

〔Effect of the invention〕

As can be understood from the above description, the present invention provides an information processing system having a central processing unit and an interface control device such as a communication control device or an input/output control device, wherein the interface control device includes an arithmetic processing device, It has a plurality of channels, and the central processing unit specifies any channel among the plurality of channels and sends it out.

and when an error is detected, retain information specifying the channel or corresponding information as identification information,
The arithmetic processing unit processes the process for that channel as abnormally terminated according to this identification information5, so on the interface control device side, the abnormality process corresponding to each channel and the notification process to the CPU side can be easily performed. The increase in hardware circuits is also minimal.

On the other hand, on the CPU side, since notification of abnormal termination corresponding to the channel can be received, management becomes easy and there is no need to load the process.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of an abnormality processing method in interface and control to which the present invention is applied, FIG. 2 is a flowchart of data parity error interrupt processing when a command is written to the CPU, and FIG. A flowchart of the processing procedure of the command processing task when writing a command to the CPU,
FIG. 4 is a block diagram of an abnormality processing method when there is one processing channel in a conventional communication control device, and FIG. 5 is a concrete explanatory diagram focusing on the interface portion thereof. 1.20-m-・Communication control device, 2...CPU,
3...-system bus, 10-... microprocessor, 11... microprocessor bus, 12-,
21--communication control register, 13--CPU interrupt control unit, 22--address decoder, 23--...
Write data parity check circuit, 24--memory circuit (FIFO), 25--μP interrupt control unit.

Claims (2)

[Claims] (1) In an information processing system having a central processing unit and an interface control device such as a communication control device or an input/output control device, the interface control device includes an arithmetic processing device and has a plurality of data processing channels. Error detection is performed on at least command-related data sent from the central processing unit by specifying any data processing channel among the plurality of data processing channels, and when an error is detected, the data An interface control characterized in that information specifying a processing channel or information corresponding thereto is held as identification information, and the arithmetic processing unit processes processing for the data processing channel as abnormally terminated according to this identification information. Anomaly handling method. (2) Error detection is to detect a parity error in write data that is performed by specifying a certain data processing channel, and the interface control device detects a parity error in write data when a parity error is detected in the write data. Information specifying a data processing channel or information corresponding thereto is stored as identification information, and an arithmetic processing unit is caused to perform interrupt processing, and this arithmetic processing unit corresponds to the specified data processing channel according to the identification information. A patent claim characterized in that the presence or absence of an error is managed in response to a processing program that is executed, and the central processing unit is notified that processing for the data processing channel has ended abnormally depending on whether or not an error has occurred when starting execution of a command. The abnormality handling method in the interface control according to the scope of item 1.