JPH0319574B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an abnormality handling method in interface control by a communication control device or input/output control device, etc., and in particular, to a communication control device or an input/output control device. etc. have multiple data processing channels (hereinafter referred to as channels), and according to specifications (hereinafter referred to as commands) from the central processing unit (hereinafter referred to as CPU), data is transferred between communication systems or other computers. etc. is performed through one of multiple channels, and when an error occurs in a command, etc. for one of the channels, abnormal processing is performed on the communication control device or input/output control device in response to the channel where the error occurred. , to control this
This paper relates to an error handling method in interface control that can be easily performed on the CPU side.

[Conventional technology]

Communication control devices or input/output control devices that perform this type of interface control usually have a built-in microprocessor, and the built-in microprocessor controls the interface section in response to commands from the CPU. It transmits data or transfers data between communication systems or other computers.

FIG. 4 shows a specific example of a communication control device, in which the communication control device 1 receives predetermined commands and data from the CPU 2 via the system bus 3, and takes corresponding actions. Sends specified data to a communication system or other computer.

Here, the communication control device 1 has an internal microprocessor (μP) 10 and a microprocessor bus 1.
1, communication register 12, CPU interrupt control unit 13,
It is equipped with a ROM 14, a RAM 15, and an external interface 16, and the communication register 12 is
It has a command register, status register, etc. Here, the communication control register 12 plays the role of an interface between the system bus 3 and the microprocessor bus 11.

The microprocessor 10 reads commands written in the communication register 12 from the CPU 2, and executes various controls on the communication system or the external interface 16 with other computers according to the contents. Then, the processing status of the command and the result of command execution are set in the communication register 12 as status information, and further, if necessary, a CPU interrupt signal is generated to the CPU 2 via the interrupt control unit 13.

In a device having such a configuration, when the CPU 2 writes data related to a command such as a command and various accompanying command parameters to the communication register 12 via the system bus 3, the data on the system bus 3 or between the system bus 3 and the communication register 1
If a data error occurs at the interface with the communication register 12, an incorrect command or command parameter will be set in the communication register 12.

In this case, the microprocessor can, to some extent,
Although it is possible to detect the abnormality and refuse command processing, there is a risk that the CPU 2 side may not be able to detect this and execute incorrect control that is different from the original request of the CPU 2 side.

Therefore, in the past, a parity check circuit was provided at the interface between the system bus 3 and the communication register 12, and the system bus 3 was connected to the communication register 12.
The data written to is checked for errors.

FIG. 5 is a block diagram mainly showing the relationship between the system bus 3 and the communication register 12, in which 17 is a write data parity check circuit, and 18 is a μP circuit for the microprocessor 10. This is an interrupt control section. In addition, 17a is
A write parity error signal line 18a is an interrupt request signal line to the microprocessor 10.

By adopting such a configuration, CPU2
When the write data parity check circuit 17 detects a write data parity error when setting a command in the communication register 12, it interrupts the microprocessor 10 and notifies the microprocessor 10 of this fact. Therefore, the microprocessor 10 receives this notification and performs processing to prevent execution of the abnormal command processing.

Furthermore, the microprocessor 10 can notify the CPU 2 of the occurrence of an abnormality using hardware or software via the CPU interrupt control unit 13, so that the CPU 2 receives this notification and executes, for example, a communication control routine. To deal with this, processing such as aborting (truncating) and activating an abnormality handling routine can be performed relatively easily.

[Problem that the invention seeks to solve]

The CPU not only processes data through a single channel like this, but also controls various processes and exchanges data with various computers and communication systems in parallel. hand,
When performing processing in such a case, a plurality of channels are required to handle the processing.

Moreover, since these plurality of channels need to function independently, simply creating a plurality of channels as shown in FIG. 5 increases the hardware accordingly. In addition, the CPU side will also need to manage multiple channels independently, and in such cases, simply notifying the CPU of an interrupt to notify an abnormality such as written data will not be enough. In order to transition to the abnormality handling routine, extremely complicated processing must be performed. As a result, the
The load on the CPU side becomes large, and furthermore, depending on the number of channels to be processed, it may become difficult to deal with it effectively.

Therefore, the microprocessor built into the control device also has the disadvantage that it is difficult to cancel the command processing execution on the channel in which the command data error has occurred and to effectively handle the abnormality.

[Purpose of the invention]

In addition to solving the problems or drawbacks of the conventional technology, when a communication control device or input/output control device has a plurality of channels, when an error occurs in a command, etc. for one of the channels, It is an object of the present invention to provide an abnormality processing method in interface control that can easily handle an abnormality in response to a channel in which an error has occurred, either in a communication control device or an input/output control device, or on the CPU side that controls the same.

[Means for solving problems]

Means in the interface control abnormality processing method of the present invention, which achieves such objects and solves the above-mentioned problems, includes a central processing unit, an interface control device such as a communication control device or an input/output control device, and the like. In the information processing system, the interface control device includes an arithmetic processing device and has a plurality of channels, and at least Errors are detected in data related to commands, and when an error is detected, information specifying a channel or information corresponding thereto is held as identification information, and the processing unit performs a process according to this identification information. This means that processing for a channel is treated as abnormal termination.

[Effect]

When an error is detected in this way, the information specifying the channel or the corresponding information is stored and managed as identification information, so the interface control device detects the error corresponding to each channel. Processing and notification processing to the CPU side can be easily performed, and there is almost no need to increase the number of hardware circuits.

On the other hand, on the CPU side, notifications regarding abnormal termination corresponding to the channel can be received, making management easier and eliminating the need for loading.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of an abnormality processing method in interface control to which the present invention is applied, and FIGS. 2 and 3 show data parity error interrupt processing and command It is a flowchart of the processing procedure of a processing task.

Note that the same parts as shown in FIGS. 4 and 5 are designated by the same reference numerals.

20 is the main block of the communication control device, which includes, in addition to the CPU interrupt control circuit 13 and the microprocessor 10, a communication control register 21, an address decoder 22, a write data parity check circuit 23, and a memory circuit (FIFO). 24, and a μP interrupt control section 25, which is an interrupt control section for the microprocessor.

Here, the communication control register 21 has dedicated register areas for channels 0, 1, . . . , corresponding to each of the plurality of channels CH0s, CH1s, .
It has n.

Further, the address decoder 22 decodes the address given from the system bus 3 when the communication control register 21 is accessed by the CPU 2. On the other hand, the FIFO 24 is a circuit having a first-in/first-out function, and takes in the output signal of the address decoder 22 as data corresponding to each bit position, supplies the information to the microprocessor bus 11, and A signal for requesting an interrupt to the setter 10 is output.

Now, the CPU 2 uses the channel area where the communication control register 21 is located via the system bus 3,
A command or command parameter is set to perform a predetermined data transfer process. At this time, the address decoder 22 receives an address signal from the system bus 3 and decodes it to select a channel selection signal (CH0s, CH1s,...
..., one of CHns) and FIFO
24 as data.

Here, during such processing, information on the system bus 3 or between the system bus 3 and the communication control register 2 is
1, the write data parity check circuit 23 receives this command data or command parameter data and detects a parity check error therein. Then, a detection signal is output to the write data parity error signal line 23a and sent to the FIFO 24.

When the FIFO 24 receives this detection signal, it takes in the channel selection signal (one of CH0s, CH1s, . . . , CHns) output from the address decoder 22 as channel information and stores it.
Note that even if multiple write data parity errors occur, the FIFO 24 can sequentially store channel identification information corresponding to each error, and the channel identification information is stored from the time when the selection signal is first taken in. An instruction signal indicating that valid data is being stored is sent to the instruction signal line 24 until all selection information is read out by the microprocessor 10.
a, and the interrupt request signal line 2 is sent to the microprocessor 10 via the μP interrupt control unit 25.
An interrupt request is made via 5a.

Here, the instruction signal indicating that valid data is being stored from the FIFO 24 is set as a 1-bit flag in one interrupt cause register in the μP interrupt control unit 25.

Now, when the microprocessor 10 detects a command setting for a certain channel by the CPU 2, it accepts the interrupt caused by the above-mentioned write data parity, if any. The interrupt program is executed first, but if there is no such interrupt, the command processing task of the corresponding channel is activated.

Here, when the interrupt processing program is executed, the microprocessor 10 first performs the following steps.
The channel identification information in which the error occurred is read from the FIFO 24, analyzed, and processed to notify the corresponding command processing task. For example, when the control flow of the microprocessor 10 is determined by each command processing task and a predetermined program is executed, there is a dedicated file (herein referred to as a task control file) used to execute the processing. Then, this notification processing is performed by setting information indicating that the write data parity error has occurred in this dedicated file.

Then, until all the flags (displayed as flags in the interrupt cause register) that are included in the μP interrupt control unit 25 and indicate that valid data is being stored are reset, such processing will continue until a write data parity error occurs. The process of notifying each command processing task as described above is executed until all the accumulated channel identification information corresponding to the number of times is read out.

Specifically, this process is performed according to the process procedure shown in FIG.

That is, as shown in FIG. 2, in step, the error occurrence channel identification information is read, and in step it is determined whether or not an error has occurred in channel 0. As a result of this determination, if it is determined that an error has occurred, the process proceeds to step a, where the command processing task of channel 0 is notified that an error has occurred, and the process proceeds to step N. On the other hand, if the result of this determination is that no error has occurred in channel 0, the process moves to the next step, in which it is determined whether or not an error has occurred in channel 1.

Similarly, if it is determined that an error has occurred as a result of this determination, the process moves to step a, notifies the command processing task of channel 1 that an error has occurred, and moves to step N. .
If the result of this determination is that no error has occurred in channel 1, the process moves to the next step, in which it is determined whether or not an error has occurred in channel 2.

In this way, it is sequentially determined whether a write data parity error has occurred for each channel, and finally, in the same way, in step M, it is determined whether or not an error has occurred in channel n. As a result of the judgment, if an error has occurred, step Ma
If no error has occurred, the process moves to step N.

In step N, it is determined whether or not channel identification information is being stored in the FIFO 24 by referring to an instruction signal indicating that valid data is being stored. the result,
If this identification information is not stored in the FIFO 24, this process ends. On the other hand, as a result of this judgment,
If it is still being stored, the process returns to step and the same process is repeated.

Note that if an error occurs multiple times regarding the same channel, it may be unnecessary to set information to the task control file from the second time onwards.

Now, after the above-described interrupt processing program runs, the command processing task corresponding to the channel that received the command is activated. The activated command processing task determines the flow of control for the microprocessor 10 and starts executing command processing according to this, but before starting this, it first refers to the invoking task control file. do.
Then, the CPU 2 checks whether a write data parity error has occurred in the command set in the register area corresponding to the own channel of the communication control register 21 by referring to information indicating the occurrence of an error.

If information (flag) indicating that an error has occurred in the previous interrupt processing is set in the task control file, the command processing task that recognizes it will perform abnormal processing without executing normal command processing. Moving into routine.

In the abnormality processing routine, the abnormal termination of command processing due to the occurrence of the write data parity error is displayed in the status register section of the register area corresponding to the own channel of the communication control register 21, and if necessary, the command processing is abnormally terminated. effect,
Notify CPU2 by interrupt.

The command processing task then completes its processing according to the processing procedure shown in FIG.

In FIG. 3, in step b, it is determined whether there is a write data parity error occurrence notification during command setting, and if there is no write data parity notification, the corresponding command processing task is executed in step b. , the microprocessor 10 is controlled to perform regular command processing tasks.

Then, the process moves to step b, where normal termination information is set in the status register, and in step b, it is determined whether or not a termination interrupt to the CPU 2 is necessary, and if it is not necessary, this process is terminated.

On the other hand, as a result of this determination, if an end interrupt is required to CPU2, the process moves to step b.
In step b, a command processing end interrupt is issued to the CPU 2. Then, this process ends.

Now, when it is determined in step b that there is a notification that a write data parity error has occurred during command setting, in step b, error information is set in the status register of the communication control register 21, and the same process is performed. step b
Set the abnormal termination information to the status data.
Then move on to step b.

By going through these steps, the CPU 2 detects the status of the communication control register 21 or receives an interrupt from the channel, and the process in step b causes the CPU 2 to perform the command processing that it requested due to a write data parity error. It is possible to detect that the process was not executed normally and ended abnormally.

In the above embodiments, we have mainly explained the case where processing is performed by checking for write data parity errors such as commands or command parameters. Of course, an error check may be performed on the data to be read, and the checking method is not limited to the write data parity check.

Further, although the explanation is centered on an example of a communication control device, the same applies to an input/output control device, and it goes without saying that the present invention can also be applied to such devices.

〔Effect of the invention〕

As can be understood from the above description, the present invention provides an information processing system having a central processing unit and an interface control device such as a communication control device or an input/output control device, in which the interface control device includes an arithmetic processing device. and has a plurality of channels, and performs error detection on at least data related to commands sent from the central processing unit by specifying any channel among the plurality of channels, and when an error is detected. In this case, information specifying a channel or information corresponding thereto is held as identification information, and the arithmetic processing unit processes processing for that channel as abnormal termination according to this identification information, so the interface control device side , abnormality processing corresponding to each channel and
Notification processing to the CPU side is simplified, and there is almost no need for an increase in hardware circuitry.

On the other hand, on the CPU side, notifications regarding abnormal termination corresponding to the channel can be received, making management easier and eliminating the need for loading.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of an abnormality processing method in interface control to which the present invention is applied, FIG. 2 is a flowchart of data parity error interrupt processing when writing a command to the CPU, and FIG.
The figure is a flowchart of the processing procedure of the command processing task when writing a command to the CPU, Figure 4 is a block diagram of the abnormality handling method when there is one processing channel in a conventional communication control device, and Figure 5 is the FIG. 2 is a concrete explanatory diagram mainly focusing on an interface part. 1, 20...Communication control device, 2...CPU, 3
...System bus, 10...Microprocessor, 11...Microprocessor bus, 12,2
1...Communication control register, 13...CPU interrupt control unit, 22...Address decoder, 23...Write data parity check circuit, 24...Storage circuit (FIFO), 25...μP interrupt control unit.

Claims (1)

[Scope of Claims] 1. In an information processing system having a central processing unit and an interface control device such as a communication control device or an input/output control device, the interface control device includes an arithmetic processing device and processes a plurality of data. a processing channel, and performs error detection on at least command-related data sent from the central processing unit by specifying any data processing channel among the plurality of data processing channels, and detects an error when an error is detected. information specifying the data processing channel or information corresponding thereto is held as identification information, and the arithmetic processing unit processes processing for the data processing channel as abnormally terminated in accordance with this identification information. An abnormality handling method in interface control characterized by: 2 Error detection is to detect a parity error in write data that is performed by specifying a certain data processing channel, and the interface control device detects a parity error in write data when a parity error is detected in the write data. Information specifying a processing channel or information corresponding thereto is stored as identification information to cause an arithmetic processing unit to perform interrupt processing, and the arithmetic processing unit corresponds to the designated data processing channel according to the identification information. The method of the patent claim is characterized in that the presence or absence of an error is managed in response to a processing program, and upon starting execution of a command, the central processing unit is notified that processing for the data processing channel has ended abnormally, depending on whether or not an error has occurred. Abnormality processing method in interface control described in scope 1.