JPH0474248A - Start reception system - Google Patents

Abstract

PURPOSE:To quicken the processing speed and also to reduce the software decision processing operations by attaining a constitution where a CPU decides the address contents after having the accesses to plural data channel devices DCH. CONSTITUTION:A CPU writes a start command into a data channel DCH with an ST instruction and reads a channel command CCW out of an MM. Then the CPU writes the decided result of the start reception state, etc., into the MM as a condition code CDC. Then the CPU is started and decides based on the information stored in the MM whether the information is stored in the MM as the code CDC or not. If the read CDC is effective, the start processing carried out at the CPU side is completed. The DCH starts the transfer of the CDC after writing this CDC into the MM. When the transfer operation is over, the result of the transfer is stored in a control register TSR. Furthermore an end interruption report is outputted to the starting side CPU. As a result, the start time interval is reduced.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a startup reception method that reports the startup reception status in response to a drive request from a CPU via a lotus.
The purpose is to provide a startup acceptance method that enables continuous startup of the CPU and requires a small amount of hardware. In a data channel device that performs a data transfer operation between the CP and
In response to channel command information having an activation request instruction from U to the data channel device, the data channel device transmits condition code information having a activation acceptance status report according to an arbitrary address set in the channel command information. Configure to store.

[Industrial application field]

The present invention relates to a data channel device, and more particularly to a startup acceptance method for reporting a startup acceptance status in response to a drive request from a CPU via a bus.

[Conventional technology]

A computer system requires a data channel device (DC, H) that controls data transfer between the MM or CM (common memory device) and the IO packing device. For example, this data channel device typically uses D
It is activated by a CH instruction, which is a conventional method.

According to this method, in response to an activation instruction to DCH,
CDC (condition code) from directly to CPU
The startup reception status report is performed by storing it in the internal register of the SIO command, and since the command completes the report after waiting, it is possible to process SIO commands without inconsistency even if they are executed consecutively.

On the other hand, in recent years, many microprocessor sensors do not have DCH instructions, and instead use normal data transfer instructions (store instructions:
A DCH activation method using an IO map using the ST command is adopted. Even in such a system, CD
A similar activation acceptance state by C is essential, and the procedure is to refer to the control register information on the DCH side or the CDC storage area provided on the system control register on the CPU side and check its normality. There are many methods that use startup processing.

FIG. 5 is a conventional DCH activation processing flowchart (1). When the CPU activates the DCH, it first writes the control register (ODR) to the DCH using the ST command.
The start order is written to (Sl). D of this launch order
Cf (When writing is done to the inner door register ODR, the DCH writes the determination result of the activation acceptance state to the control register (
CDR). During this time, the CPLI reads the CDR in the DCH using a load command or the like and scans the state (S2). That is, after issuing a boot order, the CPU determines the contents of the CDC several times, and can obtain a determination of the reception status from the CDC after the DCH stores the determination result of the activation reception status.

On the other hand, the DCH reads the Ccw on the MM after setting the determination result of the activation acceptance state described above. The 9DCH that reads this CCW controls the data transfer operation between the roc and the MM, for example. After completing the transfer operation (S4), the result is stored in the control register TSR. And the starting cp
The end interrupt is reported to u (S5).

During the above-mentioned DCH operation, the CPU has completed the startup processing on the CPU side when the CDC is enabled, and then waits for a termination interrupt report from the DCH, and then sends the interrupt report (S5
) to accept the interrupt, remove the TSR in the DCH, and check the result. Through the series of operations described above, all processing by the DCH and the CPU for instructions such as the ST instruction is completed.

The above operation is performed by the CPU and DCH directly.
This method accesses the registers within.

On the other hand, the DCH directly writes the CDC into the register of the CPU, and the CPU reads the register in the CPU, thereby making it possible to perform the above-described transfer operation in the same way.

FIG. 6 is a conventional DCH activation processing flowchart (2). When cpv writes the activation command to DCH#o4: DCH#0 sets the determination result of the activation acceptance state to the control register CDR. (7) During the period, the CPU is
It sequentially reads registers R and EG in the register and determines whether or not CDC has been received. When DCH#0 sets the determination result of the activation acceptance state to the control register CDR (returns CDC), the CPU confirms CDC reception by reading the register REG in the CPU, and then reads CCW and transfers the DCH
#0 performs a transfer operation.

On the other hand, when the CPU starts DCH#i, D
A startup command is written to CHJ$i, and the register REG in the CPU is sequentially read to receive CDC. At this time,
Naturally, when the CDC return from DCH #i is added to the register and stored, CDC reception occurs. In the operation described above, DCH#O and DCH#i cannot be activated at the same time, and after the CDC is returned from DCH#0, DCH#
i? : Sending a startup command to the target.

[Problem to be solved by the invention]

To summarize the conventional method described above, ■ If a control register for storing CDC is provided in the DCH, multiple C
Considering the optimal conditions for DCH startup from PU,
It is necessary to provide the number of CDC storage registers corresponding to the CPU. That is, the result is that conditions depending on the system are taken into account with respect to the number of CPUs, and the amount of hardware required for the control registers also increases.

(2) If a control register for storing CDC is provided in the CPU, activation for multiple DCHs must be considered. That is, first of all, assuming that the number of sides of the control register for CDC storage is one, after the CPU starts up a certain DCH, the CPU will continue to use the next DCH for the period between those DCHs until the CDC is returned.
It is necessary to wait for activation to CH. In order to solve this problem, it is necessary to increase the number of CDC storage registers to accommodate DCH. In this case also DC
This results in consideration of system-dependent conditions such as the number of H units, and the amount of hardware required for control registers is also large.

On the other hand, in response to a request from the software side, in addition to simply reporting the quality of startup acceptance, the CDC content includes two types of judgments, including multiple reception status of DCH activation orders, IO activation status, and abnormality detection during channel program execution on DCH. It is desired that CDCl notify the contents involved. The purpose of this is to detect software abnormalities early and to make it easier to narrow down the areas where abnormalities occur.

Under these circumstances, in the conventional method, if the number of control registers for storing CDC is limited, the C
Since the DC storage control register is used, there is a problem in that the CDC can only report the reception status.

Also, assuming continuous startup from multiple CPUs, the CPU
Since the CDC cannot be displayed for LI, each CDC
It becomes impossible to compensate for the order of reporting. Also, as mentioned above (
There was a problem in that the number of registers had to be increased in accordance with the number of activation source CPUs/non-activation IOs, and the amount of hardware increased.

An object of the present invention is to provide a startup reception method that enables continuous startup of multiple CPUs and IOs and requires a small amount of hardware.

[Means and effects for solving the problem] The present invention provides a data channel device that is connected to a plurality of CPUs and a common storage device via a bus and that transfers data between the MM in these cPUs, the CM, and the IO device. This is related.

Channel core with activation request instruction from CPU 7
) - information t[a (c c w) is the data channel HD
It has an address to store condition code information (CDC) on the CH. This CCW is
When the data channel device fDCH reports the activation acceptance status in response to the activation request instruction in the channel command information, the condition code information CDC is sent to the data channel device DCH as specified in the channel command information. Store in address. In other words, channel commands are issued from the CPU, but even if channel commands are sent to multiple data channel devices separately, the condition code information CDC from the data channel device DCH is added to the specified separate addresses. .

The CPU can determine the content of the specified address (condition code information) after accessing multiple data channel devices WDCH, which can speed up processing and reduce software determination processing. The amount of can also be reduced.

〔Example〕

The present invention will be described in detail below using the drawings.

FIG. 1 is a flowchart (1) of a DCH activation process according to an embodiment of the present invention. When cp, u activates, for example, an ST command, it writes the activation command to the target DCH (SIO). That is, a command is written to the DCH internal door control register (DR) using the ST command. This write causes the DCH to read the CCW on the MM. Then, the determination result such as the activation acceptance state is written to the MM as CDC (Sll). After being activated by the ST command, the CPU reads out from the MM and determines whether or not the specified information is stored as a CDC in the MM.

That is, a load command reads the CDC on the MM and scans the state. This scan is CDC from DCH
It is assumed that the CDC is being executed before the writing of the CDC, and that the CDC is received for the first time after the CDC is written, and the reception status of the CDC is determined. C if the read CDC is valid
The startup process from the PU side is completed, and the end interrupt from the DCH is awaited. After DCH writes CDC to MM (S12), it starts a transfer operation (S13). After the transfer operation is completed, the result is stored in the control register TSR. Furthermore, a termination interrupt report is sent to the starting CPU (S14).
) is output. When the CPU receives this end interrupt report, it accepts the interrupt, reads the TSR in the DCH, and confirms the result.

FIG. 2 is a configuration diagram of a control command for startup, and FIG. 3 is a configuration diagram of a CCW. The DCH is included in the startup control command mentioned above.
For the address ADR, sender ID (DCH number), internal address (ODR address), order type (e
x, 5IO), but the DA has a command address (CMA)
exists.

From the command address in this startup control wholesale command
The CH reads the CCW and executes command processing. The command stored within that command address is C
CWO is command code, l0A (activated IO), number of transferred bytes, CCWI is DA (data address), CCW
2 is CDA (CDC storage address). This CC
CDA (
(CDC storage address), and the DCH stores the CDC at this designated address.

Conventionally, this CDC storage address is not specified, so the CPU must, for example, sequentially read the registers in the DCH, but according to the present invention, the CDC storage address is specified by ODA, so the CPU is the specified CDA (CDC storage address)
The contents of the CDC can be determined from the address specified in .

FIG. 4 is a flowchart (2) of the DCH activation process according to the embodiment of the present invention. In the embodiment shown in FIG. 1 described above, C
Although one DCH is activated from the PU, in the embodiment of the present invention shown in FIG.
CH#i) is running. When starting two DCHs, the CPU starts DCH#O first, for example.
), immediately read the CDC of DCH#O (S22),
Subsequently, DCH#i is activated (S23). Then, the CDC of DCH#O/i is read again in the same manner.

That is, DCH#0 is activated at time T1 and activated at time T2.
DCH#i is activated in Conventionally, 2
Both DCH#O cannot be accessed at the same time, but each DCH#O
, DCH#i are designated separately in CCW2 and written to each one, so even if the CDCs are written at the same time, they will not disappear and can be accessed at the same time.

After starting DCH#i, CDC of DCH#0/i
is read (S24). This is read because DCH#0DCH#i are activated at the same time, and during this time, DC
H#0. DCH#1 executes reception processing corresponding to each requested command.

For example, when DCH #0 returns the CDC to the memory (S25), this data is received in CDC reading processing S26 of DCH #0/i after confirming that DCH #0 has returned the CDC. This allows for example CDH#
It is determined that O has been accepted. At this time, DCH9i
is still processing requests for startup commands. Subsequently, the CPU sequentially reads the CDC of DCH#i (S27, 328).

DCH# i finishes processing, returns CDC, and stores memory M
When the CDC is stored in EM, the CDC of D CH#i is
The process executing the read reads the CDC of DCH#i after the CDC is stored, and thereby the CDC of DCH#i can be received.

As mentioned above, activation of DCHs, which conventionally had to be performed sequentially, can be performed successively, and after activation, activation requests are accepted for each DCH.
Judgments such as whether or not the request is made can be obtained from the returned CDC, and the request is first sent without starting the DCH in an orderly manner, etc., and then the request is accepted, etc. Judgment can be made and the activation time interval can be shortened.

[Effects of the Invention] As described above, the present invention has the following effects.

- The CDC storage area can be set individually for each startup process, so there is no need to worry about the CDC being rewritten.

■When assuming continuous startup from multiple CPUs, C
Since the CDC can be displayed in accordance with the PU, the order of CDC reporting can be guaranteed.

- The CDC storage area can be set at any address, making it easy to increase the flexibility of the system.

■In addition to simply reporting the quality of startup reception, CDC contents can also include information such as the multiple reception status of DCH startup orders, IO startup status, abnormality detection during channel program execution on DCH, etc., and trouble handling by software. be able to provide valid information to

[Brief explanation of drawings]

Fig. 1 is a flowchart of DCH activation processing according to an embodiment of the present invention (1), Fig. 2 is a configuration diagram of activation control commands, Fig. 3 is a CCW configuration diagram, and Fig. 4 is a DCH activation process according to an embodiment of the present invention. Processing flowchart (2), FIG. 5 is a conventional DCH activation processing flowchart (1), and FIG. 6 is a conventional DCH activation processing flowchart (2). DCH...Data channel device, CDC...Condition code information, CCW...
- Channel command information. Figure 2

Claims (1)

[Claims] Connected to multiple CPUs and common storage devices by a bus,
In a data channel device (DCH) that performs a data transfer operation between an MM or CM in the CPU and an IO device, channel command information (CCH) having an activation request instruction from the CPU to the data channel device (DCH) is provided.
CW), the data channel device (DCH) stores condition code information (CDC) having a startup reception status report according to an arbitrary address set in the channel command information (CCW). Data channel activation reception method.