JPH0429101B2 - - Google Patents

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art and Problems to be Solved by the Invention Means for Solving the Problems Effects of the Invention Embodiments Effects of the Invention [Summary] Communication control processing In the microprogram-controlled channel connection adapter of the device, the data buffer area on the control memory is divided into two areas (A, B).
When one side is used for transfer with the channel and the other is used for cycle steal transfer between main memory, each side of the divided data buffer area ( A, B) are provided with a buffer final address bit indicating the end position and a transfer stop bit indicating the end of data transfer with the channel. By providing means for monitoring the buffer final address bit and the transfer stop bit, the monitoring means can monitor the buffer final address bit,
Or, when a transfer stop bit is detected, it generates an interrupt to the microprogram, recognizes the area (side A or B) where data can be transferred by cycle steal, and writes the data buffer area (side) of the above two sides on the control memory. A and B) are used alternately for data transfer with the channel side and cycle steal transfer with the main memory side.

[Industrial application field]

The present invention relates to a data transfer method in a communication control processing device, and particularly to a data transfer method between a main memory and a channel.

With the recent improvement in the performance of computer systems,
The onlineization of computer systems is being promoted.

In this online system, data is transferred online between the host system and the terminal device using a data line, but as the online system is promoted, the amount of data that must be processed by the host system is increasing. As the number of data lines increases, high-speed data lines are also being connected to some of the lines.

Under these circumstances, there has been a demand for measures to effectively improve throughput in communication control processing devices, which are the core of online systems.

[Problems to be solved by conventional technology and invention]

FIG. 4 is a diagram showing the configuration of a general communication control processing device, FIG. 5 is a diagram showing an example of a channel connection adapter in a conventional communication control processing device, and FIG. 6 is a diagram showing a conventional communication control processing device. FIG. 7 is a diagram schematically showing an example of another data transfer method.

First, in FIGS. 4 and 5, the main control unit 2 of the communication control processing device and the channel connection adapter 1
It is assumed that both are controlled by microprograms.

Here, the conventional technology will be explained, focusing mainly on the case of transferring data from the main memory to the channel among the data transfer between the channel of the host system and the line.

In the data transfer operation from the main memory 21 to the channel, the data in the main memory 21 is first transferred to the data buffer 110 in the control memory 11 by a cycle steal operation under hardware control (not shown) in the control processor 12. The data is transferred, and then, by the hardware operation within the channel connection section 13 that operates upon activation from the microprogram executed by the control processor 12,
It functions to transfer the data in the data buffer 110 on the control memory 11 to the channel side.

For this reason, a microprogram in the control processor 12 in the channel connection adapter 1 that is started by an input/output instruction (SIO) from a host system (not shown) is configured to determine the data address on the main memory 21, the number of bytes to be transferred, In order to instruct the transfer direction, the control processor 12 sets control data in the main memory address register (MSA) 120, byte counter (BC) 121, and cycle steal control register (CSC) 122, respectively.

At this time, the data buffer 1 on the control memory 11
Data is also set in the control storage address register (CSA) 123 to indicate the location of 10.

In the control processor 12, when the cycle steal operation is started by setting control data in the cycle steal control register (CSC) 122, the instruction execution operation in the control processor 12 is stopped, and the control processor 12
Only the data transfer operation between the main memory 21 and the data buffer 110 in the control memory 11 via the internal bus is performed by the internal hardware.

When the cycle steal operation is completed, the hardware (not shown) in the control processor 12 generates an interrupt to the microprogram, and when the microprogram recognizes this interrupt, the data transfer controller 1
Start 32.

The data transfer control unit 132 transfers the cycle steal transfer data read from the data buffer 110 of the control memory 11 to the channel via the data holding register (DB) 131.

However, in the conventional data transfer between the main memory 21 and the channel, since the data buffer 110 on the control memory 11 has only one side, the data transfer between the channel and the cycle from the main memory 21 is There was a problem that it was not possible to simultaneously perform data transfer using steal.

Next, as shown in FIG. 6, there is an improved data transfer method in which the single-sided data buffer 110 performs data transfer to and from the channel and data transfer by cycle stealing to and from the main memory 21 at the same time. Explain.

First, when the control processor 12 executes a specific microprogram, a cycle steal start address (AO) is set in the main memory address register (MSA) 120, and the cycle steal operation is started. Transfer data due to the cycle steal is prepared in the shaded area in FIG. 1A, and the address of the main memory address register (MSA) 120 changes to A0A1.

In this state, from the channel side, for example,
When a read command is set in a command register (not shown) and a specific microprogram is activated, data transfer to and from the channel is started, and a data buffer address indicating the location of the data to be sent to the channel is set. The contents of register (DBA) 130 change sequentially starting from B0.
Becomes Bn.

At this time, while the relationship Bn<A1 is maintained, data transfer to the channel is possible, and this address comparison is performed by the comparison calculation unit 124.

On the other hand, in the second cycle steal operation described above, the data transfer to the area A1 to A2 and the above channel shown in figure b is completed.
In the range from A0 to A3, it can be executed in parallel with data transfer to the above channels.

Therefore, the comparison calculation unit 124 compares the Bn with the cycle steal address An,
A cycle steal operation can be performed within the range of Bn>An.

By repeating the above operations, data transfer to and from the channel and data transfer by cycle stealing can be performed simultaneously and continuously.

However, in this method, hardware (comparison calculation unit) 1 is used to calculate the address comparison between the data transfer address (DBA) to the channel and the cycle steal address (MSA).
24 was required, and the complexity of the comparison logic was a problem.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional drawbacks, it is an object of the present invention to provide a data transfer method between a main memory and a channel that does not require a large increase in hardware and can be easily controlled by a microprogram. be.

[Means for solving problems]

FIG. 1 is a diagram explaining the concept of the present invention. In the present invention, provided in the channel connection adapter 1 controlled by a microprogram,
The data buffer area 110 on the control memory 11 is
The area of the surface is divided into A side and B side, and when one side is used for transfer with the channel, the other side is used for cycle steal transfer with the main memory 21. A buffer final address bit 111 indicating the end position of each side (A, B) of the divided data buffer area and a transfer stop bit 112 indicating the end of data transfer with the channel are provided. For example, each time one byte is transferred, the buffer final address bit 111 and transfer stop bit 112 are monitored, and the buffer final address bit 111 or transfer stop bit 112 is monitored.
is detected, an interrupt is generated to the microprogram, and when the interrupt transitions to a specific interrupt processing, the area where data transfer is possible by the next cycle steal (plane A,
or B) recognize the data buffer area (A, B) 110 on the two sides of the control memory 11;
is configured to be used alternately for data transfer with the channel side and cycle steal transfer with the main memory side.

The buffer final address bit 111 and transfer stop bit 112 are monitored by a monitoring section 132a within the data transfer control section 132.

[Effect]

That is, according to the present invention, in a channel connection adapter controlled by a microprogram in a communication control processing device, the data buffer area on the control memory is divided into two areas (A, B), and one side is used for transfer with the channel. In order to use the other side for cycle steal transfer between the main memory and the main memory, a buffer final buffer indicating the end position of each side (A, B) of the two divided data buffer areas is written on the control memory. An address bit and a transfer stop bit for instructing the end of data transfer with the channel are provided, and the buffer final address bit and transfer stop bit are monitored each time, for example, 1 byte is transferred during data transfer with the channel. By providing means, when the monitoring means detects the buffer final address bit or the transfer stop bit, it generates an interrupt to the microprogram and checks the area (plane A or B), and transfers the data buffer areas (A, B) on the two sides of the control memory to the channel side;
Cycle-steal transfers with the main memory side are used alternately, so data transfer efficiency between the communication control processing unit and the host channel is improved without significantly increasing hardware. There is an effect that can be done.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.
FIG. 2 is a block diagram showing an embodiment of the present invention, showing details of a channel connection adapter, and FIG. 3 is a time chart showing the data transfer operation according to the present invention. , a shows the transfer operation from the main memory to the channel, and b shows details of the transfer operation from the control memory to the channel.

In FIG. 2, a data buffer 11 consisting of two sides (A, B) provided on a control memory 11
0, the buffer final address bit 111 in the table area (A, B) 110' provided corresponding to the data buffer 110, the transfer stop bit 112, and the buffer final address bit 111 in the data transfer control unit 132.
and the transfer stop bit 112 (monitoring section) 132a, and related mechanisms are functional blocks necessary to implement the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

First, in the same manner as in the conventional system, the control processor 12 reads and executes a specific microprogram from the control memory 11, thereby loading the main memory 2.
1, the main memory address register (MSA) 120, byte counter (BC) 121, and cycle steal control register (CSC) 122 in the control processor 12, Set control data for each.

At this time, data is also set in a control storage address register (CSA) 123 in order to indicate the location of any one of the data buffers (sides A and B) 110 on the control storage 11.

In the control processor 12, when the cycle steal operation is started by setting control data in the cycle steal control register (CSC) 122, the instruction execution operation in the control processor 12 is stopped, and the control processor 12
Only the data transfer operation between the main memory 21 and the control memory 11 is performed by the internal hardware via the internal bus.

When the cycle steal operation is completed, the hardware (not shown) generates an interrupt to the microprogram of the control processor 12, and when the microprogram recognizes this interrupt, the data buffer ( In order to shift the data being transferred to either side A or B side 110 to the operation of starting data transfer to the channel, the data transfer control unit 1
Start 32.

At this time, the microprogram executed by the control processor 12 writes the data buffer (A, B) 1 transferred in the cycle steal operation to the data buffer address register (DBA) 13.
10 and table area (A, B) 1 of the control memory 11.
When the buffer final address bit 111 provided at 10' and the number of remaining transfer bytes become less than the capacity of the data buffer (A or B) 110, the transfer operation is terminated midway through the data buffer (A or B) 110. transfer stop bit 1
Set 12.

When these pieces of information are set and the data transfer control section 132 starts data transfer with the channel, as shown in the time chart of FIG. 3b, the hardware in the data transfer control section 132 The software accesses the data buffer (A, B) 110 based on the contents of the data buffer address register (DBA) 13 and reads out, for example, 1 byte of data necessary for one data transfer, Data holding register (DB) 13
1 to the channel, and in the next cycle, the monitoring unit 132a modifies the specific bits of the data buffer address register (DBA) 130 and transfers the data to the data buffer 11.
Table area (A,
B) Access 110' and write the buffer final address bit 111 and transfer stop bit 11.
2, and if any of the bits is detected to be 'on', the microprogram is interrupted.

When the microprogram recognizes that the interrupt is an interrupt in which the transfer stop bit 112 is 'on', it means the end of the transfer data, so it starts processing to finish the data transfer, but the buffer final address bit 111 When the interrupt is detected as being 'on', the data buffer (side A or B) 11 used for data transfer with the channel at that time is
0 is now available for data transfer from the main memory 21 by the next cycle steal,
Control is performed to continue the cycle steal operation.

FIG. 3a shows the cycle steal operation described above,
This is a time chart showing the data transfer operation to the channel, where indicates the cycle steal operation and indicates the data transfer operation to the channel.

As is clear from this figure, in data transfer according to the present invention, two data buffers (A, B) 110 on the control memory 11 are used for data transfer on the channel side and data transfer by cycle stealing from the main memory 21. The data transfer is performed alternately, ensuring continuity of data transfer.

As described above, in order to transfer data between the main memory and the channel, the present invention provides, for example, two data buffers on the control memory, and a bit indicating the final address of the data buffer and a bit indicating the end of the transferred data. The usage status of the data buffer is determined by monitoring the transfer stop bit indicating the data transfer to the channel each time data is transferred to the channel, and detecting that any of the bits is turned on. The feature is that the transfer operation with the channel and the cycle steal operation can be executed at the same time.

〔Effect of the invention〕

As described above in detail, the data transfer method in the communication control processing device of the present invention is such that the data buffer area on the control memory is divided into two areas (A, B) divided into
When one side is used for transfer with the channel, the other side is used for cycle steal transfer with the main memory, so each side (A, B) of the data buffer area divided into two is placed on the control memory. A buffer final address bit indicating the end position and a transfer stop bit indicating the end of data transfer with the channel are provided, and during data transfer with the channel, for example, each time one byte is transferred, the buffer final address bit is set. and a transfer stop bit, the monitoring means can:
When the buffer final address bit or transfer stop bit is detected, an interrupt is generated to the microprogram, the area (plane A or B) in which data can be transferred by cycle steal is recognized, and the The two data buffer areas (A, B) are used alternately for data transfer with the channel side and cycle steal transfer with the main memory side.
This has the effect of improving data transfer efficiency between the communication control processing device and the host channel without significantly increasing hardware.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the concept of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, and Fig. 3 is a diagram explaining the concept of the present invention.
The figure shows a time chart of the data transfer operation according to the present invention, FIG. 4 shows the configuration of a general communication control processing device, and FIG. 5 shows an example of a channel connection adapter in a conventional communication control processing device. The figure shown in FIG. 6 is a diagram schematically showing an example of another conventional data transfer method. In the drawing, 1 is a channel connection adapter;
1 is a control memory, 110 is a data buffer (A,
B), 12 is a control processor, 120 is a main memory address register (MSA), 121 is a byte counter (BC), 122 is a cycle steal control register (CSC), 123 is a control memory address register (CSA), 124 is a comparison operation 13 is a channel connection part, 130 is a data buffer address register (DBA), 131 is a data holding register (DB), 132 is a data transfer control part, 132a is a monitoring part, data transfer by cycle steal, is to a channel data transfer, respectively.

Claims (1)

[Scope of Claims] 1. A communication control processing device under microprogram control, which includes a control memory 11 that defines at least a microprogram area and a data buffer area 110.
and a main memory address register indicating a cycle steal start address on the main memory 21 for performing cycle steal transfer between the main memory 21 in the communication control processing device and the data buffer area in the control memory 11. (MSA) 120, and a control memory address register (CSA) 12 that holds the data buffer location on the control memory 11.
3, a byte counter (BC) 121 that holds the maximum number of transferred bytes, a cycle steal control register (CSC) 122 that controls the cycle steal operation, and the control memory 11 for data transfer between the channels. A microprogram controlled channel having a data buffer address register (DBA) 130 for holding data locations on the channel, and a data holding register (DB) 131 for sending data to or receiving data from the channel. In the connection adapter 1, the data buffer area 110 on the control memory 11
is divided into two areas (A, B), and when one is used for transfer with the channel, the other is used for main memory 2.
To use for cycle steal transfer between 1 and 1,
On the control memory 11, a buffer final address bit 111 indicating the end position of each side of the divided data buffer area and a transfer stop bit 11 indicating the end of data transfer with the channel are stored.
2, and during data transfer with the channel, the buffer final address bit 111 and transfer stop bit 112 are set every time n bytes (n is a positive integer) are transferred.
means 132a for monitoring the buffer final address bit 111 or transfer stop bit 11 by the monitoring means 132a;
2 is detected, a means (INT) for generating an interrupt to the microprogram is provided, and when the interrupt signal generated by the interrupt means (INT) causes a transition to a specific interrupt processing, the next processing is performed. Recognizing the area (surface A or B) 110 where data transfer by cycle steal is possible,
The data buffer areas 110 on the two sides (A, B) on the control memory 11 are transferred by data transfer with the channel side and cycle steal transfer with the main memory side.
A data transfer method in a communication control processing device characterized in that the data transfer method is used alternately.