JPS6367665A - Data processor - Google Patents

Abstract

PURPOSE:To simplify the logic structure of a data processor by adding a bus width extension display means and a display withdrawal device to an input/ output controller and then a means which recognizes the display of said bus width extension display means and a means which recognizes the withdrawal of the bus width extension display to a channel device respectively. CONSTITUTION:A conventional bus width extension display section is extended up to a point where a SERVICE-OUT line serving as an answer to a STATUS-IN line is set at '1'. When the bus width extension display is erased before the STATUS-IN line is set at '1', a channel device 2 recognizes that an input/output controller 3 has withdrawn the use of an extension bus and then always performs the control/sense byte transfer just with a single piece of bus. A bus width extension display withdrawal recognizing circuit of the device 2 recognizes that the controller 3 has withdrawn the bus width extension display. Thus no consciousness of extension bus is required even to a control/ sense command, therefore the control logic of a data processor is simplified.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing device, and in particular, to an input/output interface between a channel and an input/output control device, in which the number of buses used for data transfer is determined for each input/output instruction. The present invention relates to a data processing device that can be arbitrarily selected.

[Conventional technology]

Conventionally, in order to reduce the data transfer time between external storage devices, CPUs, and main storage devices, multiple data buses have been used for data transfer between channel devices and input/output control devices that control external storage devices. This is achieved by making Specifically, it is conceivable to physically reduce the number of bus lines from one to two, or to logically reduce the number of bus lines to two by using the bus lines bidirectionally. for example,
If the data bus between the channel device and the input/output control device is bidirectional to achieve a data transfer rate of 61vl B/S, the protocol (bidirectional bus usage) display will be displayed before receiving commands from the channel. The I/O controller is intended to serve the channel device. Therefore, since it is impossible to select a command and select a protocol, it is necessary to transfer control bytes and sense bytes that do not require high-speed transfer using a bidirectional bus protocol, and the control logic has become a double current, reducing reliability.

An example of this type of system that uses two bus lines is the "r data transfer system" described in Japanese Patent Application Laid-Open No. 60-74072. In the system described in the above publication, in addition to data transfer drivers and data reception receivers for channel devices and input/output control devices, new drivers and receivers are connected in parallel to enable data bus out and data bus in. It can be used in both directions, almost doubling the data transfer speed.

In these systems, a plurality of input/output control devices that physically/logically use one or two data bus lines coexist, and these are connected to a channel device via the same interface. Then, when each input/output control device transfers data, there is a method for each input/output control device to indicate to the channel device whether to use one data bus line or two data bus lines. is commonly practiced.

Figure 2 is a connection diagram of a conventional computer system.
FIG. 3 is a signal time chart of the input/output interface in FIG. 2.

Channel device i! ? Input/output control devices 3-1.3 are connected to two data bus lines 100 and 101 extending from 2, respectively.
-2. ...3-n is connected.

In that case, the input/output control device 3-2 uses only the first data bus NiA100, and the input/output control device 3-1 uses the first and second data buses vA100, 101.
．． 3-n are connected to the channel device 2 in a mixed manner. Conventional signal exchange operations until the input/output control device 3-1 starts data transfer with the channel device 2 are performed in the sequence shown in FIG. In other words, the input/output request from the CPU to the input/output control device 3-1 causes the
Since the g device 2 is logically connected to the input/output control device 3-1, the first data bus, ! ! 101 outputs an address for identifying the input/output control device 3-1, and ADD
After outputting It 117 to the RESS OUT line,
5ELECT 0UTlil is set to 11".The input/output control device 3-1 must be able to perform the following operations with the channel device if the address of the first data bus line matches its own address. 5ELECT
0PERATIONAL I in response to the OUT line
Let the N line be II 11g. At the same time, input/output control device 3
-1, data transfer is performed on the first and second data bus lines 1
MARK corresponding to data bus line 100.101 to indicate intention to use 00 and 101.
Set OIN4@ and MARKI IN wire to 151”. Channel device V!12 is 0PERATIONAL.
When you realize that the IN line has become 11111, A
While setting the DDRESSOUT line to tr Otr,
A command indicating an input/output command is sent to the first data bus line 100.
Output to , and perform the quasi-wei command sending. In addition, the channel device 2 receives MARKOIN from the input/output control device 3-1.
It recognizes that the MARKITN and MARKITN lines are both "1", and recognizes that the first and second data bus lines 100 and 101 are used when executing the corresponding input/output command. The input/output control device 3-1 is an ADDRESS
Recognizing that the 0trT line has become u Opg,
The address at which the input/output command is to be executed is output to the first data bus line 100, and ADDRESS IN!
! Let Ll I II. Channel device 2 is ADD
When it is recognized that RESSNm has become 111H, it is checked whether the address on the first data bus line 100 is the address at which an input/output command is to be executed, and if it is correct, the input/output command is executed. To send the command, set the COMMAND OUT line to "1". The input/output control device 5!3-1 is COMMAND
When you realize that the OUT line has become It I II,
The command on the first data bus line 100 is received and A
Set the DDRESS IN line to 11011.

Next, the input/output control device 3-1 analyzes the received command, and if the command can be executed, outputs a status byte to that effect to the first data bus line 100, and outputs a status byte to the first data bus line 100. Make the line II 1 '7. When the channel device 2 recognizes that the STATUSIN line is II 171, it receives the status byte on the first data bus line 100 and outputs 5ERVICE 0UTJ”
u 1 u nil il. For Koreni, 3-1 in the input/output control table is 5 TATUS IN1! A II O
+1, and channel device a2 is set to 5TATUS I
・Nfi's II OPH! 7! 5.
After setting the ERVICE OUT line to "o", if the above command involves data transfer, execute the data transfer using the first and second data bus lines 100 and 101. .

Thus, in the process of interface signal exchange.

The display of the number of data bus lines used during data transfer, that is, the bus width expansion display is 0PERATI.

Set the NAL IN line to II I H, then ADDR
This is performed in the section where the ESS OUT line is 110", and is displayed from the input/output control device 3-1 before receiving or receiving a command indicating an input/output command from the channel device 2. In other words, the CONfMAND OUT line is #11
4, bus width expansion display is performed.

Input/output commands can be broadly divided into Control commands, 5e
In addition to the n5e command and the Read/Write command, the Cont and rol commands are commands for transferring control bytes of the input/output device from the channel device to the input/output control device. Further, the S cnse command is a command to transfer detailed data of an input/output device error from the input/output control device to the channel port. Read / Write
For example, in the case of a magnetic disk device, the command is 1 to read the data stored in the magnetic disk device,
A (Read command) command to transfer the data to the channel device via the control device and store it in the main memory, read the data stored in the main memory, transfer it from the channel device to the control device, and send it to the magnetic disk device. Record it in (
This is a write command. Generally, Control
Data transferred with the /S anse command does not require high speed, and only data transferred with the Read/Write command requires high speed. Therefore, in an input/output control device controlled by a microprogram, Cont, rol/S en that does not require high speed
Data transfer for the se command is executed by a microprogram, and data transfer for the Read/Write command, which requires high speed, is executed by hardware. Furthermore, when transferring data using a microprogram, it is normally performed for each byte (8 bits + 1 parity pit).

[Issues that the invention attempts to resolve]

In this way, in conventional data processing devices, before the input/output control device receives a command byte indicating an input/output instruction, it is necessary to display the bus width expansion to the channel device. Regardless of the circumstances, the bus width expansion display must be performed, and data transfer must be performed in the bus width expansion mode. Therefore, when a microprogram transfers in the bus width expansion mode in the Control command, the transfer request is made for each byte, so the data bus lines must be used alternately.
Logic is needed to control the alternation. In that case, if you provide alternating control logic on the channel device side, the input/output control end side only needs to transfer data using one data bus line, so control on the input/output control table side is simple. However, the channel device side becomes complicated. Thus, alternating control logic is required for either individual. In addition, when one input/output control device is controlled by multiple channel devices, for example in the case of cross-call control, the input/output control device transfers data with one channel device in bus width expansion mode, and The channel device requires complex control such as data transfer using a single data bus line.

Therefore, when performing data transfer using a microprogram in such a case, in a mode that uses one data bus, data buses are not used alternately, and in bus width expansion mode, two data buses are used. The problem is that control logic for both modes must be provided for alternate use.

An object of the present invention is to resolve such problems, select the type of input/output commands, and use an expansion bus only for data transfers that require high speed, and data transfers that can be performed at low speeds. The objective is to provide a data processing device that uses only one bus at any given time.

[Means for solving problems]

In order to achieve the above object, the data processing device of the present invention includes:
In a data processing device where multiple input/output control devices can arbitrarily select the number of data bus lines used for data transfer, the input/output control device has a bus width expansion function to use multiple data bus lines. The channel device includes a display means and a means for canceling the display of the means, and a means for recognizing the display of the bus width extension display means and a means for recognizing that the bus width extension display has been withdrawn. There is a characteristic in doing.

[For production]

Conventionally, the bus width expansion display section was 0PRATI.
Set the ONAL IN line to If l II and then ADD
RESS OUT! However, in the present invention, it is extended from the conventional bus width expansion display section to ○PERATI○NAL.
After setting the IN line to 1", the 5ERVICE OUT line, which is a response to the 5TATUS IN line, becomes II.
1) This is the section up to H (see Figure 4 of Kaya). Also, if the bus width expansion display disappears before the 5TATUS IN gland reaches It I 11, the channel device will perform input/output control'! Recognizing that An has withdrawn the use of the expansion bus, the Cont and rol bytes/5ense bytes are always transferred using only one bus. That is, the bus width expansion display withdrawal circuit.

In order to transfer data for input/output commands other than Read/Write commands without using the expansion bus, the bus width expansion display for the channel device is canceled. The bus width extension display cancellation recognition circuit of the channel device recognizes that the input/output control device has canceled the bus width extension display.

This allows the input/output control device to cancel the expansion bus usage indication that has been displayed once, so the Control/S
There is no need to be aware of the expansion bus for the ensa command, and the control logic can be simplified.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a signal coupling diagram of a channel device and an input/output control device showing an embodiment of the present invention. FIG. 4 is a signal time chart of FIG. 1. In FIG. 1, 24 is an input/output control device. A data transfer circuit for transferring data to and from the control circuit w13, 100 and 101 are data bus lines, 20 is a flip-flop that stores expansion bus usage, 21 is an AND gate, 22 is an inverter circuit, and 23 is an expansion bus. ♂ gourd circuit, 10 is a flip-flop that stores expansion bus use in 3 for input/output control device, 11 is OR gate, 12.13 is AN
14 is a delay circuit for delaying the S reading time; 15 is a command decoding circuit for decoding the challenge command sent from the channel device 2; and 16 is an expansion bus usage display circuit.

In order to logically connect the channel device 2 and the input/output control device 3 when executing an input/output command, when exchanging a series of input/output interface signals, the channel device rrt 2
(L) A D D RE S S OUT t
j5 O and 5ELECT OUT wires respectively
I II, but the description is omitted in FIG.

Next, the 0PERΔTI○NALIN line from the controller=3 is set to 1g 1 II, and at the same time, the flip-flop 10 is set to memorize that the expansion bus will be used. When the flip-flop 10 is set, the output "1"' is input to the expansion bus display circuit 16, so that the NfARKOIN line and the ~1ARK I
Niwo "1' toshi, channel equipment rrL2 vs.

starts displaying that the expansion bus will be used during data transfer. As a result, in the channel device FrL2, the expansion bus recognition circuit 23 recognizes that the input/output control device 3 is displaying expansion bus use, and stores the result by setting the flip-flop 20. Next, the ADDRESS IN line from the input/output control device 3
In response to II, the channel device rI12 sends COM MA N DOUTfi to the input/output controller 3.
1, and simultaneously sends the contents of the command via the data bus line 100. In the input/output control device 3, COM
Delay circuit 1 for the M A N D OUT line signal
4 and the decoded signal and an AND gate
3 to synchronize 6 while data bus line 100
The command sent by the command is decoded by the command decoding circuit 15, and the decoding result is used as a command that does not require high-speed data transfer (for example, Con
(trol command, sense command, etc.), that fact is output to AND controllers 1 to 13. AN
When the D gate 13 performs an AND operation between the signal delayed by the delay circuit 14 and the signal decoded as low-speed transfer, the flip-flop 10 is reset by the signal passed through the OR gate 11. That is, it recognizes that the command from the channel device 2 is a transfer that does not require high speed, stops storing the use of the 5 expansion bus, and sets the signal from the flip-flop 10 to the display circuit 1G to 110H. The expansion bus display circuit 16 displays MARK OIN! in order to indicate to the channel device 2 that the expansion bus is no longer used for the command in question. and MARKIIN wire to 1
Set it to 0”.

Thereafter, the input/output control device 3 outputs the initial state byte to the data bus line 100, and outputs the STATUS INA
* is set to 111", and at the same time, this signal 111B is input to the AND gate 12. When channel device = 2, the signals II, II, and II of this 5TATUS IN line are ANDed.
game]・21, and the expansion bus recognition circuit 2
The output of 0PERATIONAL IN is also input to the AND gate 21 via the inverter 22.
The line signal HI II is also input to the AND gate 21. Since the MARK OIN line and the MARK I IN line are '0', the output of the expansion bus recognition circuit 23 is '0'.
0'' and is inverted by the inverter circuit 22 to become 1'ν'
is input to the AND gate 21. Therefore, the AND gate 21 takes the AND and outputs '1', resetting the flip-flop 20. By resetting the flip-flop 20, it is confirmed that the expansion bus display from the input/output control circuit 3 has been withdrawn. This is recognized and the output line to the data transfer circuit 24 becomes II OH, thereby notifying the data transfer circuit 24 that the bus width expansion display has been canceled. , without using the second data bus line 101.
Data transfer is performed using only the data bus line 100 of.

On the other hand, the command from channel device E3 is Read/Wr.
At the time of the ite command, the decoding circuit 15 decodes that high speed is required, so by outputting the signal II Ou to the AND gate 13, the AND gate 13
ND cannot be taken, so the flip-flop 10 is not reset and continues to be set. In addition, the signal u I T+ of the 5TATUS IN line from the input/output side control unit 3
And channel′! From device 2 (71SERVICE
When the signals LL I II OUT and t@ are input to the A N D gate 12 of the input/output control device=3, the A
Since AND can be performed with the ND gate 12, the signal II 14
4 is input to the reset terminal of the flip-flop 10 via the OR gate 11, and the flip-flop 10 is temporarily reset. However, the 5TATUS IN line is 11
At the same time as going from 114 to +10 II, ○PERAT
I○NAL IN [(7) Since the flip-flop 10 is set again due to the "1" signal, the expansion bus display circuit 1G displays MARKOIN green and MARK I IN! ;
Continue to output “1” to @.

As is clear from comparing Fig. 4 and Fig. τ3, the difference between the signal of this embodiment and the conventional signal is that MARKOINf
With i? II I 1 by vlARK I IN line
1 is sent, and the rest is the same. That is, in the past, after the 0PERATIoNAL IN line became 11", the ADDRESSOUT line became 110".
'H, and the expansion bus usage display ended before the command from the channel device 2 was decoded, which was inconvenient. However, in this embodiment, the expansion bus usage display ends. The start of the display is the same as before, but
After that, the display can be canceled after decoding the command, and if not canceled, the display will continue until the end.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to select the type of input/output instruction and use the expansion bus only when transferring data that truly requires high speed.
．． When a microprogram transfers one byte at a time, such as the data transfer of rol/5ense:l cloak, one bus is used for execution, so there is no need for control logic that is aware of the expansion bus.

The logical structure can be simplified.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a channel device and input/output control device showing an embodiment of the present invention, Fig. 2 is a connection system diagram of a conventional computer system, and Fig. 3 is a time chart of signals of a conventional input/output interface. , FIG. 4 is a signal time chart of the input/output interface in the present invention. 1: cPU, 2: channel device, 3: input/output control device,
4: Main memory, 5: Input/output device. 10.20 Niblip prop, 15: Command reading circuit, 16: Expansion bus use display circuit, 23: Expansion bus use display recognition circuit, 2: Data transfer circuit. Figure 2 Figure 3 Figure 1 (Q

Claims (1)

[Claims] 1. A channel device and a plurality of input/output control devices are connected on the same input/output interface, and data transfer between the channel device and the plurality of input/output control devices is performed using one or more data bus lines. In the data processing device, the input/output control device includes a bus width expansion display means for using a plurality of bus lines, and a means for canceling the display of the bus width expansion display means. Furthermore, the data processing device is characterized in that the channel device includes means for recognizing the bus width expansion display and means for recognizing that the bus width expansion display has been withdrawn.