JP2702832B2 - Relief controller for low priority adapter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control method for an information processing system, and more particularly to a method for relieving a low priority adapter module connected to a bus.

[0002]

2. Description of the Related Art An adapter module (hereinafter, simply referred to as "adapter") acquires a right to use a bus prior to performing data transfer with a processor module (hereinafter, simply referred to as "processor"). On the same bus,
When a plurality of adapters or processors (hereinafter, referred to as "units") are connected, a fixed priority is determined for each unit, and the right to use the bus is acquired in order from the unit having the highest priority.

FIG. 8 is a timing chart when the data transfer request of the adapter is accepted by the processor, and FIG. 9 is a timing chart when it is not accepted. After acquiring the right to use the bus, the adapter sends a bus command for a data transfer request. The processor responds depending on the internal state at that time whether or not to accept the received data transfer request. 8 and 9, information on the data bus and the tag bus is transmitted from the adapter to the processor, and information on the response bus and the response valid signal is transmitted from the processor to the adapter. The tag bus indicates the validity of the data bus information, and the response valid signal indicates the validity of the response bus information.

In FIG. 8, an adapter is a tag bus “#”.
0 "is turned on to send a data transfer request bus command to the data bus, and the tag bus"# 1 "is turned on to send a series of information on the data transfer request to the data bus. The valid signal is turned on, and "ACK", which is information indicating that the data transfer request has been normally received, is transmitted to the response bus.

In FIG. 9, the processor returns a busy response to the data transfer request of the adapter. The busy response is performed when the bus control unit constituting the processor detects that the processor cannot accept the data transfer request of the adapter. Upon receiving the busy response, the adapter makes a bus use request again to retry, and acquires the bus use right. Then, the bus command of the data transfer request is transmitted to the processor again.

FIG. 10 is a timing chart showing the conventional data transfer control. In FIG. 10, three adapters P, Q, and R repeatedly make data transfer requests to the same processor. The processor has the highest fixed priority, followed by adapter P, adapter Q, and adapter R. The data transfer request of each adapter reaches the bus control unit of the processor, and when the data transfer request is accepted, transfer data related to the data transfer request is transmitted and received between the bus control unit and the memory.

Since the right to use the bus is given according to the fixed priority of the unit, data transfer requests belonging to the same arbitration group arrive at the processor in order from the one transmitted by the adapter with the higher priority. The bus control unit checks the availability of the buffer area each time a data transfer request is received, and returns a busy response when there is no availability.
FIG. 10 shows a case where there is one buffer area.
When data is being transferred inside the processor, there is no free space in the buffer area. From FIG. 10, it can be seen that the data transfer request of the adapter R having a lower fixed priority is not accepted due to the data transfer request of the adapter P and the adapter Q.

[0008]

Conventionally, there is no means for avoiding a situation in which a low-priority adapter continuously receives a busy response because such a situation itself is special and unsatisfactory. For example, there is a method of extending the timer value of the adapter and waiting for the processing of the high-priority adapter to end. However, this method has a disadvantage that the processing execution time of the low-priority adapter becomes extremely long. . There is another method in which retry is performed by software after a time-out has occurred once. However, this method has a disadvantage that performance is degraded because the software performs extra processing.

In view of such a conventional problem, the present invention (A) changes the priority of each unit on the bus when a plurality of adapters simultaneously make data transfer requests to the same processor. (B) without changing the bus arbitration method, (c) without adding new signal lines to the bus, and (d) without adding new bus commands. ) By controlling only the hardware, (f) preventing a low-priority adapter from always receiving only a busy response as much as possible without causing adverse effects such as performance degradation in an operating condition where no busy occurs, ) It aims at minimizing the software overhead due to the busy timeout report of the adapter.

[0010]

According to the present invention, the above objects are achieved by the means as set forth in the appended claims.

That is, according to the first aspect of the present invention, at least one processor module and a plurality of adapter modules are connected to a general-purpose bus having a bus handler with a fixed priority determined for each module. When a bus use request is issued from a plurality of modules at the same time, a bus use right is given in order from a module having a higher fixed priority, and the processor module includes a CPU, a memory, and at least one buffer area. And a bus control unit comprising:
When a data transfer request is received from the adapter module while all buffer areas are in use, a busy response is performed,
When the adapter module receives a busy response to the data transfer request, the adapter module issues a data transfer request again when the adapter module receives the busy response to the data transfer request. A means for issuing a reserve request to a processor module that has returned a busy response when the condition has continued for a certain period of time is provided, and a reserve request is issued to the processor module when all buffer areas are in use. This is a rescue control device for a low-priority adapter, which is provided with a means for reserving a used empty buffer area for the adapter module when there is an adapter module.

[0012] The invention according to claim 2 is characterized in that when a data transfer request is not accepted for a fixed time or a fixed number of times, a busy transfer request is made.
In the adapter module configured to detect timeout and terminate retransmission of the data transfer request, the constant condition for issuing a reserve request is shorter than the predetermined time before the busy timeout detection or shorter than the predetermined number of times. In addition to providing a means for setting the number of times, when a data transfer request is
2. The rescue controller for a low priority adapter according to claim 1, further comprising means for stopping issuance of a reserve request when a timeout is detected.

According to a third aspect of the present invention, there is provided a low-priority adapter according to the first or second aspect, further comprising means for including information indicating a reserve request in a bus command of a data transfer request sent from the adapter module to the processor module. Rescue control device.

According to a fourth aspect of the present invention, in the processor module, a register for holding information for identifying an adapter module which issues a reserve request, the contents of the register, and an adapter module which issues a data transfer request are defined. Means for comparing, when the processor module reserves a buffer area, when the reserved buffer area is empty, when a data transfer request is received from the adapter module that made the reserve request, or even after a certain time has elapsed 4. The rescue controller for a low-priority adapter according to claim 1, further comprising means for canceling a buffer area reservation previously made when there is no data transfer request from said adapter module.

According to a fifth aspect of the present invention, when a data transfer request is received from another adapter module after a reserve request is received from a certain adapter module and a buffer area is reserved, there is an empty buffer area other than the reserved buffer area. 5. The rescue controller for a low-priority adapter according to claim 1, further comprising means for receiving a data transfer request from said another adapter module.

According to a sixth aspect of the present invention, in the processor module, after the reservation request is received from the first adapter module and the buffer area is reserved, and before the reservation is released, the reservation request is issued from the second adapter module. 6. The rescue control device for a low priority adapter according to claim 1, further comprising means for returning a busy response to said second adapter module without reserving a buffer area when said second adapter module is received.

[0017]

FIG. 1 is a schematic block diagram of the system. In FIG. 1, a plurality of processors 101 and 102 and a plurality of adapter modules 103 to 105 are connected on the same bus. The bus handler 106 performs arbitration in response to a bus use request from each unit on the bus, and permits use of the bus according to the fixed priority of each unit.

FIG. 2 is a timing chart for explaining arbitration. In the figure, unit 0-RE
Q to unit 4-REQ indicate a bus use request signal transmitted by each unit on the bus. Unit 0-RQIN to unit 4-RQIN indicate a period during which the bus handler holds the fetched bus use request. The bus handler holds the bus use request until the bus use ends. Unit 0-SEQ to Unit 4-SEQ indicate a period during which each unit has acquired the right to use the bus and is using the bus.

The bus handler stores the fetched bus use request in an internal FF circuit. After using the bus, the memory is released. Alphabetic marks Ta, Tb, and Tc in FIG. 2 indicate timings at which the bus handler fetches a bus use request. The bus handler takes in the bus use request when there is no unit operating on the bus, or when there is only one FF circuit that stores the bus use request, This is when the use of the bus ends.

The plurality of bus use requests received at the same time are as follows:
Processing is performed according to the fixed priority of the unit. In the case of FIG. 2, the order is “unit 0”, “unit 1”, “unit 2”, “unit 3”, and “unit 4” in descending order of priority. The three bus use requests fetched at the timing indicated by the letter Tb and the three bus use requests fetched at the timing indicated by the letter Tc are sequentially processed in accordance with the fixed priority. Hereinafter, the operation of the present invention will be described in detail based on examples.

[0021]

FIG. 3 shows a detailed format of a command actually put on the data bus. The 0th, 8th, and 16th bits indicate the type of command, and in this case, indicate a data transfer request. The first to seventh bits contain the number of the unit issuing the command, and the ninth to fifteenth bits contain the number of the unit to which the command should be sent. The receiving unit recognizes that the command is addressed to itself by looking at this number. The 18th bit is a read / write instruction bit, which indicates the data transfer direction. The 21st bit is a protection instruction bit, which instructs whether or not to perform writing when the area of the memory instructed to be transferred is protected by software. The parameters of the 22nd and 23rd bits are used by the adapter to identify the type of data transfer and the like, and the processor sends the received value as it is at the time of status transfer. Bits 24 to 31 indicate the number of bytes of data to be transferred.

In this embodiment, the reservation request is indicated using the 22nd bit and the 23rd bit. That is, when the 22nd bit is “0” and the 23rd bit is “1”, or when the 22nd bit is “1” and
When the number bit is “0”, it is assumed that a reserve request is indicated. Since DMA transfer can be performed by hardware control or firmware control depending on the adapter, the distinction is also indicated by the 22nd and 23rd bits.

FIG. 4 is a diagram showing an example of a circuit configuration added to the adapter. The timer 401 is for detecting an existing busy timeout, and is started when the adapter sends a data transfer request. When detecting a busy timeout, the timer 401 turns on the signal B. Register 40
Reference numeral 6 denotes an existing FF circuit that holds the contents of the 23rd bit of the bus command. Two AND circuits 402 and 403
, An OR circuit 404, a register 405, and an EOR circuit 407 are circuits that are newly added in this embodiment.

The signal A output from the timer 401 is turned on before the signal B is turned on. After the data transfer request is transmitted, if the signal A is turned on and the data transfer request is still not accepted, the output of the AND circuit 402 is turned on and the register is a FF circuit having set and reset terminals. 405 is set. When the register 405 changes to the set state, the adapter transitions to the help mode. And then timer 40
When the data transfer request is not accepted even if the signal b output by 1 turns on, the busy timeout occurs and the output of the AND circuit 403 turns on. Then, the output of the OR circuit 404 is also turned on.
Is reset. Here, the help mode of the adapter is released. The help mode of the adapter is also released when the bus command of the data transfer request is normally received.

When the adapter is in the help mode, one input of the EOR circuit 407 is turned on.
The output of 7 is obtained by inverting the other input of the EOR circuit 407. EO when adapter is not in help mode
Since one input of the R circuit 407 is turned off, the output of the EOR circuit 407 becomes equal to the other input of the EOR circuit 407. Therefore, only in the help mode, the 23rd bit of the bus command is inverted.

FIG. 5 is a block diagram of a buffer control circuit of the bus control unit. Buffer 50 composed of RAM
1 has four regions H, I, J and K. The DMA control circuit 502 on the system bus side performs DMA with the adapter.
The DMA control circuit 506 on the internal bus side controls the transfer.
Controls DMA transfer with memory. The pointer 503 is
It indicates to which area in the buffer 501 the transfer data is to be written when a data transfer request is received. The pointer 504 indicates from which area the status to be returned to the adapter after the data transfer processing is completed on the internal bus side is read. The pointer 507 has a DMA on the internal bus side.
This indicates which area is used when performing the transfer.

The register 505 is constituted by FF circuits corresponding to the respective areas H to K of the buffer 501, and each FF circuit is turned on while the corresponding area stores valid transfer data. The register 508 is configured by an FF circuit corresponding to each of the areas H to K of the buffer 501,
The circuit is turned on when the data transfer processing between the corresponding area and the memory is completed.

When a data transfer request comes from the adapter, D
The MA control circuit 502 looks at the register 505, and if there is an empty area in the buffer 501, writes the transfer data to the area indicated by the pointer 503, and simultaneously turns on the FF circuit of the register 505 corresponding to the value of the pointer 503. or,
The value of the pointer 503 itself is incremented to prepare for a data transfer request from another adapter. When the FF circuit of the register 505 is turned on, the DMA control circuit 506 is notified, and the DMA control circuit 506 reads data from the area indicated by the pointer 507 and performs DMA transfer on the internal bus. When the transfer operation on the internal bus side is completed, the DMA control circuit 506 stores the value in the register 50 corresponding to the value of the pointer 507 in the register 50.
The FF circuit 8 is turned on, and at the same time, the value of the pointer 507 is incremented. When the FF circuit of the register 508 is turned on, the DMA control circuit 502 is notified, and the DMA control circuit 502 reads the transfer data from the area indicated by the pointer 504 and performs status transfer to the adapter which has requested.

Here, each of the pointers 503, 504, 507
Has the same value in the initial state, and is incremented each time a data transfer request is received from the adapter.
The value is “00” → “01” → “10” → “11” →
It changes like “00”. In FIG. 5, a so-called first-in / first-out control is performed.

FIG. 6 is a diagram showing an example of a circuit configuration added to a processor. In FIG. 6, when the processor receives a reserve request and reserves a buffer area, the processor is configured to transition to a reserve mode. The time when the processor enters the reserve mode is when the register 604, which is an FF circuit having set and reset terminals, is set, and when the output of the AND circuit 601 is turned on. Therefore, the transition to the reserve mode is when the register 604 is in the reset state, the data transfer request is received, the reservation request is displayed in the data transfer request, and there is no free space in the buffer.

Conversely, when the reserve mode is released, the timer 605 counts a certain period of time during which no data transfer request is received from the adapter which has previously made the reserve request, and turns on one input of the OR circuit 603. Or, there is a data transfer request again from the adapter which made the reserve request earlier, and the buffer area reserved at that time was vacant, and the AND of the AND circuit 602 was established. When an adapter issues a reserve request, the processor holds the adapter number in a register 606. The comparator 607 compares the contents of the register 606 with the number of the adapter that subsequently makes a data transfer request. When the comparison results match, the output of the comparator 607 turns on.

The register 610 indicating the use state of the four buffer areas H, I, J, K outputs ON indicating that the buffer area is in use or OFF indicating the empty state. Therefore, when the output of the AND circuit 609 is ON, all the buffer areas are in use. Also, an AND circuit 6
When the output of 09 is off, it means that at least one buffer area is empty. On the other hand, the AND circuit 60
8 is always off when not in the reserve mode. A
When the ND circuit 608 is off, the AND circuit 617 is always off, so that a busy response is returned when the output of the AND circuit 609 is on, that is, when all buffer areas are in use.

When the processor is in reserve mode,
The AND circuit 608 outputs ON when the output of the comparator 607 is OFF. Therefore, the AND circuit 608 is turned on when a data transfer request is received from an adapter other than the adapter that made the reserve request. When the AND circuit 608 turns on, the AND circuit 616 always turns off.
The output of the D circuit 617 becomes the output of the OR circuit 618 as it is. One input of the AND circuit 617 is connected to the AND circuit 60.
8 and the other input is the output of the OR circuit 615. When the logical product of the AND circuit 617 is established, a busy response is returned to the adapter that has requested the data transfer.

The time when the OR circuit 615 is turned on is when any of the four AND circuits 611 to 614 is turned on. The time when the AND circuit 611 is turned on is when the write pointer holds “00” indicating the buffer area H and when the buffer area I is in use. Since the buffer is used under the control of first-in / first-out, the AND circuit 61
When 1 is on, at least three buffer areas, that is, buffer areas I, J, and K are in use. Since the remaining buffer area H is already reserved, there is no free buffer area that can be used by the adapter that has newly requested data transfer at that time. For this adapter, an AND circuit 6
11, a busy response is returned by turning on the OR circuit 615, the AND circuit 617, and the OR circuit 618.

The ON of the AND circuit 612 is at least 3
One of the buffer areas, that is, the buffer areas H, J, and K, is not empty, the ON of the AND circuit 613 indicates that the buffer areas H, I, and K are not empty, and the ON of the AND circuit 614 is the buffer area H, This indicates that I and J are not empty. Also, since the write pointer points to the reserved buffer area, it is “0” in decimal.
It takes any one of values from "3" to "3". For the above reason, the OR circuit 615 is turned on when there is no free buffer area other than the reserved buffer area.

When the processor is in the reserve mode and there is a reserve request from an adapter other than the adapter which made the reserve request first, the output of the AND circuit 601 is off, so that the contents of the register 606 do not change. ,
The number of the adapter that made the reservation request first is kept as it is. Therefore, even if another adapter issues a reserve request while the processor is in the reserve mode, the reserve request is not accepted and the buffer area is not reserved for the other adapter.

FIG. 7 is a timing chart showing the data transfer control according to the present invention. FIG. 7 assumes a case where the processor has one buffer area as in the case of FIG. Adapters A, B,
C is configured to transition to the help mode when receiving a busy response twice in succession. The adapter C has transitioned to the help mode when receiving a busy response to the retransmitted data transfer request. Since the bus request of the data transfer request after the retransmission of the adapter C in the help mode includes the indication of the reserve request, the processor shifts to the reserve mode by this data transfer request. At the same time, the processor reserves the only buffer area in use for internal data transfer.

After the processor transits to the reserve mode, a data transfer request is sent from the adapter A and the adapter B. However, the vacant buffer area is reserved for the adapter C and cannot be accepted. And a busy response is made to adapter B. Next, the data transfer request accompanied by the reserve request made by the adapter C is accepted, and here the adapter C can perform data transfer with the processor for the first time. At the same time, the reserve mode of the processor is released, and after the data transfer is completed, the help mode of the adapter is released.

[0039]

As described above, according to the present invention,
Without physical / logical changes to the bus, and under hardware-only control, the probability of a low priority adapter receiving only a busy response is extremely small. Therefore, there is an effect that both the data transfer performance by shortening the period in which the low-priority adapter performs the retry and the CPU performance by substantially eliminating the software overhead due to the busy timeout report are improved.
In addition, the present invention has an advantage that the reservation of the buffer area is performed only when necessary, so that there is no disadvantage that the performance is reduced when the operation is performed so that the buffer area does not conflict.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a system.

FIG. 2 is a timing chart illustrating arbitration.

FIG. 3 is a diagram showing a format of a bus command.

FIG. 4 is a diagram illustrating an example of a circuit configuration added to an adapter.

FIG. 5 is a block diagram of a buffer control circuit.

FIG. 6 is a diagram illustrating an example of a circuit configuration added to a processor.

FIG. 7 is a timing chart illustrating data transfer control according to the present invention.

FIG. 8 is a timing chart when a data transfer request is accepted.

FIG. 9 is a timing chart when a data transfer request is not accepted.

FIG. 10 is a timing chart showing a conventional data transfer control.

[Explanation of symbols]

101, 102 Processor module 103 to 105 Adapter module 106 Bus handler 401, 605 Timer 402, 403, 601, 602, 608, 609, 6
11 to 614, 616, 617 AND circuit 404, 603, 615, 618 OR circuit 405, 406, 505, 508, 604, 606, 6
10 Register 407 EOR circuit 501 Buffer 502, 506 DMA control circuit 503, 504, 507 Pointer 607 Comparator

Claims (6)

(57) [Claims] At least one processor module and a plurality of adapter modules are connected to a general-purpose bus having a bus handler with a fixed priority determined for each module, and the bus handler is simultaneously connected to a bus from a plurality of modules. When there is a use request, the bus use right is sequentially given from a module having a higher fixed priority, and the processor module includes a CPU, a memory, and a bus control unit including at least one buffer area. The bus control unit performs a busy response when receiving a data transfer request from the adapter module when all the buffer areas are in use, and the adapter module includes:
In an information processing system configured to make a data transfer request again when receiving a busy response to a data transfer request, the adapter module continues to receive a busy response to the retransmitted data transfer request for a certain period of time. Means for issuing a reserve request to the processor module that has returned a busy response when there is an adapter module that has issued a reserve request while all buffer areas are in use. A means for reserving a used free buffer area for the adapter module when the adapter module is used. 2. A fixed condition for issuing a reserve request in an adapter module configured to detect a busy timeout and terminate retransmission of the data transfer request when the data transfer request is not accepted for a fixed time or a fixed number of times. Means for making the time shorter than the predetermined time before the detection of the busy timeout or the number of times shorter than the predetermined number of times, and when the data transfer request is normally accepted or when the busy timeout is detected. 2. The rescue controller for a low-priority adapter according to claim 1, further comprising means for stopping issuance of the reserve request. 3. The rescue control device for a low priority adapter according to claim 1, further comprising means for including information indicating a reserve request in a bus command of a data transfer request sent from the adapter module to the processor module. 4. A processor module comprising: a register holding information for identifying an adapter module issuing a reserve request; and means for comparing the contents of the register with the adapter module issuing a data transfer request. In addition, when the processor module reserves a buffer area, when the reserved buffer area is vacant and a data transfer request is received from the adapter module that has made the reserve request, or even when a certain period of time elapses, the data is transmitted from the adapter module. 4. The rescue controller for a low-priority adapter according to claim 1, further comprising means for canceling the buffer area reservation previously made when there is no transfer request. 5. When a data transfer request is received from another adapter module after receiving a reserve request from a certain adapter module and then reserving a buffer area, when there is a free buffer area other than the reserved buffer area, said another adapter is used. 5. The rescue controller for a low-priority adapter according to claim 1, further comprising means for receiving a module data transfer request. 6. In a processor module, after receiving a reserve request from a first adapter module and reserving a buffer area and before receiving a reservation request from the second adapter module before the reservation is released. 6. The rescue control device for a low priority adapter according to claim 1, further comprising means for returning a busy response to the second adapter module without reserving a buffer area.