KR100225531B1 - Apparatus for interfacing between peripheral processor and device in the switching system - Google Patents

Abstract

The present invention relates to a matching device for matching between a low-level processor and a device using an efficient bus method in an exchanger, wherein the matching device accommodates at least one hardware device per one subprocessor having a central processing unit. A switch configured to be capable of performing, comprising: a D-bus configured to transmit information between a hardware device and a lower processor, comprising 7 transmission lines including two data transmission lines DATA 0 and DATA 1; The subprocessor is configured to include a matching unit for matching processing between the subprocessor and the hardware device through the D bus.

Description

Matching device between lower level processor and device in exchange

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matching device between a lower level processor (also referred to as a PP) and a device in an exchange, and more particularly to a matching device for performing matching processing between a lower level processor and a device using an efficient bus method. .

The lower level processor used in the exchange is located between the upper level processor provided in the exchange and the end device (also called a telephony device) to control the device. It is configured to transmit and receive signals to and from the device in a matching structure using.

That is, as shown in FIG. 1, the existing exchanger connects a TD-BUS consisting of 12 signal lines between the lower-level processor board 100 and the device 120, and transmits a signal to the device 120 through the TD-BUS. In order to transmit and receive, the lower level processor board 100 includes a matching unit 102 controlled by the CPU 101 and the CPU 101 to perform matching processing with the TD-BUS.

However, since the TD-BUS used between the lower level processor 100 and the device 120 uses the system clock SCLK as a transmission / reception clock, as shown in FIG. The transmission distance was limited, and since there were 12 signal players of TD-BUS, there were many problems of functional limitations such as being able to accommodate up to four devices 120 per one low-level processor 100. .

Accordingly, an object of the present invention is to provide a matching device for matching between a lower level processor and a device using an efficient bus method in an exchange.

Another object of the present invention is to provide a matching device that can alleviate the limitation of the transmission distance between the lower-level processor and the device by matching the lower-level processor and the device by a bus method that separates the transmission and reception clocks.

It is still another object of the present invention to provide a matching device between a lower level processor and a device to expand the number of channels per lower level processor by matching the lower level processor and the device with a bus method that reduces the number of use signals.

In order to achieve the above objects, a matching device between a lower level processor and a device according to the present invention comprises: a data exchange line configured to accommodate at least one or more hardware devices per one subprocessor having a central processing unit; A D bus including seven transmission lines including (DATA 0, DATA 1) for transmitting information between the hardware device and the lower processor; It is characterized in that it comprises a matching unit provided in the lower processor for matching processing between the lower processor and the hardware device through the D bus.

1 is a block diagram showing a matching relationship between a lower level processor and a device provided in an existing exchange;

2 is a functional block diagram of an exchange having a matching device between a lower level processor and a device according to the present invention;

3A and 3B are data format diagrams transmitted through a data transmission line according to the present invention;

4 is a detailed block diagram of a matching unit shown in FIG. 2 implemented according to the present invention;

5A through 5F are structural diagrams of respective registers provided in the register shown in FIG. 4;

6 is a timing diagram when a subprocessor writes a device in bytes according to the present invention;

7 is a timing diagram when a lower processor writes a device in word units according to the present invention;

8 is a timing diagram when a subprocessor reads a device in bytes according to the present invention;

9 is a timing diagram when a lower processor reads a device in word units according to the present invention;

10 is an operation flowchart of the interrupt handler shown in FIG. 4;

Explanation of symbols for main parts of the drawings

200: subprocessor 201: central processing unit (CPU)

202: matching unit 210: D (Device) bus

220: device 401: clock provider

402: address decoder 403: buffer for address transmission

404: Register 405: Data transfer buffer

406: bottle / serial converter 407: first control unit

408: serial / parallel converter 409: second control unit

410: Receive data dedicated buffer 411: Bus control unit

412: interrupt handler

The above and other objects and various advantages of the present invention will become apparent from the following description of the preferred embodiment.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a functional block diagram of an exchange having a matching device between a lower level processor and a device according to the present invention, and includes a lower level processor 200 and a device 220 matched by a D (Decive) bus. In particular, the lower level processor 200 includes a matching unit 202 configured to mate with the D bus and a central processing unit 201 (hereinafter, referred to as CPU) for controlling the matching unit 202.

As shown in FIG. 2, the D bus 210 may include a TXCLK signal line, a RXCLK signal line, an Assert signal line, two Data signal lines, and a lower level processor 200. 7 signal lines such as a D bus select signal line BUSSEL transmitted to the device 220 and an interrupt signal line IRQ transmitted from the device 220 to the lower level processor 200. In particular, the format of the data transmitted through the two data signal lines is configured as shown in FIG. That is, FIG. 3A is a format diagram of data transmitted from the lower level processor 200 (or PP) to the device 220, and includes a mode information area, an address information address, and two data data. 3B is a format diagram of data transmitted from the device 220 to the lower level processor 200, and only two data information areas exist.

FIG. 4 is a detailed block diagram of the matching unit 202 shown in FIG. 2. The transmission clock signal required for signal transmission from the lower processor 200 to the device 220 using the transmission clock signal TXCLK as an input signal is shown in FIG. A clock providing unit 401 for generating and providing, an address decoder 402 for decoding an address transmitted from the CPU 201, and an address transmission buffer 403 for transmitting an address output from the address decoder 402. For data transmission for transmitting data transmitted from the CPU 201 to the device 220 side or transmitting data transmitted from the device 220 side to the CPU 201 through a 16-bit data bus of D0 to D15. A register is designated by the buffer 405 and the address transmitted from the address decoder 402 to store various state data transmitted from the CPU 201 through the data transfer buffer 305. Information transmitted from the address transfer buffer 403, the register 404 and the data transfer buffer 405 in serial form in synchronization with the clock signal provided from the data generator 404 and the clock provider 401, Parallel / serial converter 406 transmitted through the bus 210 to the device 220 by a clock signal output from the clock providing unit 401 and a control signal supplied from the register 404. Serial data transmitted from the device 220 in synchronization with the reception clock signal RXCLK provided from the device 220 through the first bus controller 407 and the D bus 210 to control the A second to control the operation of the serial / parallel converter 408 according to the serial / parallel converter 408 and the clock signal provided from the clock providing unit 401 and the control signal provided from the register 404 Data output from the controller 409 and the serial / parallel converter 408 When is applied, the reception data dedicated buffer 410 for transmitting to the CPU 201 through the above-described D0 ~ D15 data bus, the interrupt (DIRQ) transmitted from the device 220 is received and transmitted, the first control unit 407 And monitoring the assert signal according to each operation and the AST signal transmitted from the device 220 through the second control unit 409, and transmitting the bus selection signal transmitted from the register 404 to the corresponding device 220. When the DIRQ signal is transmitted from the bus control unit 411 and the bus control unit 411, an interrupt of a predetermined level is generated to the CPU 201 and the interrupt source source information is controlled according to the response signal transmitted from the CPU 201. An interrupt handler 412.

In particular, the register 404 is composed of six registers, such as a status register, a control register, an AMOD register, a BMOD register, an interrupt vector register, and an interrupt mask register, as shown in FIG. The data storage structure in each register is as shown in Figs. 5A to 5F.

A status register having a structure as shown in FIG. 5A accesses the device 220, maintains an operating state upon completion of the access, and holds the bus select signal level of the subprocessor 200. ANORMAL * (BNORMAL) mentioned in FIG. 5A is information indicating that D bus 210 operation is normally performed, and AERR * (BERR *) is information of an AST signal made by the bus controller 411 during operation of the D bus 210. Error check result information, ABSEL I (BBSEL I) is the bus selection signal level information of the lower processor 200, WRASTUP is information on the write operation period of the D bus 210, RDASTUP is the D bus 210 Information on the read operation period of.

In the control register having the structure as shown in FIG. 5B, AEARLY * (BEARLY *) is information on a D bus 210 access method, VECTOR * is interrupt scheme information, and ABSEL0 (BBSEL0) is a subprocessor ( 200) It is the bus selection information printed by itself. As shown in FIGS. 5C and 5D, the AMOD and BMOD registers having a structure using 5 bits (AM5 to AM0 and BM5 to BM0) currently have a byte 8 mode of operation between the subprocessor 200 and the device 220. Bit) operation mode, word (16 bit) operation mode, double word (32 bit) operation mode, read operation mode or write operation mode information is stored. An interrupt vector register having a structure as shown in FIG. 5E assigns V7 to V3 as a user write area, and assigns V2 to V0 to an interrupt cause information area currently generated. In addition, an interrupt mask register having a structure as shown in FIG. 5F has interrupt enable and disable state information. As described above, the matching device according to the present invention including the D bus 210 including seven signal lines and the matching unit 202 configured as shown in FIG. 4 operates as follows.

First, when the lower processor 200 writes to the device 220, the CPU 201 transmits information for setting an address, an operation size, and an operation mode for designating a MOD register through the address buses A0 to A17. . The transmitted information is decoded by the address decoder 402 and stored in the MOD register in the register 404. By the value stored in the MOD register, the lower processor 200 controls whether the transmission unit is set to 8 bits, 16 bits, or 32 bits in the write mode operation and the write mode operation of the device 220.

In this way, after the size information and operation mode information to be operated in the MOD register are stored, the CPU 201 selects the D bus port, and then asserts at the rising edge of the transmission clock signal TXCLK. As shown, the mode value, address, and data are transmitted to the device 220. At this time, the mode value transmitted to the device 220 is transmitted from the mode register in the register 404, the address is transmitted from the address transfer buffer 403, and the data is transferred from the data transfer buffer 405. Each mode value, address, and data transmitted are applied to the parallel / serial converter 406.

The parallel / serial converter 406 is controlled by the first control unit 407 and converts the mode values, addresses, and data applied in parallel to the serial form as shown in FIG. 3A and outputs them. Data 0 and data 1 in FIG. 3A represent data transmission lines provided on the D bus 210. Accordingly, the parallel / serial converter 406 transmits the mode value, the address, and the data information to the device 220 through the transmission clock signal TXCLK and the data 0 and the data 1 provided by the clock provider 401.

For example, when transmitting by byte unit, information is transmitted in the same cycle as the timing diagram shown in FIG. That is, the assert signal AST that falls low from the rising edge of the transmission clock signal TXCLK is transmitted at the rising edge of the 15th transmission clock signal TXCLK from the rising edge of the next transmission clock signal TXCLK. The active period is controlled to transition to the high state. During the period in which the assert signal remains active, the mode value, address, and data are parallel / serial in synchronization with the polling edge of the transmit clock signal TXCLK as shown in FIG. 6 (see DATA 0 and DATA 1). From converter 406 to device 220, the last data value is sent at the 15th polling edge of the transmit clock signal.

In the case of word-to-word transmission, information is transmitted in the same cycle as the timing diagram shown in FIG. That is, during the transmission in word units, the active signal period of the assert signal is switched to the low state, and is maintained from the next rising edge of the transmission clock to the 19th rising edge, and is converted to the high state at the 19th rising edge. During this assert period, as shown in Fig. 7, mode values, addresses and data are transmitted from the parallel / serial converter 406 to the device 220 in synchronization with the polling edge of the transmission clock signal, At the first polling edge, the last data value is transmitted.

As described above, the first control unit 407 controls the parallel / serial converter 406 to be driven. When the current operation mode information is provided from the register 404, the first control unit 407 is synchronized with the transmission clock signal TXCLK to synchronize the parallel / serial converter. The period of the assert signal provided to 406 is controlled.

On the other hand, when the subprocessor 200 tries to read the device 220, the command and address to be read are the same as the above-described write address, the address decoder 402, the address transfer buffer 403 and the parallel / serial converter 406. Is transmitted to the device 220 via. Data read from the device 220 by the transmitted information is applied to the serial / parallel converter 408. The serial / parallel converter 408 receives data transmitted in the structure shown in FIG. 3B through the data 0 and data 1 transmission lines in synchronization with the reception clock signal RXCLK transmitted from the device 220. The second control unit 409 transmits the data received in byte, word, or double word units to the reception data dedicated buffer 410.

For example, when reading in byte unit, the active signal period of the assert signal is kept low from the rising edge of the transmission clock signal and then goes high at the rising edge of the 11th transmission clock signal from the next rising edge. The address is transmitted to the device 220 in synchronization with the polling edge of the transmit clock, and the last address value is transmitted to the device 220 at the 11th polling edge of the transmit clock. Accordingly, the assert signal is turned low at the 13th rising edge of the transmission clock signal as shown in FIG. 8 to receive the data read from the device 220, and then is turned high at the 17th rising edge. During this period, the serial / parallel converter 408 receives data transmitted through the data 0 and data 1 transmission paths in synchronization with the polling edge of the reception clock signal RXCLK transmitted from the device 220. When reading in word units, it is as shown in FIG.

The second control unit 409 controls the period of the assert signal of the serial / parallel converter 408 according to the mode information provided from the register 404 in synchronization with the transmission clock signal as in the first control unit 407 described above. .

The reception data dedicated buffer 410 transmits the parallel data transmitted from the serial / parallel converter 408 to the CPU 201 through the D0 to D15 data buses.

The bus controller 411 monitors the assert signals controlled by the first and second controllers 407 and 409 and transmits an error occurrence to the status register inside the register 404 so that the CPU 201 can recognize it. When the interrupt DIRQ is generated from the predetermined device 220, it is transmitted to the interrupt handler 412.

The interrupt handler 412 is driven as shown in the flowchart shown in FIG. That is, in the tenth step, the interrupt handler 412 checks whether the interrupt request signal is received from the bus controller 411. As a result of the check, if it is received, the process goes to the eleventh step to refer to the interrupt mask register in the register 404. As a result of the reference, if the interrupt for the device is enabled (or open), the process proceeds to the thirteenth step via the twelfth step. However, if the interrupt for the corresponding device is in the disabled state, the process proceeds to step 19 and the operation for disregarding the interrupt transmitted from the interrupt bus controller 411 is terminated and the operation is terminated.

In the thirteenth step, the interrupt handler 412 transmits an interrupt having the corresponding interrupt level to the CPU 201. At this time, the interrupt level can be set in advance among the desired levels. This has the advantage of increasing interrupt priority over conventional matching devices. (Previous matching devices are designed to use only interrupt levels 3 and 2).

After the interrupt is generated by the CPU 201, the interrupt handler 412 checks whether a response signal ACK is received. As a result of the check, if a response signal is received, the process proceeds from step 14 to step 15 to check whether the response signal received from the CPU 201 requires an auto vectored process. As a result of the check, when the automatic vector method processing is requested, the interrupt handler 412 proceeds to step 16 to perform control of reading out the interrupt source information stored in the interrupt vector register in the register 404 and ending the operation. .

The interrupt source information read by the interrupt handler 412 is transmitted to the CPU 201 through the data transfer buffer 405 so that the CPU 201 can recognize the interrupt source source.

However, when the checking result of the fifteenth step is not required for the automatic vector method processing from the CPU 201, the process proceeds to the seventeenth step to detect the level of the response signal transmitted from the CPU 201. As a result of the detection, it is checked whether the level of the response signal is the same as the interrupt level generated from the interrupt handler 412 to the CPU 201. If the result of the check is the same, the process proceeds to the sixteenth step through the eighteenth step to perform read control on the interrupt vector register in the register 404 and to provide the interrupt source source as described above.

As a result of the check in the eighteenth step, if the interrupt request signal levels are not the same, the process goes to the nineteenth step, and the interrupt handler 412 ignores the processing for the corresponding interrupt and ends the operation.

As described above, the present invention enables the matching process between the subprocessor and the device by using the D bus structure composed of seven signal lines, thereby reducing the transmission distance restriction between the subprocessor and the device, and reducing the number of signal lines. By reducing the number from seven to seven, the number of channels per hard processor board can be approximately doubled, and the number of serial data signals to two (data 0 and data 1) can significantly reduce bus run time. In addition, it is possible to increase the reliability and stability of the data by monitoring the assert signal and to set the interrupt priority higher by varying the interrupt level from 1 to 7.

Although the present invention has been described as the above-described embodiment, those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

An exchange configured to accommodate at least one hardware device per subprocessor with a central processor, A D bus comprising seven transmission lines including two data transmission lines DATA 0 and DATA 1 for transmitting information between the hardware device and the subprocessor; And a matching unit provided in the subprocessor for matching processing between the subprocessor and the hardware device through the D bus. The method of claim 1, wherein the matching unit, An address decoder for decoding an address transmitted from the central processing unit; A register that stores all information about an operation mode between the subprocessor and a hardware device; A data transmission buffer for transmitting and receiving data to and from the central processing unit through a data bus of a predetermined bit; A bottle that converts the address transmitted from the address decoder, the mode information transmitted from the register, and the data transmitted in parallel from the data transmission buffer in serial form through the two data transmission lines in synchronization with the transmission clock signal. / Serial converter; A first control unit for controlling a data transmission operation of the parallel / serial converter in synchronization with the transmission clock signal according to the mode information transmitted from the register; When the lower processor wants to read predetermined data of the hardware device, data transmitted from the hardware device through the two data transmission lines is received in synchronization with a reception clock signal provided from the hardware device through the D bus. A serial / parallel converter for converting and outputting the received information into a parallel form; A second control unit for controlling a data transmission operation of the serial / parallel converter in synchronization with the transmission clock signal according to the mode information provided from the register; A reception data dedicated buffer for receiving the reception data output from the serial / parallel converter and transmitting the received data to the central processing unit through the data bus; A bus controller which transmits a bus selection signal transmitted from the register to a corresponding hardware device through the D bus; And And an interrupt handler configured to process an interrupt by referring to interrupt-related data stored in the register when an interrupt signal generated from a hardware device is received through the D bus and the bus controller. Device-to-device matching device. The interrupt handler of claim 2, wherein when the interrupt handler receives a predetermined interrupt signal from the bus controller, the interrupt handler generates a predetermined level of interrupt to the central processor when the interrupt mode for the corresponding device is open. If the response signal requires automatic vector processing, read control is performed on the interrupt vector register stored in the register to be transmitted to the central processing unit. If the response signal does not require automatic vector processing, the response A matching device between the subprocessor and the device, characterized in that it is driven to check the signal level and perform interrupt processing. 2. The D bus of claim 1, wherein the D bus is configured by separate transmission / reception clock signal transmission lines TXCLK and RXCLK, an assert signal line, an interrupt transmission line IRQ, and a bus selection signal line BUSSEL in addition to the data transmission line. Matching device between the subprocessor and the device. The method of claim 4, wherein the matching unit, An address decoder for decoding an address transmitted from the central processing unit; A register that stores all information about an operation mode between the subprocessor and a hardware device; A data transmission buffer for transmitting and receiving data to and from the central processing unit through a data bus of a predetermined bit; A bottle that converts the address transmitted from the address decoder, the mode information transmitted from the register, and the data transmitted in parallel from the data transmission buffer in serial form through the two data transmission lines in synchronization with the transmission clock signal. / Serial converter; A first control unit for controlling a data transmission operation of the parallel / serial converter in synchronization with the transmission clock signal according to the mode information transmitted from the register; When the lower processor wants to read predetermined data of the hardware device, data transmitted from the hardware device through the two data transmission lines is received in synchronization with a reception clock signal provided from the hardware device through the D bus. A serial / parallel converter for converting and outputting the received information into a parallel form; A second control unit for controlling a data transmission operation of the serial / parallel converter in synchronization with the transmission clock signal according to the mode information provided from the register; A reception data dedicated buffer for receiving the reception data output from the serial / parallel converter and transmitting the received data to the central processing unit through the data bus; A bus control unit for transmitting a bus selection signal transmitted from the register to a corresponding hardware device through the bus selection signal line BUSSEL; And And an interrupt handler configured to process an interrupt by referring to interrupt-related data stored in the register when an interrupt signal generated from a hardware device is received through the interrupt transmission line and the bus controller. Device-to-device matching device. The method according to claim 2 or 5, The bus controller monitors period control of an assert signal made by mode information provided from the register to control transmission operations of the parallel / serial converter and the serial / parallel converter in the first control unit and the second control unit. And a function of checking whether or not the transfer state is normal between the subprocessor and the hardware device and storing the result in the register. The address matching unit of claim 6, wherein the matching unit further comprises an address transfer buffer for transmitting only 16 bits (A0 to A15) of the addresses output from the address decoder to the parallel / serial converter. Matching device between the subprocessor and the device.

Images