JPS63247859A - Shared memory device - Google Patents

Abstract

PURPOSE:To improve the processing speed of a shared memory device by performing a writing process to a store buffer against a common bus of a shared memory when a write request is produced and also to a shared memory part against a CPU to report the end of the writing process and securing the coincidence of information on the contents of all shared memory part. CONSTITUTION:The relevant address and data are set at store buffers 110 and 111 when a write request is given to a shared memory part 1a from a CPU 5a. Then the bus acquisition start is applied to a bus acquisition control circuit 13 and at the same time an instruction is given to a memory control circuit 16 to perform a write process to a memory device 14. Receiving a write end signal, the CPU 5a carries out the next process. While the part 1a acquires a common bus 6 of a shared memory to deliver the information stored in both buffers 110 and 111 and sends write signals to all parts 1a to write the relevant data to the device 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a shared memory device, and particularly to a shared memory device suitable for use in an autonomous distributed information processing device system.

[Conventional technology]

FIG. 3 shows the configuration of a conventional shared memory device.

The shared memory unit (GM) 1 includes four information processing devices (CPUs).
) 5a, 5b, and 5c. This access is to q, the CPU internal bus 4a.

4b, 4c, 4d, GM interface (GM
I/F) 2a, 2b, 2c, and 2d.

Another conventional example (Japanese Unexamined Patent Publication No. 57-189257) is shown in FIG. The shared memory section includes four memory sections 1a.

The memory units 1a, lb, lc, and ld are installed in a distributed manner, and the four memory units 1a, lb, lc, and ld have the same contents. Gates (buffers) 3a, 3b, 3c, and 3d are provided as means for making the contents the same.
5 When writing data from a to GMla, write data to GMla via gate 3a, and write data to other GMlb, l
The data is also written to c and ld via the bus 6 at the same time.

[Problem that the invention seeks to solve]

An autonomous distributed system is sometimes adopted in a system consisting of multiple information processing devices and shared memory. An automatic distributed system is a system that communicates directly or indirectly (via memory) between information processing devices, in which each processing device maintains its own certain state even if a processing device other than itself fails. The system has the ability to continue its work without being affected by other processing devices.

Consider the case where such an autonomous decentralized system is applied to the conventional example shown in FIG. When trying to achieve autonomous decentralization with each CPU, CPUs 5 a , 5 b , 5 c , 5
d, even if any one CPU stops, the other three CPUs can operate normally, but if shared memory section 1 stops, each CPU will be unable to exchange data at all, and normal operation will not be possible. The drawback was that the operating range was limited.

In the conventional technology shown in Fig. 4, no matter which part stops, the remaining C
It becomes possible to exchange data between PUs, and the above problem can be solved. However, no consideration was given to the data processing speed, and the corresponding shared memory units 1a, lb, l
Reading from c and ld to the CPUs 5a, 5b, 5c, and 5d can be done directly without using the shared memory common bus 6, so the processing speed is fast, but when writing,
If write requests overlap from multiple CPUs, for example 1a and 1b, and CPU 1a has a higher priority, CPU 1a acquires the shared memory bus 6, and C:PUlb is forced to wait until the writing is completed, and processing is delayed. The downside was that it was slow.

SUMMARY OF THE INVENTION An object of the present invention is to provide a shared memory device with faster processing times for reading and writing from a shared memory.

[Means for solving problems]

In the present invention, a store buffer is provided for use when writing to a shared memory section, and in response to a write from a CPU, data is written to the store buffer for the shared memory common bus and simultaneously stored in the shared memory section corresponding to the CPU. By writing , the CPU is made to report the completion of writing.

[Effect]

When writing from the CPU to the corresponding shared memory section, the end of the write is reported even if the shared memory common bus has not been acquired at the time of writing to the store buffer and the memory section. If valid data exists, the store buffer issues a bus acquisition request to the shared memory common bus and performs a write operation to all shared memory units connected to the bus.

As a result, the content information of all shared memory sections can be made consistent.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 2 shows an example of a system configured with four CPUs. Figure 1 shows the shared memory section 1 of one of them.
This is the internal details of a. Other shared memory units 1b, lc, l
d also has the same configuration.

First, the operation when writing data from the CPU 5a to the shared memory section will be described.

First, the access to the shared memory 1a adjacent to the processor 5a that has generated the request will be described. When a write request from the CPU 5a to the shared memory unit 1a occurs, the address f
li and data Q2 are respectively stored in address store buffer 110. It is set to Delus 1 to Abatsuhua 111,
A bus acquisition activation Qδ is applied to the bus acquisition control circuit 13. Also, in parallel with this operation, an instruction Q4 is given to the memory control circuit 16 to write into the memory device 14. The memory priority selection circuit 17 prioritizes the write request from the shared memory common bus 6, selects the request from the CPU 5a, reports it to the memory control circuit 16, and selects the request from the selector 150.
, 151 to select the CPU side.

Write data from the CPU 5a to the memory device 14. When the writing is completed, send a signal 1 to report the completion to the CPU 5a.
It will be held on 61st. CPU 5 received the completion report.
A assumes that the writing to the shared memory section 1a has been completed, that is, the CPU 5a assumes that there is no longer an interface with the shared memory 1a, and moves on to the next process execution.

On the other hand, the separated shared memory 5a performs the following operations independently of the CPU 5a. The activated bus acquisition control circuit 13 outputs a bus acquisition request signal to the shared memory common bus 6. The bus acquisition priority selection circuit 12 receives the bus acquisition request signal on the shared memory common bus 6 as input, performs priority selection according to an initially determined priority order selection procedure, and reports the result to the bus acquisition control circuit 13. Upon receiving the report, the bus acquisition control circuit 13 stores the address store buffer 110 .
The write signal for outputting the information stored in the data store buffer 111 and sending the write signal to all the shared memory sections la, lb, lc, and ld is sent to the memory priority selection circuit 17 in all the shared memory sections. When the shared memory common bus 6 side is selected by prioritizing the access requests from each CPU, each shared memory section reports to its own memory control circuit 16, and its own selector 150, 151 selects the shared memory common bus side and writes data on the bus to its own memory unit 14.

Note that the shared memory unit 1a adjacent to the requesting processor 5a
In this case, double writing to the same address is performed: writing via the selectors 150, 151 when starting writing from the CPU 5a, and writing via the common bus 6.

Note that double writing may be stopped. In this case, the second write via the common bus 6 may be locked. It is also possible to lock the first call and use only the second call from the common bus 6, but the CPU 5 a
Therefore, it is not practical to confirm the completion of writing to the memory 14 until the second time. In particular, you may want the data immediately after writing starts, and in this case, the first
It is desirable to complete the process on the first writing.

Next, the operation in response to a read request from the CPU 5a to the shared memory section 1a will be explained. The read request Q4 is input to the memory priority selection circuit 17, and when the read request is selected in the same way as when writing, it is reported to the memory control circuit 16, which causes the selectors 150 and 151 to select the CPU side and select the memory device. 14 to output data, and the CPU 5a
A completion report signal 161 is output to. This readout is non-destructive. In this read operation, it is not necessary to occupy the common bus 6.

When writing to the shared memory section occurs simultaneously from multiple CPUs, the next write request may be issued from the CPUs before the data in the store buffer has been transferred. In order to cope with such a case, a plurality of stages of store buffers are provided and a first-in-first-out method is used to avoid loss of write requests.

Note that the present invention can also be applied to general systems other than autonomous decentralized systems.

〔Effect of the invention〕

According to the present invention, in a shared memory device having a shared memory section shared by a plurality of CPUs, the processing time of the CPU can be shortened when writing as well as when reading, and the writing time can be reduced by all At least 3 in the method of making the CPU wait until the writing to the shared memory section is completed
According to this embodiment, processing that requires microseconds takes about 1 microsecond, which is an effect of improving the processing speed by one-third.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the invention. A detailed diagram of the inside of a shared memory device, FIG. 2 is a system configuration diagram of the present invention, FIG. 3 is a conventional system configuration diagram with one shared memory device, and FIG. 4 is a system in which the shared memory device is distributed to each CPU. FIG. 1... Shared memory section, 12... Bus acquisition priority selection circuit. 13... Bus acquisition control circuit, 14... Memory device,
16...Memory control circuit, 17...Memory priority selection circuit, 110...Address store buffer, 111.
...Data store buffer, 161...Completion report signal.

Claims (1)

[Claims] 1. Consisting of a plurality of information processing devices, a plurality of shared memory units corresponding to each processing unit, and a common bus commonly connected to the shared memory, the shared memory unit stores information. a store buffer that temporarily holds write information in response to a write request from a processing device to the shared memory unit; and at the same time, setting the write request information in the store buffer;
means for writing into a memory section corresponding to the information processing device;
When writing is performed in the store buffer and the memory section, there is a means for reporting completion of writing to the information processing device that is the source of the write request, and if valid data exists in the store buffer, the memory section means for outputting a bus acquisition request signal to a connected common bus; priority selection means for inputting a bus acquisition request signal on the common bus and acquiring a bus according to an initially determined priority order; A shared memory device comprising means for writing the same data in parallel to all of the shared memory units in response to a write request made.