JPH08137738A - Cpu arbitration circuit - Google Patents

Abstract

PURPOSE: To eliminate the excessive processings of respective CPU by immediately inputting an interruption signal to CPU on a read-side when CPU on a writing-side terminates writing into a shared memory at the time of transferring data between CPU. CONSTITUTION: Monitor circuits 6 and 7 monitor whether respective address signals A1, A2 transmitted from CPU 1 and 2 are matched with designated addresses or not. When they are matched, designated address access signals B1 and B2 are transmitted, the completion of the reading of data from the shared memory 5 by CPU 1 and 2 are detected and shared memory read completion signals C1 and C2 are transmitted. An arbitration circuit 8 transmits the interruption signals E1 and E2 of a read request to CPU 2 on the read-side in response to designated address access B1 and B2 and releases the transmission of the interruption signals E1 and E2 in response to the shared memory read completion signals C1 and C2. Thus, respective CPU 1 and 2 need only to read and write data from/into the shared memory 5, and the excessive processings become unnecessary.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbitration circuit, and more particularly to an arbitration circuit of a CPU for a shared memory used among a plurality of CPUs such as a master CPU (central processor unit) and a submaster CPU.

[0002]

2. Description of the Related Art In a control system or the like using a CPU, a structure in which a plurality of CPUs are installed side by side and processing is distributed is used for the purpose of improving the processing capacity and performance of the system. In such cases, a shared readable / writable shared memory is provided for each CPU to transfer information between the multiple CPUs, and information exchanged between the CPUs is written to and read from the shared memory to transfer information. I do.

FIG. 3 is a block diagram illustrating a conventional method in which the multiple CPUs 1 and 2 utilize the shared memory 5. In the figure, CPU1 and CPU2 are respectively
Address / control buses A1 and A2 and data bus D
1 and D2, and the shared memory 5 has an address /
The control bus A3 and the data bus D3 are connected. CPU1 and CPU2 are gate circuits 3 respectively
And via address bus A3
Also, the shared memory 5 is accessed via the data bus D3.

Data is transferred between the CPU 1 and the CPU 2 by using the shared memory 5. CPU
When transmitting information from 1 to the CPU 2, write data from the CPU 1 is written in the shared memory 5 via the gate circuit 3. The CPU 2 periodically reads the data written in the shared memory 5, and the write information from the CPU 1 is updated. Conversely, CPU2 to CPU
When transmitting information to 1, the write data from the CPU 2 is written to the shared memory 5 via the gate circuit 4, and the write data of the shared memory 5 is periodically read by the CPU 1 and written from the CPU 2. Update the data.

When the reading timing of one CPU is earlier than the writing timing of the other CPU, the data read by the CPU remains the data before being written from the other CPU, and it is necessary to prevent the update data from being missed. The CPU on the reading side needs to periodically read the data in the shared memory 5.

[0006]

As described above, in the conventional shared memory, the reading and writing cycles of the CPU1 and CPU2 are processed asynchronously. There is a problem in that it is necessary to periodically read the data in the shared memory 5 regardless of whether or not the data has been written, regardless of whether the data has been updated, and extra processing time is often wasted.

[0007]

The circuit of the present invention is provided so that it can be accessed by a plurality of CPUs, and at least one address is designated to indicate the end of data writing from one CPU. Memory and the CP
It monitors whether each address signal sent from U matches the designated address, sends a designated address access signal when they match, and detects that each CPU has completed reading data from the shared memory. A plurality of monitoring circuits for transmitting a shared memory read completion signal, a read request interrupt signal to the read side CPU in response to the designated address access signal, and a shared memory read complete signal in response to the shared memory read completion signal. One arbitration circuit for canceling the transmission of the interrupt signal.

[0008]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Reference numerals 1 and 2 are CPUs, 3 and 4 are gate circuits, 5 is a shared memory, 6 and 7 are address monitoring circuits, and 8 is a reference numeral. Each arbitration circuit is shown. In the figure, the shared memory 5 is divided into two address spaces as viewed from the CPU 1 or the CPU 2. That is, as illustrated in FIG. 2, the shared memory 5 is written by the CPU 1
2 is divided into an address space A in which 2 reads and an address space B in which the CPU 2 writes and reads from the CPU 1. The address monitoring circuits 6 and 7 monitor the situation where the CPU 1 and the CPU 2 are accessing the shared memory 5, respectively, while receiving the address / control signals of the address / control buses A1 and A2. CPU1 (or CPU2) is shared memory 5
Of the address space A (B) is continuously or intermittently written, and immediately after writing all the data, the address a (b) specified in advance in the address space A is accessed. After that, the data write access is completed. Address monitoring circuit 6
In (7), when the designated address a (b) is received, the designated address access signal B1 (B2) is sent to the arbitration circuit 8.
Send to. The arbitration circuit 8 is the address monitoring circuit 6 (7).
When the designated address access signal B1 (B2) is input from the CPU 1, it is considered that the writing side CPU 1 (2) has opened the address / control bus A3, and the interrupt signal E2
(E1) is sent to CPU2 (1). CPU2
When detecting the interrupt signal E2 (E1), (1) reads the shared memory 5. Address monitoring circuit 7
(6) detects the read state and sends the shared memory read completion signal C2 (C1) to the arbitration circuit 8 upon completion. The arbitration circuit 8 uses the shared memory read completion signal C2 (C
In response to 1), the interrupt signal E2 (E1) being sent is released. Further, the arbitration circuit 8 uses the address of the shared memory 5 /
Which of the CPU1 and CPU2 is used to open the gate to the control bus A3 and the data bus D3 is controlled by sending either of the bus open control signals G1 and G2.

A more specific operation example of the above-described interrupt generation procedure will be described. CPU1 is shared memory 5
Immediately after writing data to the address space A of
The address is set to the designated address a in the address space A. This designated address a may be shared with the CPU 2. The address monitoring circuit 6 which has detected that the address a has been set notifies the arbitration circuit 8 of it by the designated address access signal B1. Upon receiving the notification, the arbitration circuit 8 considers that the address / control bus A3 has been opened, and sends an interrupt signal E2 to the CPU 2. Upon receiving the interrupt signal E2, the CPU 2 determines that the data in the address space A of the shared memory 5 has been updated,
The content is read. When detecting that the reading of the CPU 2 is completed, the monitoring circuit 7 sends a shared memory reading completion signal C2 to the arbitration circuit 8. The arbitration circuit 8 releases the interrupt signal E2 when receiving the shared memory read completion signal C2. By this series of operations, the CPU
As soon as there is a data update from 1 to the shared memory 5, CP
The updated data can be read by U2.

As described above, in the embodiment, the interrupt signal E2 (or E1) is input to the CPU 2 (or 1) on the reading side as soon as the CPU 1 (or 2) on the writing side finishes writing to the shared memory 5. Therefore, each CPU does not need to read the shared memory 5 periodically, and when the writing from one ends, the other can immediately read. That is, each CPU only needs to read from and write to the shared memory 5 without executing periodical processing or external port control, so that extra processing in each CPU becomes unnecessary.

[0012]

As described above, according to the present invention, C
When the writing side CPU finishes writing to the shared memory during data transfer between PUs, the reading side C
Since an interrupt signal is input to PU, C on the read side
The PU does not need to periodically read the shared memory as in the conventional case, and can immediately read from the other when writing from one is completed. That is, each CPU only needs to read from and write to the shared memory without executing the periodic processing or the external port control, and therefore each CPU does not need the extra processing as in the prior art.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an internal block diagram of the shared memory 5 according to the embodiment of the present invention.

FIG. 3 is a block diagram illustrating a conventional shared memory system.

[Explanation of symbols]

 1, 2 CPU 3, 4 Gate circuit 5 Shared memory 6, 7 Address monitoring circuit 8 Arbitration circuit A1, A2, A3 Address / control signal D1, D2, D3 Data bus B1, B2 Designated address access signal C1, C2 Shared memory read Completion signal E1, E2 Interrupt signal G1, G2 Bus release control signal

Claims (3)

[Claims] 1. A shared memory provided so as to be accessible from a plurality of CPUs and having at least one address designated to indicate the end of data writing from one CPU, and each of the shared memories sent from the CPUs. Whether or not the address signal matches the designated address is monitored and a designated address access signal is sent out when the addresses match, and each of the CPUs
A plurality of monitoring circuits that detect completion of data reading from the shared memory and send a shared memory read completion signal, and a read request interrupt signal to the read side CPU in response to the designated address access signal. And one arbitration circuit that releases the interrupt signal in response to the shared memory read completion signal. 2. The CPU arbitration circuit according to claim 1, wherein the shared memory divides and allocates different address spaces for each of the CPUs. 3. The CPU arbitration circuit according to claim 1, wherein the designated address different for each CPU is designated in the shared memory.