KR100380328B1 - Down prevention device at board disconnection of exchange system - Google Patents

Abstract

The hernia monitoring means for detecting the disconnection of the slave board connected to the common bus in the master by detecting the disconnection of the slave board when operating the exchange system using the parallel common bus to prevent the entire exchange system from being shut down. Further, the hernia monitoring means applies a virtual data transfer completion signal to the processor in the master when a hernia is detected when the master selects an arbitrary slave for data access or during execution of the data access. At the same time, interrupt signal that requires exception handling is applied to prevent system down caused by board interruption.

Description

Down prevention device at board disconnection of exchange system

The present invention relates to an exchange system, and more particularly, in the case of board exchange of the exchange system to detect whether the slave board is disconnected during operation of the exchange system using a parallel common bus and to prevent the entire exchange system from being down. It relates to a down prevention device.

The exchanger system using the parallel common bus, as shown in FIG. 1, is attached to the processor (1) and the data access signal of the processor (1) that controls the overall connection operation and maintenance of the exchange system And a master bus (M1) consisting of a common bus interface section (2) for interfacing control signals with a DPRAM (S1a-SNa) and a common bus interface section (S1b-SNb) capable of simultaneously reading and writing data. A plurality of slaves (S1-SN) consisting of) are connected to an address line, a data line, and a control line.

As described above, the master M1 is connected to any slave S1-SN in a state in which the master M1 and the plurality of slaves S1-SN are connected through a parallel common bus including an address line, a data line, and a control line. In the case where the data stored in the DPRAM S1a-SNa is to be accessed, the processor 1 in the master M1 selects an arbitrary slave S1-SN for data access and then accesses the data as shown in FIG. When outputting the request signal DS *, the common bus interface unit 2 connects the common bus interface units S1b-SNb in any of the selected slaves S1-SN to occupy an address line, a control line, and a data line. do.

Subsequently, the slave S1-SN receiving the data access request signal DS * from the master M1 transmits the data stored in the DPRAM S1a-SNa to the master M1 through the occupied data bus. Then, a signal DTACK * for notifying completion of transmission of the corresponding data is transmitted to the master M1 side.

At this time, when the processor 1 in the master M1 receives a signal notifying completion of data transfer from the slave that has accessed the data, the operation for data access ends as shown in FIG.

As described above, when a master connected through a parallel common bus requests access of data stored in an arbitrary slave (DS *), a signal (DTACK *) notifying completion of data transmission when a slave board requesting data access is removed from a slot. Is not generated, the master cannot detect the data transfer completion signal DTACK *.

Therefore, the master determines that an error has occurred in the data transmission bus, which causes a problem that the entire exchange system is down.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described general problems, and an object thereof is to detect whether a corresponding slave board is accessed when a master accesses data stored in a slave in a system executing data transmission and reception through a parallel common bus. When detected by a board failure, the master executes an exception handling program to prevent the system from crashing due to a bus error.

1 is a block diagram showing a connection of a master and a slave in a conventional exchange system.

2 is a timing diagram showing a data transmission process in a conventional exchange system.

Figure 3 is a block diagram of the down prevention device at the time of board replacement of the exchanger system according to the present invention.

4 is a timing diagram showing a data transmission process in an exchange system of the present invention.

<Explanation of symbols for the main parts of the drawings>

M10: Master S10-S1N: Slave

11 processor 12 common bus interface unit

13: hernia detector

The present invention for achieving the above object is further provided with a hernia monitoring means for detecting the hernia of the slave connected to the common bus in the master in a system in which the master and a plurality of slaves are connected in parallel through a common bus. Characterized in that.

In the above-described hernia monitoring means, when the master selects an arbitrary slave and requests data access, the hernia monitoring means detects virtual data on the processor side of the master when a hernia of the selected slave is detected or a hernia of the slave is detected during data access. It is characterized by applying an interrupt signal for requesting exception processing at the same time as applying the transfer completion signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As can be seen in FIG. 3, the apparatus for preventing downtime of board exchange of an exchange system according to the present invention includes a processor 11 and a data access signal of the processor 11 for controlling call connection and maintenance and overall operation of the exchange system. And a plurality of slaves including a master M10 including a common bus interface unit 12 for interfacing control signals with a DPRAM (S10a-S1Na) and a common bus interface unit S11b-S1Nb capable of simultaneously reading and writing data. (S10-S1N) is connected in parallel via an address line, a data line, and a control line, which are common buses, and detects whether the slaves (S10-S1N) connected to each other are connected to the master 13 through a common bus. The hermetic detection unit 13 for transmitting the interrupt signal to the processor 11 is configured to further include a master (M10).

Operation of the data communication between the master and the slave in the present invention having the technical configuration as described above is as follows.

The master M10 is used to access data stored in any of the plurality of slaves S10-S1N connected in parallel through a common bus, for example, data stored in the DPRAM S10a of the first slave S10. When the processor 11 in M10 outputs the data access request signal DS * as shown in FIG. 4, the common bus interface unit 12 in the master M10 is assigned a first slave S10. The common bus interface unit S10b is connected to occupy an address line, a control line, and a data line.

Thereafter, the slave S10 receiving the data access request signal DS * from the master M10 transmits the data stored in the DPRAM S10a to the master M10 through the occupied data bus, and then the corresponding data. The signal DTACK * for notifying completion of the transmission is transmitted to the master M10 side.

At this time, when the processor 11 in the master M10 receives a signal notifying completion of data transfer from the slave that has accessed the data, the operation for data access is terminated.

However, as described above, when the master M10 requests data access to the first slave S10 and occupies a data bus, the first slave S10 that is requested to access data is accessed. When a hernia is removed from the slot while data access is being executed, the information SS on the hernia of the slave S10 is detected by the hernia detector 13 in the master M10 as shown in FIG. 4.

Accordingly, the hernia detection unit 13 generates a virtual response signal DSACK * for notifying completion of data transmission according to the hernia of the first slave S10 to which data is accessed and applies the same to the processor 11. At the same time, an interrupt signal IRQ * for requesting exception operation processing is applied to the processor 11 side as shown in FIG.

At this time, the processor 11 of the master M10 terminates the data access operation from the first slave S10 according to the virtual data transmission completion signal DSACK * applied by the hernia detection unit 13. At the same time, an exception handling operation is executed according to the interrupt signal IRQ * to prevent the system from going down.

As described above, the present invention provides a virtual data transmission completion signal in a device that monitors hernia hernia when a slave hernia occurs when a master accesses the slave during operation of a system connected in parallel through a common bus. This prevents the master from going down by generating an interrupt and an interrupt for exception handling, thus providing stability to the operation of the system.

Claims (3)

In a system in which a master and a plurality of slaves are connected in parallel through a common bus, And a hernia monitoring means for detecting a hernia of a slave connected to a common bus in the master. 2. The method of claim 1, wherein the hernia monitoring means applies a virtual data transfer completion signal to the processor in the master when a hernia of the selected slave is detected at the time when the master selects an arbitrary slave and requests data access. And an interrupt signal for requesting exception handling at the same time. 2. The method of claim 1, wherein the hernia monitoring means applies a virtual data transfer completion signal to the processor in the master when a hernia of the slave is detected while the master selects an arbitrary slave and performs data access. At the same time, an interrupt signal for the board system of the exchanger system, characterized in that for applying an interrupt signal requesting exception processing.