JPH06223031A - Transfer controller - Google Patents

Abstract

PURPOSE:To facilitate system alterations by eliminating the need for a memory which stores device addresses. CONSTITUTION:This transfer controller has use right setting circuits 37 and 29, transfer control circuit 26 and 31, address input/output circuits 32 and 33, and data input/output circuits 34 and 35 as interfaces between the transfer controller 3 and common buses 4 and 5. Further, this controller has a synchronization control circuit 52 which generates a transmission request signal transmission timing signal, sent control signal time monitoring circuits 53 and 50 which detect whether or not there is a response within a mean time, and sent control signal minimum time width guaranteeing circuits 54 and 51 which guarantee the shortest time wherein no malfunction is caused even if a sent control signal varies.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a common I / O bus shared transfer control device for controlling transfer between a plurality of common I / O buses each having an independent right of use in an information processing system.

[0002]

2. Description of the Related Art In a conventional first system for writing data from a first bus of a plurality of common input / output buses to a shared storage device, reading data from the storage device, and transferring the data to a second bus, For this data transfer, the CPU connected to the second bus must interrupt the original processing.

Also, in a second conventional system in which both buses are connected by a coupling device instead of a shared storage device,
After data is stored in the responsible local storage unit from the input / output device connected to the first bus, the input connected to the second bus via the first bus, the coupling device, and the second bus. Data is transferred to the output device. If a large amount of data is to be transferred, the first bus will be occupied, and as a result, the usage efficiency of the bus and the performance of the CPU connected to the first bus will decrease.

A problem in bus transfer is a collision of bus transfer requests requested by two or more devices. In order to solve this, in the second conventional device, the bus combiner replaces the data transfer destination device with the bus transfer request. The method of receiving the contents and ending the use of the bus is adopted. The coupling device must then have a memory for storing the contents of the bus transfer. Therefore, an increase in the transfer amount requires a larger memory. If there are multiple memories and a failure occurs, the recovery process becomes complicated.

Further, in the coupling device, after receiving the transfer destination address, the judging unit judges whether or not the device having this address is connected to the second bus. If a device was present, a bus use request signal was sent to the second bus. An example of this is US Pat.
See No. 9.

[0006]

[Patent Document 1] US Pat. No. 423
In the apparatus shown in No. 4919, the given destination address is changed and transmitted. For this judgment and address change, it is necessary to store the address of the device connected to the second bus. Therefore, if there is new installation, modification, or removal of equipment connected to the second bus,
The contents of this memory must be changed. A mistake in changing this content causes a system failure.

An object of the present invention is to provide a transfer control device that can easily cope with the above system change.

[0008]

In order to solve the above-mentioned problems, in the device of the present invention, a central processing unit and a peripheral device connected to two common input / output buses and connected to each common input / output bus. In a transfer control device for writing and reading data to and from a central processing unit and a peripheral device connected to a common input / output bus from the other side, one is provided for each of the two common input / output buses. Each of them monitors the response waiting time of transfer for a predetermined time after an address and data transmission control signal is input from one common input / output bus, and when the predetermined time elapses without a response signal, the other one is monitored. A sending control signal time monitoring circuit that generates a transfer request signal for the common input / output bus,
When there is a transfer request response to the one common input / output bus after the transfer control signal time monitoring circuit has generated the transfer request signal, a change in the address and data transmission control signals on the other common input / output bus is detected. It has a minimum time width guarantee circuit that guarantees the sending time of the transfer address and data transmitted to the other common input / output bus for a certain time or longer.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, in order to facilitate understanding of the embodiments of the present invention, the relationship between transmission of a destination device address, a command signal, and data and its response signal will be described below.

Referring to FIG. 2, devices connected to the common buses 4 and 5, such as the CPU 41 and the input / output device 42 shown in FIG.
Or 43, when the data transfer is performed between the busses 43 and 43, after the bus use right is established, the destination device address and the command signal E are included in the common bus in synchronization with the transmission of the address and the data transmission control signal A. Send to bus C. In the case of data output, the output data is output to the data bus D on the common bus in synchronization with the control signal A. CP
Each device connected to the common bus, such as U41, the input / output device 42 or 43, changes the control signal A, for example,
In response to "0" to "1", the destination device address on the address bus C is decoded. When the destination device address indicates its own device as a result of this decoding, the command signal E is input. If it is a data output, the content of the data bus D is also input. Next, each of the above devices sends the notification of this input to the sending device by the change of the response control device signal B, for example, "0" to "1". The sending device which has received this notification changes the control signal A from, for example, "1" to "0". In response to the change of the control signal A, the control signal B is changed from "1" to "0", for example.

Next, an embodiment of the present invention will be described in detail. Since the circuit configuration is symmetrical with respect to each bus, a case where the first bus 4 to the second bus transfer has a higher transmission priority will be described.

Referring to FIG. 1, the transfer control device 3 of the present invention uses the right-of-use setting circuits 37 and 29, transfer control circuits 26 and 31, address input / output circuits 32 and 33, and data input / output as a common bus interface. Circuits 34, 35
Have. Also, a synchronization control circuit 52 for generating a transmission request signal transmission timing signal, and a transmission control signal time monitoring circuit 53, 5 for detecting whether or not there is a response within an average time.
0 and a transmission control signal minimum time width guarantee circuit 5 that guarantees a minimum time that does not cause a malfunction even if the transmission control signal changes.
It has 4,51.

Next, an embodiment of the present invention will be described in detail. When a device connected to the first bus changes the signal (A in FIG. 2) of the data transmission signal line 102 from "0" to "1", the transfer control circuit 26 causes the signal line 1
Via 50, the transmission control signal time monitoring circuit 50 and the second bus transmission control signal minimum time width guarantee circuit 51 are notified that the signal has changed. The other device connected to the first bus 4 decodes the destination device address on the address bus according to the timing of the change of the signal A on the line 102,
The response signal is sent to the first bus 4. The response time of the device connected to the first bus 4 is generally an average value. Therefore, no response within the average response time means that there is no device having the destination device address corresponding to the first bus 4. Time monitoring circuit 5
When 0 detects that there is no change (response) of the signal A from the line 102 within this average time, the time monitoring circuit 50 sends the transmission request signal via the line 151 to the second bus right setting circuit 29. And transmission control signal minimum time width guarantee circuit 51
Give to. In response to the change of the signal A, the synchronization control circuit 52 sends this transmission request signal transmission timing instruction to the line 161.
To the time monitoring circuit 50 via. In response to this request signal, the usage right setting circuit 29 sets the usage right via the signal line 107. After the use right setting is completed, the use right setting circuit 29
Is transferred via the signal line 152 to the second bus transfer control circuit 31
Notify the bus permission. In response to the permission signal and the timing signal applied from the control circuit 52 via the line 159, the transfer control circuit 31 causes the address input / output circuit 3 to operate.
3 and the data input / output circuit 35, a sending instruction signal is sent. Therefore, the transfer control signal is transmitted from the first bus 4 to the line 10
2, the transfer control circuit 26, the line 150, the transmission control signal minimum time width guarantee circuit 51, the line 153, the transfer control circuit 31, and the line 108 are transmitted to the second bus 5. The command signal is transmitted from the first bus 4 to the line 104, the transfer control circuit 2
6, the line 154, the transfer control circuit 31, and the line 110 to the second bus 5. Address is the first bus 4
From the line 105, the address input / output circuit 32, the line 117, the address input / output circuit 33 and the line 111 to the second bus 5. Data is from first bus 4 to line 10
6, data input / output circuit 34, line 119, data input / output circuit 35, and line 112 to the second bus 5. The response control signal applied via the line 107 is the transfer control circuit 31, the line 155, the transfer control circuit 26 and the line 1.
It is transmitted to the first bus 4 via 03. Second bus 5
The device connected to the device determines the destination address on the address by the change of the signal (A in FIG. 2) and responds if its own device is instructed, and the transfer of the bus ends. If the device having the destination device address is not connected to the second bus 5, the first bus transfer is forcibly terminated. If the signal A of the signal line 108 does not change within the time guaranteed by the transmission control signal minimum time width guarantee circuit 51 after the bus transfer of the first bus 4 ends, the bus transfer of the second bus 5 also ends. To do. The response of the device connected to the first bus 4 may be abnormally delayed, and there may be a response after or during the transmission on the second bus 5, and the bus transfer of the first bus 4 may end.
This situation occurs during the determination of the destination address in the device connected to the second bus 5, and the transmission on the second bus 5 ends, resulting in an erroneous determination and an erroneous operation of the device. In order to solve this problem, when the transfer control circuit 31 changes the signal on the line 108 in response to the signal on the line 152, the transmission control signal minimum time width guarantee circuit 51 causes the signal A to be supplied via the line 102. The signal on the line 108 is held in a changed state for a minimum time period in which a malfunction does not occur even when is changed. After that, the transmission control signal minimum time width guarantee circuit 51 changes the signal on the line 108 again and terminates the bus transfer of the second bus 5 even if there is no response from the second bus 5. As a result, the present invention does not require a circuit for storing the address of the device connected to the second bus 5.

[0014]

According to the present invention, it is detected that a bus transmission request waits for a certain period of time in order to transmit a bus transfer from the own bus to the other bus, and a bus transfer request signal is generated on the other bus. After requesting the bus right from the circuit and the partner bus,
By providing a circuit that guarantees the address and data transmission time of the bus transfer transmitted to the other system bus for a certain time or more when there is a bus transfer response to the own system bus, the device existing on the other system bus to be connected can be There is an effect that it is not necessary to provide a circuit for storing an address in the transfer control device.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a timing diagram according to the present invention.

[Explanation of symbols]

 3 Transfer Control Device 4 First Shared Bus 5 Second Shared Bus 29, 37 Usage Right Setting Circuit 32, 33 Address Input / Output Circuit 34, 35 Data Input / Output Circuit 50, 53 Transmission Control Signal Time Monitoring Circuit 51, 54 Transmission Control signal minimum time width guarantee circuit

Claims (1)

[Claims] 1. A central processing unit and a peripheral device connected to two common input / output buses and connected to respective common input / output buses from a central processing unit and a peripheral device connected to a partner common input / output bus. A transfer control device for writing and reading data is provided so as to correspond to each of the two common input / output buses, each of which receives an address and data transmission control signal from one common input / output bus. A transmission control signal time monitoring circuit that monitors the response waiting time of the transfer for a predetermined time after being input, and generates a transfer request signal to the other common input / output bus when the predetermined time elapses without a response signal. If the transfer control signal time monitoring circuit generates a transfer request signal and then a transfer request response is sent to the one common input / output bus, the other common input / output A transfer characterized by having a minimum time width guarantee circuit that guarantees the sending time of the transfer address and data transmitted to the other common input / output bus for a certain time or more after the change of the address and data sending control signal on the bus. Control device.