JPH0651910A - Duplex bus device - Google Patents

Abstract

PURPOSE:To improve reliability by surely transferring data even in the condition of congesting duplex buses. CONSTITUTION:Each master is provided with an access monitoring means 4 for detecting whether a data transfer request addressed to the master itself is inputted by using one bus or not while transferring data from the master itself to the other master by using the other bus by monitoring signals on the duplex bus, an access holding means 5 for holding access during execution and renouncing the inside bus when the state of inputting the data transfer request addressed to the master itself by using one bus while transferring data from the master itself to the other master by using the other bus is detected and an address holding means 6 for holding an address due to the access during holding and continuously outputting the address to the other master. After the data are completely transmitted from the other master to the master itself, the bus right of the inside bus is possessed so as to activate the held access again.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duplicated bus device in which a duplicated bus is used by a plurality of masters (computer devices). More specifically, the amount of data transferred between a plurality of masters is large. And, as a result, even if the bus is congested, the present invention relates to a duplicated bus device that ensures data transfer between them.

[0002]

2. Description of the Related Art In a distributed control system or the like which is required to have high reliability, a computer device in charge of control calculation and a bus (communication line) connecting these computer devices are duplicated and one of them fails. In some cases, a redundant configuration is adopted so that the other can back up.

FIG. 3 is a conceptual diagram showing the structure of a conventional dual bus device of this type. In the figure, MS1 and MS2 are computer devices (CPU cards) that can be masters, B
S is a bus having a duplex configuration, and each master MS1, MS2,
Slave SR1, S controlled by each master
R2 ... Is connected. In the device configured as described above, each master uses one of the buses of the redundant configuration by a bus adapter having an interface function with the bus BS for data transfer, and the master of the other master and the master of the other master. If it is configured to drive the internal bus of 1 at a time, the following problems occur in data transfer between the two masters MS1 and MS2.

That is, when data is transferred from one master to the other master using different buses, the data transfer from one master to the other master does not wait for each other to finish. If both are simultaneously performed, both accesses cannot be realized without using the internal bus of each master at the same time. However, in reality, it cannot be satisfied.

Therefore, the conventional apparatus is provided with a function of prioritizing the access from one master with respect to the access from the other master, and the access from the other master is performed after the priority processing is completed. It was configured to be possible.

[0006]

However, according to the conventional apparatus having such a structure, when the master having a high priority processing frequency is frequently accessed, the access from the other master is always kept waiting. That means
There is no guarantee that the access will be made securely. In particular, when the amount of data transferred between masters is large, the bus is congested and data transfer from the other master becomes impossible.

The present invention has been made in view of such a situation, and in a computer device in which a duplicated bus is used by a plurality of masters, the data transfer amount between the masters is increased and the buses are congested. Even in such a case, it is an object of the present invention to provide a dual bus device capable of reliably performing data transfer between masters.

[0008]

The present invention, which achieves such an object, has a plurality of masters coupled to a bus having a duplex configuration, and each master can simultaneously access another master through the duplex bus. A redundant bus device that monitors each master for signals on the redundant bus, and uses one bus while transferring data to another master by itself. Access monitoring means to detect whether or not a data transfer request is sent to itself, and the access monitoring means uses one bus while it is transferring data to another master. When it detects that there is a request to transfer data to itself, it holds the access pending means that puts the current access on hold and abandons the internal bus, and holds the address of this access pending access. An address holding means for outputting the address to the other master is provided together, and after the data transfer from the other master to itself is completed, the bus right of the internal bus is acquired and the suspended access is restarted. Is a dual bus device.

[0009]

The access monitoring means detects whether or not there is a data transfer request from another master while its own master is transferring data to another master. When the access monitoring means detects the state, the access holding means suspends the operation being accessed by its own master (CPU) and suspends the use of the internal bus. As a result, the internal bus can be used by the access from the external master.

The address holding means holds the address of the access that has been suspended until the data transfer from the external master is completed, and immediately after the data transfer from the other master to itself is completed, the internal bus is held. The bus right of is acquired and the access that has been suspended can be restarted.

[0011]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a conceptual diagram showing the construction of an embodiment of the present invention. In the figure, BS is a bus having a duplex configuration, and B1, B
It consists of two. MS1 and MS2 are two CPU devices that can be masters coupled to the bus BS having a dual configuration, and the internal configuration of each of these masters is the same. Although not illustrated here, the bus BS having a dual configuration is
It is assumed that a plurality of slave devices (for example, I / O devices) controlled by each master are connected.

In each of the masters MS1 and MS2, 11,
A bus adapter 12 is coupled to the redundant bus BS and has an interface function for each of the redundant buses B1 and B2. 1 is a C that operates as a master device
PU, 2 is a memory, and 3 is an internal bus that connects the CPU 1, the memory 2, and the bus adapters 11 and 12 to each other. Here, the CPU 1 in each of the masters MS1 and MS2, via the bus adapter 11 or 12, the bus BS of the duplicated configuration, the bus adapter 11 or 12 in the other master, and the internal bus 3, the memory in the other master. Data can be transferred to. Data transfer between each master
For example, it is necessary to keep the database of each master the same.

Reference numeral 4 denotes access monitoring means, which is the bus adapter 1
Signals on the duplicated bus BS and internal bus 3 via 1 and 12
Monitors the above signal and detects whether there is a request to transfer data to one of the masters while using one of the buses to transfer data to another master. It is for. As the access monitoring means, a circuit for monitoring whether or not there is an address addressed to itself on the bus (for example, bus B2) is used.

Reference numeral 5 is an access holding means for holding the access made by one's own master using one of the duplicated buses BS (for example, B2). If it detects that there is a data transfer request to itself using one bus (B1) while transferring data to another master using one bus (B2), the CPU1 Right to hold access during execution and allow CPU 1 to use internal bus 3 (bus right)
Is configured to be abandoned.

Reference numeral 6 is an address holding means for holding the access address while the access holding means 5 holds the access by the CPU 1. In this case, the bus adapter 1 is used.
In the example provided in 1 and 12, it is configured by a register, for example. The address held by the address holding unit 6 is configured so that the address is continuously output to another master side via one bus (for example, B2) even if the access from the master is on hold. is there.

The operation of the apparatus thus configured will be described below. FIG. 2 is a flowchart showing an example of the operation. Here, first, the CPU 1 in the master MS1 accesses the memory 2 in the master MS2 via the internal bus 3 in the master MS1, one bus B2 of the bus BS having the redundant configuration, and the internal bus 3 in the master MS2. A case (such data transfer is called transfer (a) for convenience) is assumed. The CPU 1 in the master MS2 accesses the memory 2 in the master MS1 via the internal bus 3 in the master MS2, the other bus B1 of the duplexed bus BS, and the internal bus 3 in the master MS1 (data transfer). This is referred to as transfer (b).

First, as shown in (a) and (b),
The CPU 1 of the master MS1 is going to execute the transfer (a) which is an access to the memory 2 of the master MS2 via the internal bus 3, the bus adapter 12, and the bus B2. In this state, in the master MS1, the CPU1
Owns the bus right of the internal bus 3. In this state, it is assumed that the other master MS2 outputs an access request corresponding to transfer (b) via the bus B1 and the bus adapter 11.

In this case, the access monitoring means 4 of the master MS1 detects a state where two such access requests conflict with each other, and outputs the signal SUSP indicating that there is an access request from another master MS2 (c ) To activate. Address holding means 6 of master MS1
Receives the signal SUSP becoming active,
The address of the transfer (a) from the master MS1 to the master MS2 is held as shown in (d).

Similarly, the access holding means 5 of the master MS 1
Receives the signal SUSP becoming active,
As shown in (a) and (b), the transfer (a) from the master MS1 to the master MS2 is suspended (interrupted), and the bus right by the CPU1 of the internal bus 3 of the master MS1 is abandoned. When the bus right by the CPU 1 of the internal bus 3 is abandoned, the data transfer (b) from the master MS 2 is performed without collision on the internal bus 3.

Even in such a state, the address held by the address holding means 6 in the master MS1 is continuously transferred to the master MS2 side via the bus B2 as shown in (d). As a result, the access request (transfer (a) request) is continuously issued to the internal bus 3 of the master MS 2. Therefore, the master MS
When the data transfer (b) from 2 is completed, the master MS1
In the inside, the CPU 1 acquires the bus right of the internal bus 3 and restarts the operation of the transfer (a) held by the access holding means 5. The restart to the transfer (a) here promptly changes the bus right of the internal bus 3 of the master MS 2 by the transfer request (address) sent from the address holding means 6 even while the transfer (b) is being executed. It will be executed immediately because it can be acquired.

When the transfer (a) is performed via the bus B2 and the transfer (b) is performed via the bus B1, the same operation is performed in the master MS2. In the above explanation,
It is assumed that, of the duplexed buses, the access passing through the bus B1 is preferentially processed.

[0022]

As described in detail above, according to the present invention, even when two masters simultaneously make an access request before the end of access to the other master, Collisions on the internal buses of the respective masters can be avoided, and access requests that are occurring simultaneously can be executed reliably.

Therefore, it is possible to realize a highly reliable dual bus device that can reliably transfer data even if the bus having a dual configuration is congested.

[Brief description of drawings]

FIG. 1 is a structural conceptual diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing an example of operation.

FIG. 3 is a conceptual diagram of a configuration of a conventional device.

[Explanation of symbols]

 BS Duplex configuration bus (communication line) MS1, MS2 Master 1 CPU 2 Memory 3 Internal bus 4 Access monitoring means 5 Access holding means 6 Address holding means 11, 12 Bus adapter

Claims (1)

[Claims] 1. A dual bus device having a plurality of masters coupled to a dual bus, each master being configured to simultaneously access other masters through the dual bus, wherein each master has a dual bus. Monitors the signals on the bus and detects whether there is a request to transfer data to itself using another bus while transferring data to another master using one bus. When the access monitoring unit and the access monitoring unit detect that a data transfer request to the other master is being made using one bus while the data is being transferred to another master using one bus , The access holding means for holding the access being executed by itself and abandoning the internal bus, and holding the address by this access pending access and outputting the address to other masters subsequently. A redundant bus device, which is provided with an address holding means for acquiring the bus right of the internal bus and restarts the suspended access after the data transfer from another master to itself is completed.