JPS62192845A - Bus control system - Google Patents

Abstract

PURPOSE:To use a single system bus for multi-purpose, and also, efficiently by separating the single system bus into the first high speed use and the second low speed use by a bus separating means. CONSTITUTION:Gates 51, 52 for constituting a bus separating means 5 control on/off of a connection to an address signal line (1)', and a control signal line (2)' of a system bus (d) side from a system bus (c) side of an address signal line (1) and a control signal line (2) of a system bus (d) side, and a gate 53 controls on/off of a flow of a data in both directions by data lines (3), (3)'. In such a way, the gates 51-53 switch a signal line of the system bus (c) side to each signal line of the system bus (c) side, to each signal line of the system bus (d) side, and the system bus can be separated into (c) and (d).

Description

[Detailed Description of the Invention] [Summary] A bus control method for a data processing system, in which a main storage device and a second input/output device corresponding to a hard disk that is required to process data at a higher speed than a predetermined data processing speed, for example. When processing data with the device, the bus separation means separates the system bus from the system bus between the first input/output device that processes data at a predetermined processing speed and the main processing unit, and connects the system bus to the second input/output device. By setting and using it as a dedicated bus between the main memory and the main memory, a single system bus can be used for multiple purposes and efficiently.

[Industrial Application Field] The present invention is applicable to two types of devices: a low-speed input/output device that processes data without specifying a processing speed, and a high-speed input/output device that needs to process data at a higher speed than a predetermined processing speed. Bus control methods for data processing systems that transfer data through one system bus, especially when processing data at high speeds Modern data processing systems have many inputs and outputs that require various data processing speeds. The trend is for devices to be connected through system buses and for these input/output devices to be required to operate simultaneously.

There is a need for a method for realizing such simultaneous operations without increasing the number of signal lines of the system bus.

[Prior Art and Problems to be Solved by the Invention] FIG. 3 is a diagram illustrating a conventional example using a single bus, and FIG. 4 is a diagram illustrating a conventional example adding a dedicated bus.

Figures 3 and 4 show an overview of the configuration of a conventional data processing system.The system configuration consists of a main processing unit (hereinafter referred to as CPU) that controls various processing operations of the data processing system, corresponds to CPU1. at a predetermined processing speed. A low-speed input/output device 2 that transfers data to and from a main storage device (hereinafter referred to as "intermediate") 4, etc., and a low-speed input/output device 2, which corresponds to, for example, a hard disk,
A high-speed input/output device 3 that transfers data to and from the UI, MS4, etc., and a high-speed input/output device 3 that stores data based on address and control signal specifications from the CPU, low-speed input/output device 2, high-speed input/output device 3, etc. It is composed of 4.

In the case of FIG. 3, the CPU, low-speed input/output devices 2. High-speed input/output device 3. MS4s are connected by a single system bus (al), and this single system bus (
Data is inherited through the address line, control signal line, and data line that are inherited through a).

On the other hand, FIG. 4 shows the CPU, low-speed input/output device 1, high-speed input/output device 3. System bus (a) that connects MS4 and
A dedicated bus (11
), and in particular data transfer between the high-speed input/output device 3 and the MS 4 is processed through a dedicated bus (b).

In the case of FIG. 3, the normal system bus (al) is controlled by system bus request signals (hereinafter referred to as BRQ) sent from the low-speed input/output device 2 or the high-speed input/output bag W3, for example.
is sent to the CPUI and controlled under the control of the CPUI.

Furthermore, the control of the system bus (a) in FIG. 4 is the same as that in FIG. 3, but the dedicated bus (bl) is controlled through the control line from the high-speed input/output device 3, treated as irrelevant.

Therefore, for example, as in the case of FIG.
system bus (a) for data processing with CPUI
If the high-speed input/output device 3 occupies the MS at the same time,
Even if a BRQ■ occurs to access 4, the low-speed input value W2 will have to wait until the system bus (al) is finished using, and the high-speed input/output bag R3 will not be able to fully demonstrate its performance. There will be no.

In order to solve the above problem, if a dedicated bus (b) is provided between the high-speed input/output device 3 and the MS 4 as shown in Figure 4, there are problems such as the need for extra signal lines. occurs.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the invention in detail.

The block diagram in Figure 1 is the functional block 1 explained in Figure 3.
~4 and the system bus (+l:
1. (dl) and a bus separation means 5 for separating the system bus (C) and the system bus (d) while the BRQ■ from the high-speed input/output device 3 is being sent.

[Effect]

While a single system bus is used between the CPU and low-speed input/output devices, a data processing request occurs between the main memory and a high-speed input/output device, such as a converter disk that requires high-speed data processing. Then, the bus separation means separates the single system bus into the first system bus between the cr'u and the low-speed input/output device, and the second system bus between the main storage device and the high-speed input/output device. By separating and setting a dedicated bus for high-speed input/output devices and main storage, a single system bus can be used for multiple purposes and efficiently.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 1 and 2.

FIG. 2 shows a block diagram illustrating the invention in detail. Note that the same reference numerals indicate the same objects throughout the figures.

The lotus separating means 5 includes gates 51 to 5 in the embodiment shown in FIG.
An example configured with 3 is shown. The gates 51 and 52 connect the address signal line (1) 1, the control signal line (from the C1 side to the address signal line (1)' and the control signal line (2)' on the system line (d) side). The gate 53 controls the data line f3L (on/off of bidirectional data flow at 31').

Further, the lotus separation means 5 is connected to the CPL II and the low speed input/output device 2.
The system bus (C) side that connects the MS 4 and the high-speed input/output device 3 is separated from the system bus (d) side that connects the MS 4 and the high-speed input/output device 3.

The signal line (e) from the high-speed input/output device 3 sends BRQ■ as a bus separation signal to the bus separation means 5, and controls the on/off of each gate 51 to 53 in the lotus separation means 5.

In this state, when the CPUI is accessing the low-speed input/output device 2, when the high-speed input/output device 3 accesses the MS4, BRQ■ is sent to the gates 51 to 53 through the signal line (e).
Send to.

As a result, the gates 51 to 53 transmit the signals of the system bus (C1 side signal lines (1) to (3)) to the system bus (d
The signal is no longer transmitted to the signal lines (1)' to (3)' on the l side, and the system bus (C) and system bus (d) are separated.

However, the data processing operation between the CPU 1 and the low-speed input/output device 2 connected to the system bus (C1) can continue as is.

In this state, the high-speed input/output device 3 is able to access the MS4 using the system bus (dl) regardless of the usage status on the system bus (C) side, and the performance of the high-speed input/output device 3 is fully maintained. It becomes possible to demonstrate this.

(Effects of the Invention) According to the present invention as described above, there is an effect that a single system bus can be used for multiple purposes and efficiently.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining a conventional example using a single bus, and FIG. 4 is a diagram explaining a conventional example using a dedicated bus. Diagrams illustrating the added conventional examples are shown. In the figure, 1 is a CPt1, 2 is a low-speed input/output device, 3 is a high-speed input/output device, 4 is a gate, 5 is a bus separation means, and 51 to 53 are gates, respectively. Book, Iroki iQ Pakuri E Soe (B Kai 3 Bukku Map No. 1)

Claims (1)

[Claims] A plurality of input/output devices (2, 3) are connected via a system bus,
Data for simultaneous data transfer between the main processing unit (1) and the input/output device (2), and between the main storage device (4) and the input/output device (3) through the system bus ((c), (d)) In the processing system, when processing data between the main storage device (4) and the input/output device (3), the system bus ((c), (d)) is connected from a predetermined position to the first system bus ((c). )) and the second system bus ((d)) for a predetermined period of time, and during data processing between the main processing unit (1) and the input/output device (2) , the first and second connected in the same state
When processing data between the main storage device (4) and the input/output device (3), the bus separating means (5) While receiving the bus request signal [(2)] from the output device (3), the second system bus ((d)) is separated from the first system bus ((c)). Input/output device (3
) and the main storage device (4), and the second
The input/output device (3) through the system bus ((d)) of
A bus control method characterized by data transfer with.