JPS63188257A - Bus acquiring system - Google Patents

Abstract

PURPOSE:To perform a processing without waiting a module issuing a bus request for a long time, by enabling the bus to be used again after another one module uses the bus when the bus request is not reset after a prescribed amount of data are transferred. CONSTITUTION:A bus request validity indication circuit 100, when the bus request being still valid after the usage of the bus is permitted and the data transfer of the prescribed amount of data are performed, sets the output at a logic (1) after a bus acknowledge signal is reset. And such output state is transferred in order to the bus request validity indication circuit 100 and a bus request validity indication shift circuit 300 of an another bus usage control circuit 601, and the sending of the bus acknowledge signal is controlled. As a result, when not bus request signal is still reset after the data transfer of the prescribed amount of data in its own module, the usage of the bus after the usage of the bus by another one module is permitted again.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to a bus acquisition method thereof.

〔overview〕

The present invention provides a bus acquisition system that includes a plurality of modules each connected to one bus, and a bus controller that controls the use of the bus using a bus acknowledge signal in response to a bus request signal from each module. The bus use circuit instructs each of the above modules to hold the state of whether the bus request signal from the module is valid or not. For example, if the bus request signal from the module is logic "L", the above hold When the instruction status is logic "1", the bus acknowledge signal is set to logic "1" to permit the use of the bus for a certain period of time to transfer a certain amount of data, and after transferring the certain amount of data, the bus is If the request is not reset, the module that issued the bus request is granted permission to use the bus by allowing another module to use the bus again after it has been used.
This allows permission regardless of priority, so that users do not have to wait for a long time.

[Conventional technology]

If there are multiple modules on one bus, requests to use the bus may be issued from multiple modules. In such a case, it is necessary to select one of the modules issuing bus usage requests and have that module use the bus.

Conventionally, the above control has been performed as follows. First, a bus controller is installed in the bus system to control the bus, and each module sends a bus request signal to the bus controller to request bus use, and the bus controller sends a bus acknowledge signal to grant permission to use the bus. to each module, and each module makes the bus request signal logic rlJ if it wants to use the bus. When bus request signals are raised from multiple modules, the bus controller sends a bus acknowledge signal to the module with the highest priority from among those that have raised bus request signals according to a predetermined priority order.
The system was to give the bus the right to use the bus.

[Problem that the invention seeks to solve]

In the conventional bus acquisition method described above, the genetics for bus requests are determined in advance, so
A module that is assigned a low-brarity request has the disadvantage of having to wait for a long time when many bus requests are issued from modules with a higher brararity.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus acquisition method that eliminates the above-mentioned drawbacks and can process bus requests without making a module wait for a long time.

[Means for solving problems]

The present invention provides a bus acquisition system that includes a plurality of n modules each connected to one bus, and a bus controller that controls the use of the bus using a bus acknowledge signal in response to a bus request signal from each module. The bus controller is provided for each of the modules, and includes n bus use control circuits that each control the use of the bus of its own module, and each bus use control circuit receives a bus request signal from its own module for a certain period of time. a bus request valid instruction circuit that instructs whether the bus request is valid or not; a bus acknowledge signal control circuit that controls the sending of the bus acknowledge signal based on the output of this bus request valid instruction circuit; A bus request valid indication shift circuit that transfers the output state of the bus request valid indication circuit of its own module to the above bus request valid indication circuit corresponding to another module that is outputting a bus request signal when the bus request signal is not being output. Controls the input of the bus request signal from the own module to the bus request valid indication circuit by the output of the bus request termination indication circuit that instructs that the bus request signal has been reset and the bus request termination indication circuit corresponding to other modules. a bus request input control circuit, and the output of the bus request valid indication shift circuit is sequentially input to one input of the bus request valid indication circuit of the next bus use control circuit and one input of the bus request valid indication shift circuit. They are characterized by being connected to each other.

Further, the bus acquisition method of the present invention is a method in which use of the bus is permitted when the bus request signal is logic "1" and the bus acknowledge signal is logic "1". This is a method in which bus use is permitted when the output of the instruction circuit is logic "1", and the bus acknowledge control circuit is configured when the output of the bus request valid instruction circuit is logic "1" and the bus request signal is logic "1". When , the above bus acknowledge signal is set to logic “1”.
It can be configured as follows.

[For production]

When the bus request signal from the own module is valid, the bus request valid instruction circuit causes the output to be, for example, logic "1", and when the bus request signal from the own module is logic rlJ, the bus acknowledge signal control circuit sets the bus acknowledge signal to logic "1",
Allows the own module to use the bus and transfers a certain amount of data. At this time, the output of the bus request valid indication shift circuit becomes logic "O", and the bus acknowledge signals in other modules become logic "0", and use of the bus is not permitted.

After the above-described certain amount of data has been transferred, the pass acknowledge signal of the own module is reset to the logic "0" by the output of the above-mentioned bus request valid indication circuit becoming the logic "0" after a certain period of time after the bus acknowledge signal becomes the logic rlJ. 0". On the other hand, whether the bus request signal is logic "1" or logic "0" is determined by the bus request end instruction circuit.
”, logic “0” is input to the bus request signal control circuit of the bus usage control circuit of each other module,
Bus request signals from other modules are controlled so that bus request signals from other modules are not input while the own module is using the bus.

Furthermore, if the bus request is still valid even after bus use is permitted and a certain amount of data has been transferred, the bus request valid indication circuit outputs the bus request after the bus acknowledge signal is reset. Make it logical rlJ.

Then, the output state of this bus request valid instruction circuit is sequentially transferred by the bus request valid instruction shift circuit to the bus request valid instruction circuit and bus request valid instruction shift instruction circuit of the other bus use control circuits, and is transferred to the bus request valid instruction circuit and the bus request valid instruction shift instruction circuit of the other bus use control circuits in order Controls the sending of bus acknowledge signals in As a result, if the bus request signal is still not reset after the own module has transferred a certain amount of data, use of the bus is permitted again after any one other module uses the bus.

Therefore, it is possible to process a module that has issued a bus request without making it wait for a long time, regardless of the library priority.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and shows a case where there are three modules. FIG. 2 is a partial configuration diagram showing one of the bus use control circuits in FIG. 1.

In this embodiment, the modules (
1) 1, module (2) 2 and module (3) 3
and a bus controller 5.

The bus controller 5 includes three bus use control circuits 601 and 60 that control bus use for each module.
2 and 603, and are connected to each other in a predetermined manner.

One of the inputs of the bus use control circuit 601 for the module (1)l is connected to the bus request signal (1)10 from the module (1)1, and the other two inputs are connected to the bus use control circuits 602 and 603. A three-man AND gate 72 is connected to the outputs A and B of the request end instruction flip-flops 82 and 83, respectively, and one input is connected to the output of the AND gate 72, and the other input is connected to the OR gate of the bus use control circuit 602. bus request valid indication to the output of shift gate (1) 32.

A two-man powered AND gate 52 connected, a two-man powered AND gate 51 with one input connected to the other input of the AND gate 52, and two inputs connected to the outputs of the AND gates 51 and 52, respectively. or gate 57 and
A bus request request instruction flip-flop (F/F/
F) Bus acknowledge gate (1) consisting of (1) 41 and an AND gate with one input connected to the output of AND gate 72 and the other input connected to the output of bus request valid indication flip-flop (1) 41 21 and an inverter 61 whose human power is connected to the output of the AND gate 72
and a two-person AND gate circuit 6 whose one input is connected to the output of the bus request valid indication flip-flop (1) 41 and the other input is connected to the output of the inverter 61.
7, and a shift gate (2) whose one input is connected to the output of the inverter 61 and whose other input is a bus request valid indication.
A two-man AND gate circuit 66 connected to the output of 32
and a bus request valid indicating shift gate (1) 31 consisting of a two-man OR gate whose two inputs are connected to the outputs of AND gate circuits 66 and 67, respectively, and a clock signal whose input is connected to the bus request signal (1) 10. It includes a bus request end instruction flip-flop (F/F) 81 whose terminal is connected to the output of the bus technology gate (1) 21 and outputs an output C. Here, the other input of the AND gate 51 is connected to the output of the bus request valid instruction flip-flop (1) 41, and the reset terminal of the bus request valid instruction flip-flop (1) 41 is connected to the output of the bus acknowledge gate 21. .

Here, as shown in FIG. 2, the AND gate 72 controls the bus request input control circuit 500, and the AND gates 51 and 52, the OR gate 57, and the bus request valid instruction flip-flop (1) 41 control the bus request valid instruction circuit 100. , the bus acknowledge gate (1) 21 connects the bus acknowledge signal control circuit 200 to the inverter 6.
1, AND gates 66 and 67, bus request valid indication shift gate (1) 31 connects the pass force valid indication shift path 300 to the bus request end indication flip-flop (
1) 81 constitutes the bus request end instruction circuit 400, and the AND gate 72 constitutes the bus request input control circuit 500.

Similarly, the bus use control circuit 602 includes AND gates 53, 54, 68, 69 and 73, an OR gate 58, an inverter 63, a bus request valid instruction flip-flop (2) 42, and a bus acknowledge gate (2). ) 22 and a bus request end instruction flip-flop 82, the bus use control circuit 603 includes AND gates 55, 56, 70, 71 and 74,
It is configured to include an OR gate 59, an inverter 65, a bus request valid instruction flip-flop (3) 43, a bus acknowledge gate (3) 23, and a bus request end instruction flip-flop 83. In addition, 44
．． 45 and 46 are clocks.

The feature of the present invention is that in FIG.
is configured as shown in the figure.

Next, the operation of this embodiment will be explained.

First, assume that in the initial state, the bus request valid instruction flip-flop (1) 41 is "1" and the bus request valid instruction flip-flops (2) 42 and (3) 43 are rOJ. If the bus request signal from each module is not set to "1", the output of the bus request valid instruction flip-flop (1) 41 is "1", so
The output of the bus request valid indication shift gate (1) 31 becomes rlJ and is sent to the next bus request valid indication flip-flop (3) 43. By the way, since the bus request (3) signal 12 is "0", the output of the OR gate 59 of the bus use control circuit 603 becomes rOJ,
Also, since the output of the AND gate 70 becomes "1", the output of the bus request valid indication shift gate (3) 33 is r
lJ, and is further sent to the bus request valid indication flip-flop (2) 42 of the next bus use control circuit 602. Again, the bus request signal (2) 11 is “
0'', the signal is further sent to the bus request valid instruction flip-flop (1) 41 of the next bus use control circuit 601. Here, since the bus request valid instruction flip-flop (1) 41 is set to "1", the AND gate 51 is set to "1" and the bus request valid instruction flip-flop (1) 41 is held. ``Next, consider the case where the bus request signal (2) 11 is set. Since the bus request signal (3) 12 is rOJ, as described above, the bus request valid indication flip-flop (3) 43 is bypassed and is sent to the bus request valid indication flip-flop (2) 42.

Here, since the bus request signal (2) 11 is "1", the output of the bus request valid indication shift gate (2) 32 is "0" and is not sent to the next time. Also, since the output of the AND gate 54 is "1", the clock 44.
When 45 and 46 are input, the bus request valid indication flip-flop (2) 42 is set to "1".
In addition, bus request valid indication flip-flop (1)
41 is reset. Here, the bus acknowledge signal (
2) 14 is set, giving module 2 the right to use the bus. Furthermore, bus request signal (2) 11
is reset, the bus acknowledge signal (2) 14
is reset and transmits a valid instruction to the bus request valid indicating flip-flop (1) 41 or (3) 43 to which the bus request is sent in the same procedure as above.

Next, bus request valid indication flip-flop (1)
41 is "1", and bus request valid indication flip-flop (2) 42 and 43 are "0". Here, when the bus request signals of all modules are set to rlJ, the output of the bus request valid instruction flip-flop 41 is "1", so the bus acknowledge signal (1) 13 is set and the module (4) 1 will be sent to. When the module (1) 1 transfers a certain amount of data, the bus acknowledge signal (1) 13 is reset and the bus request valid indication flip-flop (3) 43
The bus request valid instruction moves to . At this time, if the bus request signal (1) 10 is still set, the bus request end instruction flip-flop 81 is set. As a result, the input of the bus request signal (2) 11 is blocked by the AND gate 73. In this state, the bus request valid instruction flip-flop (3) 43 is set, so the bus acknowledge signal (3) 15 is set and sent to the module (3) 4, and the module (3) 43 is set.
3) Data transfer in step 3 is performed.

When the data transfer is completed, the bus acknowledge signal (3)
15 is reset, but since the bus request end instruction flip-flop 81 remains set, the bus acknowledge valid instruction bypasses the bus acknowledge valid instruction flip-flop (2) 42 and passes through the bus acknowledge valid instruction flip-flop (1) 41. Set. When the bus acknowledge valid instruction flip-flop (1) 41 is set, the bus acknowledge signal (1) 13 is set and the module (1) 2 transfers data in the same manner as described above.

In other words, in this case, even if module (1) 1 cannot transfer all the data in one use of the bus, it can use the bus once with another module and then use the bus again and transfer the remaining data. become.

Although the above embodiment deals with the case where the number of modules is n=3, the present invention can generally be applied to a plurality of n modules.

〔Effect of the invention〕

As explained above, with the above configuration, each module transfers bus use to another module after transferring a certain amount of data, and after transferring a certain amount of data, further bus requests are made. If not reset, after any one module uses the bus,
This allows the bus to be used, which has the effect of allowing processing to be performed without making the module wait for a long time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a block diagram showing a part of this embodiment. 1.2 and 3...modules (1), (2) and (3), 4...bus, 5...bus controller, 1
0.11 and 12... bus request signal (1),
(2), and (3), 21.22 and 23... Bus acknowledge gate (1), (2) and (3), 3
1.32 and 33...Bus request valid indication shift gates (1), (2) and (3), 41.42 and 43...Bus request request indication flip-flop (F/F) (1), ( 2) and (3), 44.45.
46...Clock, 51-56.66-74...And gate, 57-59...Or gate, 61.63
．． 65... Inverter, 8L 82.83... Bus request end instruction flip-flop, 100... Bus request valid instruction circuit, 200... Bus acknowledge signal control circuit, 300... Bus request valid instruction shift circuit, 400...Bus request end instruction circuit, 500...Bus request input control circuit, 601
．． 602 and 603... bus use control circuit (1),
(2) and (3).

Claims (2)

[Claims] (1) A plurality of n modules (1, 2, 3) each connected to one bus (4) and a bus acknowledge signal (13) in response to a bus request signal (10, 11, 12) from each module , 14, 15), wherein the bus controller (5) is provided for each of the modules and controls the use of the bus of its own module.
bus use control circuits (601, 602, 603), and each bus use control circuit has a bus request validity instruction circuit (100 ), a bus acknowledge signal control circuit (200) that controls the transmission of the bus acknowledge signal based on the output of the bus request valid indication circuit, and a bus acknowledge signal control circuit (200) that controls the transmission of the bus acknowledge signal when the bus acknowledge signal from the own module is not output. A bus request valid indication shift circuit (3
00), a bus request termination instruction circuit (400) that indicates that the bus request signal from the own module has been reset, and a bus request termination instruction circuit (400) corresponding to other modules that outputs the above bus request signal from the own module. a bus request input control circuit (500) that controls input to the bus request valid indication circuit, and the output of the bus request valid indication shift circuit is sequentially outputted to one of the bus request valid indication circuits of the bus use control circuits. A bus acquisition method, characterized in that the bus acquisition method is connected to two inputs and one input of a bus request valid indication shift circuit. (2) In the bus acquisition method, the bus request signal is logic “1”.
”, the bus is allowed to be used when the bus acknowledge signal is logic “1”, and the bus acknowledge control circuit is allowed to use the bus when the output of the bus request valid indication circuit is logic “1”. In this patent, the bus acknowledge control circuit is configured to set the bus acknowledge signal to logic "1" when the output of the bus request valid indication circuit is logic "1" and the bus request signal is logic "1". A bus acquisition method according to claim (1).