JP2828994B2 - Data transmission equipment - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data transmission apparatus, and in particular, serially transmits data transmitted via a plurality of parallel input-side transmission paths to an output-side transmission path. The present invention relates to an improvement of a data transmission device for transmitting data.

<Conventional technology> In a data processing device using a computer or the like,
A plurality of processing units are connected by digital signal communication. Then, when the data processing is distributed and processed by a plurality of processing devices, the result obtained by each processing device is sent to a second processing device different from these processing device groups,
The second processing device executes a process using the plurality of received results. For example, there is an apparatus disclosed in Japanese Patent Application No. 61-17543.

<Problems to be Solved by the Invention> In each of the above-described processing devices, the time required for processing the distributed data differs depending on the received data and the content of the processing required for the device, and each of the processing devices performs the processing. As a result, the data groups are not always transmitted in the same order and at the same time intervals. Further, if the transmission path itself can have a buffer function for minimizing the stagnation of the transmission data group caused by the variation of the processing time in the second processing device, the amount of birdware of the processing device can be reduced. it can.

Therefore, a main object of the present invention is to receive data transmitted via a plurality of parallel input-side transmission lines up to the limit of the capacity of the transmission line, and to output the data in the order of arrival of the transmission data group. An object of the present invention is to provide a data transmission device that transmits data to a transmission line on the side and arbitrates output when there is a stagnant transmission data group and can transmit the data to the transmission line on the output side.

<Means for Solving the Problems> A data transmission apparatus according to the present invention transmits continuous data to a plurality of parallel input-side transmission paths at an arbitrary time interval longer than a time interval unique to each transmission path. When inputting a data group to a plurality of parallel transmission paths, each data of the data group to each transmission path can be input at an arbitrary time difference equal to or more than a predetermined time difference. , And further, to the limit of the physical capacity of the transmission path. In addition, the data can be transmitted in series to the transmission line on the output side in the order of arrival of the data and when the data is accumulated, so as to minimize the accumulation. For this purpose, the data transmission device transmits the data in the order in which the data arrives and the data stays in the data transmission unit in response to the transmission permission signal being sent from the transmission line on the output side. In this case, arbitration is performed so as to reduce stagnation as much as possible, and arbitration control means for transmitting the arbitration serially to the transmission line on the output side.

<Operation> According to the data transmission apparatus of the present invention, in response to the transmission permission signal being transmitted from the transmission line on the output side, the data transmission order of the plurality of transmission main stages is determined. Arbitration so that the transmission capacity of the transmission line can be accepted up to the limit of the physical capacity of the transmission line, and there is no delay time required for arbitration control. Can be sequentially transmitted to the output side transmission path within the transfer time of

<Embodiment> FIG. 1 is a schematic block diagram of an embodiment of the present invention. In the embodiment shown in FIG. 1, two data transmission paths are used.
10, 20, 30 and 40, 50, 60 are provided in parallel, and the arbitration control unit 80 performs parallel operation in response to the transmission permission signal being transmitted from the data transmission line 100 which is the output side transmission line. The output order is arbitrated according to the degree of congestion of each data on the input side transmission line, and is output to the data transmission line 100.

Next, a specific operation of the embodiment shown in FIG. 1 will be described. In the initial state, the data transmission path on the output side
100 indicates a state in which data can be received, and the transmission permission signal A
K100 has been returned to the arbitration control unit 80. The arbitration control unit 80 transmits a transmission permission signal AK1 from the data transmission line 100 on the output side.
Upon receiving 00, the transmission permission signals AK and AK60 are output to the data transmission paths 30 and 60. The AK30 and the AK60 do not permit transmission to the data transmission path 100 at the same time, but allow one of them to transmit to the data transmission path 100. In the present embodiment, for example, it is assumed that the data transmission path 60 is permitted and the data transmission path 30 is prohibited.

When data arrives at the data transmission path 10, the data and the transmission signal C10 are transmitted to the data transmission path 30 via the data transmission path 20. The transmission permission signal AK10 is in a state where transmission is permitted until the data and the transmission signal C10 are transmitted to the data transmission path 10, but the data and transmission signal C1
When "0" is transmitted, the signal is output to the preceding stage as a signal for inhibiting input of the next data and transmission signal during data reception, that is, during reception. The transmission signal C10 is transmitted via the data transmission path 20,
Since the data is transmitted to the data transmission path 30, the data transmission path 30
Information that the data transmission path 20 and the arbitration control unit 80 are being received is output to the transmission permission signal. In the arbitration control unit 80,
Check that there is no data in the data transmission path 60, and if there is no data,
, And prohibits the data transmission path 60 from transmitting data to the data transmission path 100. The data transmission path 30 transmits data to the data transmission path 100 since transmission to the data transmission path 100 is permitted. When data passes through the data transmission line 100, a transmission permission signal AK100 is returned from the data transmission line 100 to the arbitration control unit 80, and the arbitration control unit 80 transmits the transmission permission signal to the data transmission line 30.
By returning AK30, transmission of data from data transmission path 30 to data transmission path 100 is permitted. After the data passes through the data transmission line 100, the transmission permission signal AK100 is output, and the data transmission from the data transmission line 30 to the data transmission line 100 is permitted. This is because, if data transmission from the data transmission unit 30 is permitted in a state where the data exists, the previous data is rewritten with the subsequent data, and the previous data is lost.

Next, when data arrives at the data transmission path 40, the data and the transmission signal C20 are transmitted to the data transmission path 60 via the data transmission path 50. Since the transmission signal C20 is transmitted to the data transmission path 60 via the data transmission path 50, the data transmission path 60 outputs, to the data transmission path 50 and the arbitration control unit 80, information indicating that the signal is being received as a transmission permission signal. I do. The arbitration control unit 80 confirms that there is no data on the data transmission path 30.If there is no data, the data transmission path 60 is allowed to transmit data to the data transmission path 100, and the data transmission path 30 On the other hand, data transmission to the data transmission path 100 is prohibited. Since transmission to the data transmission path 100 is permitted, the data transmission path 60 transmits data to the data transmission path 100. When data passes through the data transmission line 100, the transmission permission signal AK60 is returned from the data transmission line 100 to the data transmission line 60 via the arbitration control unit 80, and the data transmission line
Allow sending data from 60.

Next, a case where data 2 is input slightly later than data 1 will be described. When data arrives at the data transmission line 10, the transmission signal C10 is sent to the data transmission line 30 via the data transmission line 20, and the arbitration control unit 80 transmits the data to the data transmission line 100 to the data transmission line 100. Prohibit transmission. At this time, data arrives at the data transmission path 40, temporarily stops at the data transmission path 60 via the data transmission path 50, and when the data 1 passes through the data transmission path 30, the data arrives at the data transmission path 100 of the data transmission path 60. Is allowed to be sent. As described above, the arbitration control unit 80 suspends the data 1 and the data 2 whose arrival time is late in the data transmission path 30 or the data transmission path 60, and arbitrates the transmission paths.

FIG. 2 is a specific circuit diagram of an embodiment for arbitrating two independent data. First, the configuration will be described with reference to FIG. The data transmission lines 10, 20, 30 and
40, 50, 60 are transfer control units 11, 21, 31, and 41, 5, respectively.
1, 61 and data holding means 12, 22, 32 and 42, 52, 62. The data transmission path 100 includes a transfer control unit 101 and a data holding unit 102. Transfer control units 11, 21, 31,
Each of 41, 51, and 61 performs handshake transfer control with one transmission signal input, one transmission permission signal input, one transmission signal output, and one transmission permission signal output. The transfer control unit 101 has a function of performing a logical sum on two different transmission signal inputs, and performs the same handshake as the transfer control units 11, 21, 31, 41, 51, and 61 as transfer control. Perform transfer control. FIG. 3 shows a detailed circuit of the transfer control units 11, 21, 31, 41, 51, and 61, and FIG. 4 shows a detailed circuit of the transfer control unit 101. The arbitration control unit 80 includes NAND gates 81, 82, 83
, 84, AND gates 85 and 86, D-type flip-flops 87 and 88, and NOR gates 89 and 90.

Next, the operation of the embodiment shown in FIG. 2 will be described. In the initial state, a reset signal RESET (“L” level) is supplied to the transfer control units 11, 21, 31, 41, 51, 61 and 101, AND gates 85 and 86, and NAND gates 82 and 83. As a result, the transfer controllers 11, 21, 31, 41, 51, and 61 are each initially reset, and the respective Q1 outputs go to the “H” level, and the Q2 outputs also go to the “H” level. When the transfer control unit 101 is reset, the Q1 output goes to “H” level and the Q2 output goes to “L” level. The output of the NAND gate 82 becomes “H” by the reset signal, and is input to the NAND gate 81 constituting the flip-flop. The remaining input of the NAND gate 81 becomes “H” since the transfer control unit 31 is reset, the output of the NAND gate 81 becomes “L”, and the preceding flip-flop constituted by the NAND gates 81 and 82 is stabilized. The subsequent flip-flop constituted by the NAND gates 83 and 84 receives the output of the preceding stage and also receives the reset signal in the NAND gate 83, so that the output of the NAND gate 83 becomes “H” and the output of the NAND gate 84 becomes “L”. ", And the flip-flop at the subsequent stage is stabilized. Since the output of the NAND gate 83 is given to the input of the NOR gate 89, the output of the NOR gate 89 is “L”.
The data transmission from the transmission path 30 to the transmission path 100 is prohibited. Since the output of the NAND gate 84 is given to the input of the NOR gate 90, the output of the NOR gate 90 becomes “H”, enabling data transmission from the transmission path 60 to the transmission path 100.

In this state, when data 1 is supplied to the data holding unit 12 and the transmission signal C10 (“L” level) is supplied to the transfer control unit 11, the transfer control unit 11 sets the Q2 output of the transfer control unit 21 to “H”. Therefore, the Q1 output of the transfer control unit 11 is set to the “L” level, and the Q1 output of the transfer control unit 11 is transmitted to the transfer control unit 21 and becomes a clock pulse of the data holding unit 12 so that the contents of the data 1 are stored in the data holding unit 12. Output to Qi. Transfer control unit 21
Since the Q2 output of the transfer control unit 31 is “H”, the Q1 output is set to “L” level, the Q output of the transfer control unit 21 is transmitted to the transfer control unit 31, and the data holding unit 22 It becomes a clock pulse and outputs the contents of Qi of the data holding means 12 to Qi of the holding means 22. Further, the Q2 output of the transfer control unit 31 becomes an input of the NAND gate 81, and changes the output of the NAND gate 81 from “L” to “H”.
And 83 are input. The output of the NAND gate 82 becomes “L” when all the inputs become “H”, and the flip-flop in the preceding stage is stabilized. Also, NAND Gate 84
Is changed from “L” to “H”, and this output becomes the input of the NAND gate 83. The output of the NAND gate 83 becomes “L” because all the inputs have become “H”, and the flip-flop in the subsequent stage is stabilized. The output “L” of the NAND gate 83 becomes an input of the NOR gate 89, and when the transmission permission signal from the transfer control unit 101 is activated, the Q1 output of the transfer control unit 31 is set to “L” level and transmitted to the transfer control unit 101. When the transmission enable signal AK is “H”, the transfer control unit 101
The output becomes “L” and becomes a clock pulse of the data holding means 102, and the contents of Di of the data holding means 102 are output to Qi. During the period when the output is transferred from the transfer control unit 31 to the transfer control unit 101, the output “H” of the NAND gate 84 is held as the flip-flop output of the subsequent stage and is input to the NOR gate 90, so the output of the NOR gate 90 is “L”. And the output from the transfer control unit 61 to the transfer control unit 101 is inhibited, and the D-type flip-flop 88
Is set to “L”, the output Qi of the data holding means 62 is set to high impedance,
Try not to collide with the output.

Next, when the data 2 is provided to the data holding unit 42 and the transmission signal C20 is provided to the transfer control unit 41, the operation is completely the same as that described above for the input of the data 1, so that the description is omitted.

Next, a case will be described in which data 2 is input at a certain time difference from data 1 after the initial state.
Data 1 is provided to the data holding means 12, and the transmission signal C10
Is given to the transfer control unit 11, and the data 2 inputted with a slight delay is given to the data holding means 42, and the transmission signal C20
Is provided to the transfer control unit 41, the transmission signal C10 is provided to the transfer control unit 31 via the transfer control units 11 and 12. The Q2 output of the transfer control unit 31 is input to the NAND gate 81, and the output is changed from “L” to “H” to stabilize the flip-flop constituted by the NAND gates 81 and 82. The output of the NAND gate 82 is
By changing the output of the NAND gate 84 from “L” to “H”, the flip-flop constituted by the NAND gates 83 and 84 is stabilized. Nand gate
The output of 83 is given to the NOR gate 89, and the transmission of the transfer control unit 31 to the transfer control unit 101 is permitted. At this time, the output of the NAND gate 84 is given to the NOR gate 90, and the transfer control unit
The transmission of the transmission control unit 31 is prohibited.
Is transmitted to the transfer control unit 101, the transmission of the transfer control unit 61 is permitted. The case where the data 1 is input slightly later than the data 2 can be completely described in the same manner, so that the description is omitted.
As described above, when data 1 and data 2 are input in conflict, the data input late by the flip-flops of NAND gates 81 and 82 and the flip-flops of NAND gates 83 and 84 are temporarily stopped.

As described above, according to this embodiment, the transmission line 10 on the output side is used.
In the state where 0 is empty, only data 1 exists,
When data 2 does not exist, data 1 is sequentially output. When only data 2 exists, when data 1 does not exist, data 2 is sequentially output. When data 1 and data 2 are transmitted at the maximum transfer capacity of the data transmission line, the data transmission line 100 cannot process the data.
Data stays in the data transmission lines 30, 20, and 10 and the data transmission lines 60, 50, and 40. In this case, the data transmission path
30 and the data transmission path 60 alternately transmit data on each transmission path to the data transmission path 100.

FIG. 5 is a specific circuit diagram of another embodiment for arbitrating two independent data. First, the configuration will be described with reference to FIG. The data transmission lines 10, 20, 30 and 40, 50, 60 in FIG.
41, 51, 61 and data holding means 12, 22, 32, and 42, 52, 62. The data transmission path 100 is connected to the transfer control unit 1
01 and data holding means 102. Transfer control unit 11,
21, 31, 41, 51 and 61 each have one transmission signal input,
One transmission enable signal input, one transmission signal output, and one
Handshake transfer control is performed by the output of the transmission permission signal. The transfer control unit 101 has a function of performing a logical sum on two different transmission signal inputs, and performs the same handshake as the transfer control units 11, 21, 31, 41, 51, and 61 as transfer control. Perform control. FIG. 6 shows a detailed circuit of the transfer control units 11, 21, 31, 41, 51 and 61, and FIG. 7 shows a detailed circuit of the transfer control unit 101. The arbitration controller 80 includes a D-type flip-flop 81 ', NOR gates 82', 85 'and 86', NAND gates 89 'and 90', and inverters 83 ', 84' and 8 '.
7 'and 88'.

Next, the operation of the embodiment shown in FIG. 5 will be described. In the initial state, a reset signal RESET (“L” level) is provided to the transfer control units 11, 21, 31, 41, 51, 61, and 101. As a result, the transfer control units 11, 21, 31, 41, 51, 61 and 101 are respectively initially reset, and the respective Q1
The output goes high, and the Q2 output goes high.
As a result, the outputs of inverters 83 'and 84' attain "L" level, and the output of NOR gate 82 'attains "L" level. Therefore, the set input of the D-type flip-flop 81 'is at "L" level, the reset input is also at "L" level,
Q output of type flip-flop 81 "is at" H "level,
The output becomes “L” level. Also, since the reset signal is given to the NAND gate 89 ', the output of the NAND gate 89' goes to "H" level, and the output of the NAND gate 90 'goes to "L" level. Q of D type flip-flop 81 '
Since the output is given to the input of NOR gate 86 ',
The output of NOR gate 86 'becomes "L" level, and data transmission from transmission line 60 to transmission line 100 is disabled. Since the output of the D-type flip-flop 81 'is given to the input of the NOR gate 85', the output of the NOR gate 85 'becomes "H" level, enabling data transmission from the transmission line 30 to the transmission line 100.

In this state, when the data 1 is provided to the data holding unit 12 and the transmission signal C10 is provided to the transfer control unit 11,
Since the Q2 output of the transfer control unit 21 is at “H” level, the transfer control unit 11 sets the Q1 output to “L” level,
The output of Q1 is transmitted to the transfer control unit 21 and becomes a clock pulse of the data holding means 12 to output the contents of the data 1 to Qi of the data holding means 12. The transfer control unit 21 is a transfer control unit
31 Q2 output is “H” level, so its Q1 output is “L”
Level, the Q1 output of the transfer control unit 21 is transmitted to the transfer control unit 31 and becomes the clock pulse of the data holding unit 22 and the content of Qi of the data holding unit 12 is
Output to Qi. Further, the Q2 output of the transfer control unit 31 becomes the input of the inverter 84 ', and changes the output of the inverter 84' from "L" level to "H" level.
In the initial state, the Q2 output of the transfer control unit 61 is at the "H" level, the reset input of the D-type flip-flop 81 'remains at the "L" level, and the set input is also at the "L" level. It does not change from the initial state as it is. Therefore, while the D-type flip-flop 81 'remains set, the Q output is at the "H" level, the output is at the "L" level, the Q output is applied to the input of the NOR gate 86', and the output of the NOR gate 86 'is "L". "
The level and the output are given to the input of the NOR gate 85 ', and the output of the NOR gate 85' is at the "H" level, so that the data transmission from the transmission line 60 to the transmission line 100 is prohibited. Enables transmission. That is, since the transmission permission signal from the transfer control unit 101 is active, the Q1 output of the transfer control unit 31 is set to “L” level, transmitted to the transfer control unit 101, and the transmission permission signal AK is set to “H”.
In the case of the level, the Q1 output of the transfer control unit 101 becomes "L" level and becomes a clock pulse of the data holding means 102, and the contents of Di of the data holding means 102 are output to Qi. When a transmission signal is output from the transfer control unit 31 to the transfer control unit 101, the Q1 output of the transfer control unit 31 is set to "L" level and is simultaneously input to the NAND gate 89 '.
Since the output of 9 'is held at the "H" level and the output of the NAND gate 90' is held at the "L" level, the output Qi of the data holding means 62 is set to high impedance,
It does not conflict with Qi output. The initial state is maintained even after the data transmission from the transmission path 30 to the transmission path 100 is completed.

Next, when the data 2 is provided to the data holding unit 42 and the transmission signal C20 is provided to the transfer control unit 41, the transfer control unit 41
Since the Q2 output of the transfer control unit 51 is “H”, the Q1 output is set to “L” level, and the Q1 output of the transfer control unit 41 is
The data is transmitted to 51 and becomes a clock pulse of the data holding means 42 to output the contents of the data 2 to Qi of the data holding means 42. Since the Q2 output of the transfer control unit 61 is “H”, the transfer control unit 51 sets the Q1 output to “L” level,
Is transmitted to the transfer control unit 61 and becomes a clock pulse of the data holding means 52.
Is output to Qi of the data holding means 52. Also, the Q2 output of the transfer control unit 61, the inverter 83 'and the NOR gate 82'
To change the output of the inverter 83 'from "L" level to "H" level and the output of the NOR gate 82' from "L" level to "H" level. As a result, the set input of the D-type flip-flop 81 'is at "H" level, the reset input is also at "H" level, and the D-type flip-flop 81'
Are reset, the Q output becomes "L" level, and the output becomes "H" level. Since the Q output of the D-type flip-flop 81 'is given to the input of the NOR gate 86', the output of the NOR gate 86 'goes to "H" level, enabling data transmission from the transmission line 60 to the transmission line 100. Since the output of the D-type flip-flop 81 'is given to the input of the NOR gate 85', the output of the NOR gate 85 'becomes "L" level, and the data transmission from the transmission line 30 to the transmission line 100 is disabled. In other words, the output of NOR gate 86 'is
When the transmission permission signal from the transmission control unit 101 is activated, the Q1 output of the transfer control unit 61 is set to the “L” level and transmitted to the transfer control unit 101. When the transmission permission signal AK is at the “H” level, The Q1 output becomes “L” level and becomes a clock pulse of the data holding means 102, and the data holding means 1
The contents of Di of 02 are output to Qi. When a transmission signal is output from the transfer control unit 61 to the transfer control unit 101, Q1 of the transfer control unit 61
The output is set to the "L" level, and is simultaneously input to the NAND gate 90 '. The output of the NAND gate 90' is set to the "H" level, the output of the NAND gate 89 'is set to the "L" level, and this state is maintained. As a result, the output Qi of the data holding means 32 is set to a high impedance so as not to collide with the Qi output of the data holding means 62. After the data transmission from the transmission line 60 to the transmission line 100 is completed, the latch composed of the NAND gates 89 'and 90' holds the state until the next transmission signal is input. Control units 31 and 61
Are set to the initial state again.

Next, a case where the data 2 after the initial state is input with a certain time difference from the data 1 will be described. After the data 1 is provided to the data holding unit 12 and the transmission signal C10 is provided to the transfer control unit 11, the data 2 input with a slight delay is provided to the data holding unit 42, and the transmission signal C20 is provided to the transfer control unit 41. , The transmission signal C10 and the data 1 are transmitted to the transfer control units 11 and 21 and the data holding unit.
The data is supplied to the transfer control unit 31 and the data holding unit 32 via 12 and 22. Further, the Q2 output of the transfer control unit 31 becomes the input of the inverter 84 ', and the output of the inverter 84' is set to "L".
The level is changed from the “H” level to the “H” level, and this output becomes the input of the NOR gate 82 ′.
When the output is "H" level, the D-type flip-flop 81 '
Reset input remains at “L” level and set input is also “L”
The level remains unchanged from the initial state. Further, the data 2 input with a slight delay is supplied to the data holding unit 42, and the transmission signal C20 is supplied to the transfer control unit 41, and the transmission signal C20 and the data 2 are transmitted to the transfer control units 41 and 51 and the data holding unit 42 And 52, to the transfer control section 61 and the data holding means 62. The Q2 output of the transfer control unit 61 becomes the input of the inverter 83 ', changes the output of the inverter 83' from the "L" level to the "H" level, and becomes the input of the NOR gate 82 '. The output of the inverter 84 'is changed to "H" level by the Q2 output of the section 31, and the output of the NOR gate 82' is continuously at "L" level from the initial state. Therefore, the reset input of the D-type flip-flop 81 'remains at the "L" level and the set input becomes "H".
The level is reached, and the state is held. The Q output of the D-type flip-flop 81 'is held at "H" level and the output is held at "L" level. These outputs are supplied to NOR gates 86' and 85 '. Transmission is permitted and transmission of the transfer control unit 61 is prohibited, and transmission of the transmission signal C10 and data 1 from the transfer control unit 31 and the data holding unit 32 to the transfer control unit 101 and the data holding unit 102 is completed. Held until When the transfer from the transfer control unit 31 and the data holding unit 32 to the transfer control unit 101 and the data holding unit 102 is completed, the Q2 output of the transfer control unit 31 becomes “H” level, and the D-type flip-flop 81 ′ Is set to "H" level, the reset input is also set to "H" level, the D-type flip-flop 81 'is reset, and the transmission of the transfer control unit 61 is permitted. The case where the data 1 is input slightly later than the data 2 can be completely described in the same manner, so that the description is omitted. As described above, when data 1 and data 2 are input in conflict, the D-type flip-flop 81 'and the D-type flip-flop 8
The Q2 output of the transfer control unit 101 serving as a clock input to the NOR gate 82 ', the inverters 83', 84 ', and the D-type flip-flop 81', which determines the input to 1 ',
Pause late input data.

As described above, according to this embodiment, the transmission path on the output side
In a state where 100 is empty, when only data 1 exists and data 2 does not exist, data 1 is sequentially output. When only data 2 exists and data 1 does not exist, data 2 is sequentially output. You. Further, when data 1 and data 2 are transmitted at the maximum transfer capacity of the data transmission path, the data transfer path 100 cannot process the data.
Data stays in the data transmission lines 30, 20, and 10 and the data transmission lines 60, 50, and 40. In this case, the data transmission path
30 and the data transmission path 60 alternately transmit data on each transmission path to the data transmission path 100.

<Effects of the Invention> As described above, according to the present invention, even when data of a plurality of parallel transmission lines are transmitted at arbitrary time intervals and asynchronously with each other, the data is transmitted from the data transmission line on the output side. Arbitration is performed by the arbitration control unit in response to the permission signal being sent, so that the transmission capacity is accepted to the limit of the physical capacity of the transmission line, and the delay time required for the arbitration control is completely eliminated and the output side transmission line has no delay. They can be transmitted sequentially. Therefore, a highly reliable arbitration mechanism can be realized together with high-speed transmission.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of one embodiment of the present invention.
FIG. 2 is a detailed circuit diagram of an example of transmitting data sent from two data transmission paths to a data transmission path on the output side. FIGS. 3 and 4 are circuit diagrams of one embodiment of the transfer control unit. FIG. 5 is a detailed circuit diagram of another example for transmitting data sent from two data transmission lines to a data transmission line on the output side. 6 and 7 are circuit diagrams of one embodiment of the transfer control section. In the figure, 10, 20, 30, 40, 50, 60, and 100 are data transmission paths and 8
0 is an arbitration control unit, 11, 21, 31, 41, 51, 61, and 101 are transfer control units,
12,22,32,42,52,62,102 are data holding means, 87,88 are D-type flip-flops, 85,86 are AND gates, 81,82,8
3,84 are NAND gates, 89,90 are NOR gates, 81 'is a D type flip-flop, 82', 85 ', 86' are NOR gates,
83 ', 84', 87 ', 88' indicate inverters, and 89 ', 90' indicate NAND gates.

 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Soichi Miyata 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (56) References JP-A-62-23253 (JP, A) JP-A-62 -174856 (JP, A) JP-A-59-501038 (JP, A) JP-A-61-140253 (JP, A) JP-A-61-10348 (JP, A) JP-A-61-202546 (JP, A) ) JP-A-58-170155 (JP, A)

Claims (1)

(57) [Claims] 1. Data transmission for serially transmitting a plurality of data transferred via a plurality of parallel input transmission lines equivalent to each other with respect to data transmission to an output transmission line to an output transmission line. A cascade connection of a plurality of data transmission lines each comprising a transfer control unit and data holding means for controlling data transfer according to a transfer control signal from the transfer control unit. Based on the transfer control signal from the transfer control unit of the data transmission line at the last stage of each of the input-side transmission lines and the transmission permission signal from the output-side transmission line. An arbitration control unit configured to output a transmission permission signal to a transfer control unit of a data transmission line, wherein the arbitration control unit transmits data to the output-side transmission line in the order of arrival, and outputs any one of the plurality of parallel input-side transmission lines. Two sets of When the residence of data occurs in the sending passage, the data transmission apparatus comprising the arbitration control means for alternately transmitted data of said two sets of transmission lines to the output side transmission line.