JP3113355B2 - Data transmission equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission apparatus, and more particularly to a data transmission apparatus for transmitting data transmitted via a plurality of parallel input transmission lines to an output transmission line in series. Regarding improvement.

[0002]

2. Description of the Related Art In a data processing apparatus using an electronic computer or the like, a plurality of processing apparatuses are connected by digital signal communication. When the data is distributed and processed by a plurality of processing devices, the result obtained by each processing device is sent to a second processing device different from the processing device group, and the second processing device receives the data. The process is executed using the plurality of results. An example of such a data transmission device is disclosed in Japanese Patent Application Laid-Open No. Sho 62-17486. Further, as another example of the data transmission device, Japanese Patent Laid-Open No.
There is one disclosed in Japanese Patent Publication No. -108660. The data transmission device described in Japanese Patent Application Laid-Open No. Sho 62-174856 has an arbitration function of determining which data is to be transmitted if a time difference is within a certain time when two sets of data are input simultaneously. Not. On the other hand, JP-A-1-108
In the data transmission device described in Japanese Patent Application Laid-Open No. 660, if the arrival time difference between two sets of data is within a certain range, the data having the late arrival arrives outside the range of the certain time difference for time adjustment. It is temporarily stopped on the transmission line,
If two sets of data are input simultaneously, the arbitration function will not work.

[0003]

SUMMARY OF THE INVENTION The above-mentioned JP-A-62-1
In the data transmission device described in Japanese Patent No. 74856, the time required to process the distributed data differs depending on the received data and the contents of the processing required for the device. Are not always sent in the same order and at the same time intervals. Further, if the transmission path itself can have a buffer function for minimizing the stagnation of the transmission data group caused by the variation of the processing time in the second processing device, the amount of hardware of the processing device can be reduced. it can.

Therefore, a main object of the present invention is to receive data transmitted through a plurality of parallel input-side transmission lines up to the limit of the capacity of the transmission line, and furthermore, to receive a transmission data group. An object of the present invention is to provide a data transmission device that transmits data to an output-side transmission line in order, arbitrates the output when a transmission data group remains, and transmits the data to the output-side transmission line.

[0005]

A data transmission device according to the present invention is provided.
Is connected via first and second parallel input transmission lines.
Multiple transmitted at arbitrary time intervals and asynchronously with each other
A transmission permission signal is sent from the transmission line on the output side.
Transmission to the output side transmission line in series.
A data transmission device for transmitting the first and second data.
Each stage of the transmission line on the input side of the
And a transfer holding unit, wherein the transfer control unit includes:
The transmission signal from the control unit and the transmission
Outputs a transmission signal to the subsequent transfer control unit in response to the enable signal
Output a transmission permission signal to the transfer control unit in the previous stage.
The data holding circuit stores the data of the preceding stage.
Receives the data output from the holding circuit and holds it
And output from the transfer control unit of the stage.
In accordance with the transmission signal, the held data is
And outputs the signals to the first and second parallel circuits.
If two sets of data exist on the input transmission line in a row and the two sets
If the difference between the arrival times of the
Stop the slower arrival data on the corresponding transmission path, and
When data arrives at the same time, only one data
Transmit on the corresponding transmission path and transmit the other data
A conflict detection means for stopping on a road, wherein the first input
The transmission signal to the transfer control unit at the predetermined stage of the
A lock input, and a predetermined stage of the second input-side transmission path
A transmission signal to the transmission control unit is used as a data input of the first signal.
A D-type flip-flop and the first D-type flip-flop
Output signal from the first input side transmission line
The transfer control unit of the next stage after the predetermined stage transmits the transfer control of the predetermined stage.
A first logic for controlling transmission of the transmission permission signal to the control unit
Gate and transfer control at a predetermined stage of the second input-side transmission path
The signal to be transmitted to the first section is used as its clock input, and the first
A transmission signal to a transfer control unit at a predetermined stage on the input side transmission line is transmitted to the transmission control unit.
A second D-type flip-flop as a data input of
By the output signal from the second D-type flip-flop,
Transfer control of the next stage of the predetermined stage of the second input side transmission line
From the transmission permission signal to the transfer control unit of the predetermined stage
A second logic gate for controlling transmission, and the first D-type
Output signal from flip-flop and second D-type flip-flop
And an output signal from the drop to the input of that, the output signal
However, in both cases, the transmission permission signal in the logic gate is
When the transmission is at a level that prevents transmission, the first and second
Logic gate on a predetermined side of the two logic gates
Signal that permits transmission of the above-mentioned transmission permission signal only to the
A logic circuit for outputting a signal,
Check that the transmission permission signal is sent from the output side transmission path.
Corresponding to the first and second input-side transmission lines
Depending on the degree of data congestion, output from each input side transmission line
Arbitration control means to arbitrate the order of data output to the
It is configured with.

[0006]

In the data transmission apparatus according to the present invention, in response to the transmission permission signal being transmitted from the transmission line on the output side, the order of arrival of data and the data stagnated on the plurality of transmission lines having the conflict detection function. In such a case, arbitration is performed to minimize the stagnation, and when two sets of data arrive at the same time,
By transmitting only one data and stopping the transmission of the other data, the data transmitted from the corresponding transmission path is received up to the limit of the physical capacity of the transmission path and required for arbitration control. There is no delay time, and the data can be sequentially transferred to the output side transmission line within the transmission time inherent in the transmission line.

[0007]

FIG. 1 is a schematic block diagram of an embodiment of the present invention. Referring to FIG. 1, two data transmission paths 10, 2
0, 30 and 40, 50, 60 are provided in parallel to detect whether or not the arrival time difference between data 1 and data 2 as inputs to the data transmission lines 10 and 40 is within a certain time difference range. Therefore, a conflict detection unit 70 is provided. The conflict detection unit 70 does not adjust the time if the arrival time difference between the data 1 and the data 2 is out of the range of the fixed time difference, and adjusts the time if the arrival time difference is within the range of the fixed time difference. The data transmission path 20 or 50 is temporarily stopped until the difference falls outside the range of the predetermined time difference.

The arbitration control unit 80 responds to the transmission permission signal AK100 sent from the data transmission line 100, which is the output transmission line, in response to the parallel input transmission lines 10, 20,.
The output order is arbitrated according to the degree of congestion of each of the data 30, 40, 50, and 60, and output to the data transmission path 100.

Next, a specific operation of the embodiment shown in FIG. 1 will be described. In the initial state, the data transmission path 100 on the output side is in a state where data can be received.
The ck signal AK100 is returned to the arbitration control unit 80. The arbitration control unit 80 controls the data transmission path 100 on the output side.
Receiving the Ack signal AK100 from the
And 60 output Ack signals AK30 and AK60. The Ack signals AK30 and AK60 do not permit transmission to the data transmission path 100 at the same time, but allow one of them to transmit to the data transmission path 100. In this embodiment, it is assumed that the data transmission path 60 is permitted and the data transmission path 30 is prohibited. When data arrives at the data transmission line 10, the data and the transmission signal c 10 are transmitted to the data transmission line 2.
The transmission signal c10 is also transmitted to the arbitration control unit 80 while being transmitted to the data transmission line 30 via the data transmission line 0. The arbitration control unit 80 confirms that there is no data in the data transmission path 60, and if there is no data, permits the data transmission path 30 to transmit data to the data transmission path 100,
Data transmission to the data transmission path 100 is prohibited for the data transmission path 60.

The data transmission path 30 is a data transmission path 100
Is transmitted to the data transmission line 100 because the transmission to the data transmission line 100 is permitted. When data passes through the data transmission line 100, an Ack signal AK30 is returned from the data transmission line 100 to the data transmission line 30 via the arbitration control unit 80, and data transmission from the data transmission line 30 to the data transmission line 100 is performed. Allow Next, when data arrives at the data transmission path 40, the data and the transmission signal c20 are transmitted to the data transmission path 60 via the data transmission path 50, and the transmission signal c20 is also transmitted to the arbitration control unit 80. You. The arbitration control unit 80 confirms that there is no data on the data transmission path 30, and if there is no data, the data transmission path 6
0 is permitted to transmit data to the data transmission path 100, and the data transmission path 30 is transmitted to the data transmission path 1
Data transmission to 00 is prohibited. Since the transmission to the data transmission line 100 is permitted, the data transmission line 60 transmits the data to the data transmission line 100. And data transmission path 1
When the data has passed through 00, an Ack signal AK60 is returned from the data transmission line 100 to the data transmission line 60 via the arbitration control unit 80, and the transmission of data from the data transmission line 60 is permitted.

Next, a case where data 2 is input later than data 1 will be described. When data arrives at the data transmission path 10, the transmission signal c10 is sent to the data transmission path 20 and also to the competition detection unit 70, and the competition detection unit 70 sends the data to the data transmission path 40 within a certain time difference. If data exists, data 2 is temporarily stopped on data transmission path 50, and when data 1 passes through data transmission path 20, data 2 stopped on data transmission path 50 starts to move. As described above, the conflict detection unit 70 detects the conflict between the data 1 and the data 2, temporarily suspends the data having a late arrival time on the data transmission path 20 or the data transmission path 50, and prevents the arbitration control unit 80 from malfunctioning. To prevent.

FIG. 2 is a more specific block diagram of an embodiment of the present invention, and FIG. 3 is a block diagram showing the transfer control unit 11 shown in FIG.
FIG. 4 is a specific block diagram of the transfer control unit 101 shown in FIG.

First, a specific configuration of an embodiment of the present invention will be described with reference to FIGS. Figure 1 above
The data transmission lines 10, 20, 30, 40, 50 and 60 shown in FIG.
1, 51, 61 and data holding circuits 12, 22, 32, 4
2, 52, and 62. Transfer control unit 1
Reference numerals 1, 21, 31, 41, 51, and 61 perform handshake transfer control with one transmission signal input, one transmission permission signal input, one transmission signal output, and one transmission permission signal output, respectively. Further, the transfer control unit 101 has a function of calculating the logical sum of two different transmission signal inputs, and the transfer control units 11, 21, 3
The same handshake control as in 1, 41, 51 and 61 is performed. More specifically, transfer control unit 11 includes 2-input NAND gates 111 and 115, 3-input NAND gate 112, and inverters 113 and 115 as shown in FIG. , 51,61
Is configured in the same manner as the transfer control unit 11. As shown in FIG. 4, the transfer control unit 101 includes a two-input NAND gate 12
4 and 3 input NAND gates 121 and 122 and an inverter 123 are included.

As shown in FIG. 2, the conflict detection unit 70 includes D-type flip-flops 71 and 72 and AND gates 73 and 72.
74, 75, 76, NOR gate 77, driver 7
8 and an OR gate 79. The arbitration control unit 80
ND gates 81, 82, 83, 84 and AND gate 8
5,86 and D-type flip-flops 87,88 and NO
R gates 89 and 90 are included.

Next, the operation of the embodiment shown in FIG. 2 will be described. In the initial state, the reset signal transfer control unit 11,21,31,41,51,61 and 101 and the AND gate 7 3, 7 4, provided to the 85, 86 and NAND gate 82 and 83. As a result, the transfer controllers 11, 21, 31, 41, 51, and 61 are each initially reset, and the respective Q1 outputs go to the “H” level, and the Q2 outputs also go to the “H” level. Transfer control unit 10
When 1 is reset, its Q1 output goes to "H" level and its Q2 output goes to "L" level. The output of the NAND gate 82 becomes “H” level by the reset signal, and is input to the NAND gate 81 forming the flip-flop. The remaining inputs of the NAND gate 81 all become “H” level because the transfer control units 21, 31, 51, 61 are reset, and the NAND gate 81
Is at "L" level, and NAND gates 81 and 8
The preceding flip-flop composed of 2 is stable.

The subsequent flip-flop constituted by NAND gates 83 and 84 receives the output of the preceding flip-flop and receives a reset signal in NAND gate 83, so that the output of NAND gate 83 goes to "H" level. , the output of NAND gate 8 4 becomes "L" level, is stabilized subsequent flip-flops. Since the output of the NAND gate 83 is given to the input of the NOR gate 89, the output of the NOR gate 89 becomes "L" level and the data transmission to the data transmission line 100 is disabled. The output of NAND gate 80 is NO
By being applied to the input of R gate 90, the output of NOR gate 90 attains "H" level, and data transmission path 1
Enable data transmission to 00.

[0017] A ND gate 73 output by the reset signal is input becomes the "L" level, D-type flip-flop 71 is set, its Q output is "H"
Level, the output of the OR gate 79 also becomes "H" level, and the output of the AND gate 75 becomes "H" level.

In this state, data 1 is supplied to data holding circuit 12, and pulse signal c10 is transmitted to transfer control unit 1.
1, the transfer control unit 11 outputs the AND gate 75 because the Q2 output of the transfer control unit 21 is at the “H” level.
Is at "H" level, and its Q1 output is at "L" level. The Q1 output of the transfer control unit 11 is
1 and becomes a clock pulse of the data holding circuit 12, and the content of the data 1 is
Is output to Qi of The transfer control unit 21 is a transfer control unit 31
Since the Q2 output of the transfer control section 21 is at the "H" level, the Q1 output of the transfer control section 21 is set to the "L" level, and the Q1 output of the transfer The contents of Qi of the holding circuit 12 are output to Qi of the data holding circuit 22.

The Q1 output of the transfer control unit 21 and the Q2 output of the transfer control unit 31 are input to the NAND gate 81, and the output of the NAND gate 81 is changed from " L " level to " H " level. NAND gate 8
2 and 83 are input. NAND gate 82 by the input goes to all "H" level, and its output is "L" level, to stabilize the preceding flip-flop. Further, the output of NAND gate 8 4 is changed to "H" level from the "L" level, the output is the input of the NAND gate 8 3. NAND gate 8 3 in its entirety
By input is "H" level, the output thereof becomes "L" level, to stabilize the subsequent flip-flops.

The "L" level signal output from the NAND gate 83 is input to the NOR gate 89, and the Q1 output of the transfer control unit 31 is set to "L" by activating the transmission permission signal from the transfer control unit 101. Level
The information is transmitted to the transfer control unit 101. When the transmission permission signal AK is at "H" level, the output of Q1 of the transfer control unit 101 becomes "L" level, the clock pulse of the data holding circuit 102, and the content of Di of the data holding circuit 102 is output to Qi. You. During the period when the data is output from the transfer control unit 31 to the transfer control unit 101, the NAND gate 84
Is held as a flip-flop output of the subsequent stage and input to the NOR gate 90, so that the output of the NOR gate 90 holds the "L" level,
By detecting the output from the transfer control unit 61 to the transfer control unit 101 and setting the Q output of the D-type flip-flop 88 to the “L” level by the output of the transfer control unit 31, the Qi of the output of the data holding circuit 62 is Is set to high impedance so as not to collide with the Qi output of the data holding circuit 32.

Next, when the data 2 is supplied to the data holding circuit 42 and the pulse signal c20 is supplied to the transfer control unit 41, the operation is completely the same as that described above with respect to the input of the data 1, so that the description is omitted. .

Next, after the initial state, data 2 becomes data 1
A case will be described in which the input is made slightly later than the input.
The data 1 is supplied to the data holding circuit 12, the pulse signal c10 is supplied to the transfer control unit 11, and the clock input terminal of the D-type flip-flop 71 and the D input terminal of the D-type flip-flop 72. The data 2 input slightly later than the data 1 is supplied to the data holding circuit 42 until the pulse signal c10 returns from the “L” level to the “H” level again. When the pulse signal c20 is given to the transfer control unit 41, the D input of the D-type flip-flop 72 is at the "L" level, so that when the pulse signal c10 returns from the "L" level to "H" again, Q
The output becomes “L” level, the output of the AND gate 76 also becomes “L” level, and the pulse transmitted to the transfer control unit 41 is not sent to the transfer control unit 51 but is stopped by the transfer control unit 41.

The Q1 output of the transfer control unit 11 is
1, the output of the AND gate 74 becomes "L" level, the Q output of the D-type flip-flop 72 is set, and the pulse stopped by the transfer control unit 41 is permitted to transfer again, and the transfer control unit 51 Is forwarded to The operation when the data 1 is input slightly later than the data 2 is the same, and the description is omitted.

When data 1 and data 2 are input at exactly the same time, the Q outputs of D-type flip-flops 71 and 72 are both at "L" level, and
Since the output of the D gate 76 is at "L" level, the data transmitted to the transfer control unit 41 is prohibited, and the output of the NOR gate 77 is at "H" level.
9, the output of the AND gate 75 also becomes "H" level, so that the data transmitted to the transfer control unit 11 is permitted. Subsequent operations are the same as when the two data inputs are shifted. When data 1 and data 2 are input in conflict as described above, NA
Flip-flops of ND gates 81 and 82 and N
The data input late by the flip-flops of the AND gates 83 and 84 is temporarily stopped.

As described above, according to this embodiment, when only the data 1 exists and the data 2 does not exist in the state where the data transmission path 100 on the output side is open, the data 1 is sequentially output, and Only 2 exists and data 1
Is not present, data 2 is sequentially output. Also,
When the data 1 and the data 2 are transmitted at the maximum transfer capacity of the data transmission line, the data transmission line 100 cannot be processed, so that the data transmission lines 30, 20, and 10 and the data transmission lines 60, 50, and 40 are not processed. Data stays in In this case, the data transmission path 30 and the data transmission path 60 alternately transmit data on each transmission path to the data transmission path 100.
To be transmitted.

[0026]

As described above, according to the present invention, even when the data of a plurality of parallel transmission lines are transmitted at arbitrary time intervals and asynchronously with each other, the data is transmitted to the plurality of parallel transmission lines. Arriving at the same time, the arbitration control means performs arbitration in response to the transmission permission signal sent from the data transmission line on the output side, thereby receiving data up to the limit of the physical capacity of the transmission line. In addition, there is no delay time required for the arbitration control, and the signals can be sequentially transmitted to the output side transmission path. Therefore, a highly reliable arbitration mechanism can be realized together with high-speed transmission.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of one embodiment of the present invention.

FIG. 2 is a specific block diagram of one embodiment of the present invention.

FIG. 3 is a specific block diagram of a transfer control unit 11 shown in FIG.

FIG. 4 is a specific block diagram of a transfer control unit 101 shown in FIG.

[Explanation of symbols]

 10 to 60, 100 Data transmission path 11 to 61, 101 Transfer control unit 12 to 62, 102 Data holding circuit 70 Conflict detection unit 80 Arbitration control unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 13 / 36,13 / 362,13 / 38 G06F 13 / 42,15 / 16

Claims (1)

(57) [Claims] A first and a second parallel input-side transmission line are provided.
Transmitted at arbitrary time intervals and asynchronously with each other
A transmission permission signal is sent from the transmission line on the output side
Is sent in series to the output side transmission line.
A data transmission device for transmitting data to each of the first and second input-side transmission lines.
And a transfer control unit and a data holding circuit.
The control unit transmits the transmission signal from the transfer control unit in the preceding stage and the transfer signal in the subsequent stage.
In response to the transmission permission signal from the transmission control unit,
The transmission signal is output to the
The transmission permission signal is output to the
The circuit uses the data output from the previous data holding circuit
Receiving and holding this, and the transfer
In accordance with the transmission signal output from the control unit,
Data is output to a data holding circuit in the subsequent stage, and two sets of data are provided on the first and second parallel input-side transmission paths.
Data exists and the arrival time difference between the two sets of data is constant
If it is within the range, the data of the later arrival will be
Stop at the transmission route and when two sets of data arrive at the same time
Means that only one data is transmitted on the corresponding transmission path,
Competition detection means to stop the other data on the corresponding transmission path
And a transfer control unit at a predetermined stage of the first input-side transmission line.
The transmission signal to the second input is the clock input to the second input.
The transmission signal to the transfer control unit at the predetermined stage of the
A first D-type flip-flop serving as a data input;
1 according to the output signal from the D-type flip-flop.
A transfer controller following the predetermined stage of the first input-side transmission line;
From the transmission permission signal to the transfer control unit at the predetermined stage.
A first logic gate for controlling the transmission
The transmission signal to the transfer control unit at the predetermined stage of the transmission path is
Input at a predetermined stage of the first input-side transmission path.
A second D-type that uses a transmission signal to the control unit as its data input
A flip-flop and the second D-type flip-flop
The output signal of the second input-side transmission path.
The transfer control unit of the predetermined stage next to the transfer control unit of the predetermined stage
Logic gate for controlling transmission of the transmission permission signal to the
And an output signal from the first D-type flip-flop.
And the output signal from the second D-type flip-flop.
And the output signals are both input to the logic gate.
At a level that prevents transmission of the above-mentioned transmission permission signal.
At this time, of the first and second logic gates,
The above transmission permission only for the specified logic gate
A logic circuit for outputting a signal permitting signal transmission.
And a transmission permission signal is sent from the output-side transmission path.
Corresponding to the first and second input-side transmission lines
Depending on the degree of data congestion, output from each input side transmission line
Arbitration control means to arbitrate the order of data output to the
A data transmission device, comprising: