JP2514258B2 - Data transmission equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention serializes a plurality of packet data (consisting of one word or a plurality of words) transferred via a plurality of parallel input side transmission lines. The present invention relates to a data transmission device for transmitting to an output side transmission line.

<Conventional Technology> First, a conventional data transmission device will be described.

FIG. 12 is a schematic block diagram of a conventional data transmission device. In this data transmission device, two data transmission lines 10, 2
0, 30 and 40, 50, 60 are provided in parallel, and the arbitration control unit 80
Then, in response to the transmission permission signal AK100 sent from the data transmission path 100 that is the output side transmission path, the output order is arbitrated by the congestion degree of the packet data of each of the parallel input side transmission paths and the arbitrary word number is And outputs the packet data consisting of

Next, a specific operation of the data transmission device shown in FIG. 12 will be described. In the initial state, the data transmission path 100 on the output side is in a state capable of receiving packet data, and the transmission permission signal AK100 is returned to the arbitration control unit 80. The arbitration control unit 80 receives the transmission permission signal AK100 from the data transmission line 100 on the output side, and receives the data transmission lines 30 and 6
The transmission enable signals AK81 and AK82 are output to 0. The AK81 and AK82 do not permit the transmission to the data transmission line 100 at the same time, but one of them permits the transmission to the data transmission line 100. In this example, for example, consider a state in which the data transmission line 60 is permitted and the data transmission line 30 is prohibited.

When the head word of the packet data arrives at the data transmission line 10, the post head data and the transmission signal C10 are transmitted to the data transmission line 30 via the data transmission line 20. The transmission permission signal AK10 is transmitted to the data transmission line 10 by the data and transmission signal C1.
Transmission is permitted until 0 is transmitted, but when data and transmission signal C10 are transmitted, it is output as a signal that prohibits the input of the next data and transmission signal during data reception in the previous stage, that is, during reception. It Since the transmission signal C10 is transmitted to the data transmission line 30 via the data transmission line 20, the data transmission line 30 includes the data transmission line 20 and the word number counting unit 800.
The information that the data is being received is output to the arbitration control unit 80 via the transmission permission signal. The word number counting unit 800 counts the number of data passing through the data transmission path 20, generates a packet unit pulse, and transmits it to the arbitration control unit 80. The arbitration control unit 80 confirms that there is no packet data on the data transmission line 60, and if there is no packet data, permits the data transmission line 30 to transmit data to the data transmission line 100, and Data transmission to the data transmission path 100 is prohibited for 60. The data transmission line 30 is the data transmission line 100.
Since the transmission to the data transmission path has been permitted, packet data consisting of an arbitrary number of words is transmitted to the data transmission line 100. And
When the packet data passes through the data transmission path 100,
The transmission permission signal AK81 is transmitted from the data transmission line 100 to the arbitration control unit 80.
The packet data is returned to the data transmission path 30 via the, and the data transmission path 30 permits the data transmission path 100 to send the packet data.

Next, when the head word of the packet data arrives at the data transmission line 40, the head word data and the transmission signal C40 are transmitted to the data transmission line 60 via the data transmission line 50. Information that the transmission signal C40 is being received by the arbitration control unit 80 via the data transmission line 50 and the word number counting unit 800 because the transmission signal C40 is transmitted to the data transmission line 60 via the data transmission line 50. Is output to the transmission permission signal. Word count unit 800
Then, the number of data passing through the data transmission path 50 is measured, a pulse in packet unit is generated and transmitted to the arbitration control unit 80.
The arbitration control unit 80 confirms that there is no packet data in the data transmission line 30, and if there is no packet data, permits the data transmission line 60 to transmit data to the data transmission line 100, and For 30, the data transmission to the data transmission path 100 is prohibited. The data transmission line 60 is
Since the transmission to the data transmission line 100 has been permitted, the packet data having an arbitrary number of words is transmitted to the data transmission line 100. Then, when the packet data passes through the data transmission path 100, the transmission permission signal AK82 is transmitted.
From the arbitration control unit 80 to the data transmission line 60,
The transmission of data from the data transmission line 60 is permitted.

Next, the case where the packet data 2 is input with a slight delay as compared with the packet data 1 will be described. When the first word of the packet data 1 arrives at the data transmission line 10, the transmission signal C10 is transmitted via the data transmission line 20 to the data transmission line 3
The word number counting unit 800 counts the number of pieces of data passing through the data transmission path 20, generates a packet unit pulse, and transmits it to the arbitration control unit 80. Accordingly, in the arbitration control unit 80,
The data transmission line 60 is prohibited from transmitting data to the data transmission line 100. In this state, when the first word of the packet data 2 arrives at the data transmission line 40, the packet data 1 is temporarily stopped at the data transmission line 60 via the data transmission line 50.
After passing through the data transmission path 30, the packet transmission from the data transmission path 60 to the data transmission path 100 is permitted. In this way, in the arbitration control unit 80, the packet data 1
And the packet data 2 of which the arrival time of the packet data 2 is late is temporarily stopped on the data transmission line 30 or the data transmission line 60 to arbitrate the transmission line.

FIG. 13 is a concrete circuit diagram for arbitrating two independent 2-word packet data. First, thirteenth
The configuration will be described with reference to the drawings. The data transmission lines 10, 20, 30 and 40, 50, 60 in FIG. 12 are respectively transfer control units.
It comprises 11, 21, 31 and 41, 51, 61 and data holding means 12, 22, 32 and 42, 52, 62. In addition, the data transmission line 100
Is composed of a transfer control unit 101 and a data holding unit 102. The transfer control units 11, 21, 31, 41, 51, and 61 each handshake with one transmission signal input, one transmission permission signal input, one transmission signal output, and one transmission permission signal output. Transfer control is performed. The transfer control unit 101 has a built-in function to take a logical sum of two different transmission signal inputs, and the transfer control units 11, 21, 31, 41, 51 and
Performs the same handshake control as 61. Transfer control unit 11,2
The detailed circuit of 1,31,41,51 and 61 is shown in Fig.14.
The detailed circuit of 101 is shown in FIG. Data holding means 12,22,3
2, 42, 52, 62 and 102 are configured to transfer the contents of Di to Qi when the clock pulse falls. The arbitration control unit 80 includes NAND gates 81, 82, 83 and 84 and an AND gate 85.
And 86, D type flip-flops 87 and 88, and NOR gates 89 and 90. D-type flip-flops 87 and 88 are D-type at the falling edge of the clock pulse.
The contents of the input are output to the Q output. The word number counting unit 800 is composed of D-type flip-flops 801, 802, 803 and 804 and NOR gates 805 and 806. D
The type flip-flops 801 and 802 are configured to output the contents of the D input (Q2 = 1) to the Q1 output at the falling edge of the clock pulse.
803 and 804 are configured to output the contents of the D input (Q2 = 1) to the Q1 output at the rising edge of the clock pulse.

Next, the operation of the data transmission device shown in FIG. 13 will be described. In the initial state, the reset signal RESET (“L”
Level) is given to the transfer control units 11, 21, 31, 41, 51, 61 and 101, AND gates 85 and 86, NAND gates 82 and 83, and D type flip-flops 801, 802, 803 and 804. Thereby, the transfer control units 11, 21, 31, 41, 51 and
61 is initially reset, Q1 output becomes “H” level, and Q2 output also becomes “H” level. When the transfer control unit 101 is reset, the Q1 output becomes “H” level and the Q2 output becomes “L” level. The D-type flip-flops 801, 802, 803 and 804 are set to Q1 by the reset signal.
Set the output to “H” level and the Q2 output to “L” level. The D type flip-flops 87 and 88 make the Q output "L" level by the reset signal. The output of the NAND gate 82 becomes “H” in response to the reset signal, and the NAND gate 82 is input to the NAND gate 81 forming the flip-flop. The remaining inputs of the NAND gate 81 are "H" because the Q2 outputs of the D type flip-flops 801 and 803 are both "L",
The output of the NAND gate 81 becomes “L”, and the flip-flop of the previous stage composed of the NAND gates 81 and 82 becomes stable. The subsequent flip-flop composed of NAND gates 83 and 84 receives the output of the preceding stage and
Since the reset signal is input to 83, the NAND gate
The output of 83 is "H", the output of 84 is "L", and the flip-flop in the subsequent stage is also stable. Since the output of the NAND gate 83 is given to the input of the NOR gate 89, the output of the NOR gate 89 becomes "L", and the data transmission from the data transmission line 30 to the transmission line 100 is prohibited. The output of the NAND gate 84 is given to the input of the NOR gate 90.
The output of 90 becomes "H", and the data transmission line 60 to the transmission line 100
Enables data transmission to and from.

In this state, when the packet data 1 is given to the data holding means 12 and the transmission signal C10 (“L” level) is given to the transfer control unit 11, the transfer control unit 11 causes the transfer control unit 21 to operate.
Since the Q2 output is "H", the Q1 output is set to the "L" level, the Q1 output of the transfer control unit 11 is transmitted to the transfer control unit 21, and becomes the clock pulse of the data holding means 12, and the content of the data 1 is changed. Output to Qi of the data holding means 12. Since the Q2 output of the transfer control unit 31 is “H”, the transfer control unit 21
The Q1 output is set to “L” level, the Q1 output of the transfer control unit 21 is transmitted to the transfer control unit 31, and becomes a clock pulse of the data holding means 22, and the contents of Qi of the data holding means 12 are transferred to Qi of the data holding means 22. Output. D type flip-flop
801 and 803 and the NOR gate 805 divide the Q2 output of the transfer control unit 31 by two, and the output becomes the input of the NAND gate 81. In this way, the pulse input to the NAND gate 81 can be arbitrated and controlled for data in packet units having an arbitrary number of words by arbitrarily dividing the Q2 output of the transfer control unit 31. The output of NOR gate 805 becomes the input of NAND gate 81, which changes the output of NAND gate 81 from "L" to "H", and this output becomes the inputs of NAND gates 82 and 83. When the inputs of the NAND gate 82 are all "H", the output is "L" and the flip-flop of the previous stage is stabilized. Further, as a result, in the subsequent flip-flop, the output of the NAND gate 84 becomes "H", and the output of the NAND gate 83 becomes "L" and becomes stable. The output “L” of the NAND gate 83 becomes an input of the NOR gate 89, and the transmission permission signal from the transfer control unit 101 is activated, so that
The output is set to "L" level and transmitted to the transfer control unit 101, and when the transmission permission signal AK is "H", the Q1 output of the transfer control unit 101 is "L".
At the same time, it becomes a clock pulse of the data holding means 102 and the content of Di of the data holding means 102 is output to Qi. While the output from the transfer control unit 31 is being output to the transfer control unit 101, the output “H” of the NAND gate 84 is held as the flip-flop output of the subsequent stage and input to the NOR gate 90, so the output of the NOR gate 90 is “L”. Holds the transfer control unit 61
From the output to the transfer control unit 101, and the output of the transfer control unit 31 sets the output of the D-type flip-flop 88 to "L", thereby making the output Qi of the data holding means 62 high impedance and holding the data. It does not collide with the Qi output of the means 32.

Next, when the packet data 2 is given to the data holding means 42 and the transmission signal C40 is given to the transfer control unit 41,
Since the operation is the same as that of the packet data 1 input, the description thereof is omitted.

Next, a case where the packet data 2 is input after a certain time difference from the packet data 1 after the initial state will be described. The first word of the packet data 1 is given to the data holding means 12, the transmission signal C10 is given to the transfer control section 11, and then the first word of the packet data 2 input with a slight delay is given to the data holding means 42. When the transmission signal C40 is given to the transfer control unit 41, the transmission signal C10 is given to the transfer control unit 31 via the transfer control units 11 and 21. This changes the output of NOR gate 805 from "H" to "L",
This NOR gate output “L” becomes the input of the NAND gate 81, and by changing its output from “L” to “H”,
Stabilizes the front-stage flip-flop composed of NAND gates 81 and 82. Also, the post-stage flip-flop,
Output “N” of NAND gate 84, Output “L” of NAND gate 83
And stabilized. The output of the NAND gate 83 is given to the NOR gate 89 and permits the transfer control unit 31 to send it to the transfer control unit 101. At this time, the output of NAND gate 84 is NOR gate 90.
However, the transmission control unit 61 prohibits the transmission of data from the transfer control unit 61, but the transmission control unit 31 transmits the transmission signal C10 corresponding to two words of the packet data 1 to the transfer control unit 101, and then transfers the data. Transmission of the control unit 61 is permitted. The case where the packet data 1 is input slightly later than the packet data 2 can be explained in exactly the same way, and therefore will be omitted. in this way,
When two pieces of packet data 1 and packet data 2 are input in conflict with each other, the flip-flops of the NAND gates 81 and 82 and the flip-flops of the NAND gates 83 and 84 temporarily stop the input packet data.

As described above, according to this data transmission device, when only the packet data 1 exists and the packet data 2 does not exist when the transmission path 100 on the output side is empty, the packet data 1 is sequentially output and the packet data 2 is output. If the packet data 1 exists and the packet data 1 does not exist, the packet data 2 is sequentially output. Also, packet data 1
When the packet data 2 is transmitted at the maximum transfer capacity of the data transmission path, the processing capacity of the output side data transmission path 100 cannot keep up, so the data transmission paths 30, 20 and 10 and the data transmission paths 60, 50 are transmitted. Packet data stays in and 40. In this case, the data transmission line 30 and the data transmission line 60 alternately transmit the packet data on each transmission line to the data transmission line 100 as data in packet units.

<Problems to be Solved by the Invention> However, the conventional data transmission devices shown in FIGS. 12 and 13 have the following problems.

That is, when the arbitration control unit 80 shown in FIG. 12 is composed of the NAND latches 81, 82 and the NAND latches 83, 84 shown in FIG. 13, the contention timing of the input signals such that the logical state of these latch outputs becomes undefined is unclear. Exists. That is, the 16th
As shown in the timing chart of the figure, when the output of the NOR gate 806 of FIG. 13, that is, the input of the NAND gate 82 changes at the same time as the output of the NAND gate 81 which is the other input of the gate 82, the output of the gate concerned. Becomes logically indeterminate. When the NAND latches 81, 82 and the NAND latches 83, 84 are composed of, for example, CMOS circuits, the logical indefinite state as described above changes from the logic “L” level to the logic “H” level and vice versa. Occurs at the same time, the output level will either settle to a logical "H" level, to a logical "L" level, or to an intermediate level between the two levels. Therefore, these three types of final states are determined probabilistically, and the arbitration control function itself is not impaired.However, even if the same logic / circuit configuration is used, the arbitration order of packet data for each device is small. Different things can happen. Therefore, the input order of packet data input in parallel is strictly maintained,
That is, even when inputting in parallel with a slight time difference,
For an application field in which arbitration and output are performed on a first-come-first-served basis, it is necessary to select a device that satisfies these conditions.

A main object of the present invention is to provide a conflict avoiding means that makes it unnecessary to select devices even in the above case.

<Means for Solving the Problem> A data transmission device of the present invention is for transmitting a plurality of packet data transferred via a plurality of parallel input side transmission lines in series to an output side transmission line. A data transmission device, for transmitting a plurality of packet data sequentially to the output side transmission line in the order of arrival based on a transmission permission signal from the output side transmission line and a signal indicating arrival of packet data An arbitration control unit that outputs a transmission permission signal of
Between the timing of the signal indicating the arrival of one packet data to the arbitration control unit and the subsequent input timing of the signal indicating the arrival of another packet data to the arbitration control unit, a time difference of a predetermined time or more is provided. And a conflict avoidance unit for setting.

<Operation> By providing the contention avoidance unit, it is possible to avoid the contention timing of the input signal in which the output of the arbitration control unit becomes indefinite, and even when a plurality of parallel packet data arrive in competition, Data can be transmitted while guaranteeing that data is output on a first-come-first-served basis. Therefore, the input order of the packet data input in parallel is strictly maintained, that is, even if the input is performed in parallel with a slight time difference, it is unconditionally applied to the application field in which arbitration is performed on a first-come-first-served basis. It can be applied to.

<Example> Hereinafter, the present invention will be described in detail based on examples.

FIG. 1 is a block diagram showing a schematic configuration of a data transmission device according to an embodiment of the present invention. In this embodiment, the packet data has a 2-word structure.

The feature is that the conflict avoidance unit 700 is provided. The other part, namely the data transmission lines 10, 20, 30, 40, 50, 60 and 1
The configurations of 00, the arbitration control unit 80, and the word number counting unit 800 are the same as those in FIG.

As described above, the conflict avoidance unit 700 is provided by the AK32 and AK62 which are the conflict inputs to the arbitration control unit 80.
This is to prevent the outputs of the NAND latches 81 and 82 shown in the figure from falling into a logic indeterminate state. For that, AK30 and AK
It is also necessary to avoid the conflict for the 60 input, and for the two inputs C20 and C50, the conflict must be avoided in the first place.

To avoid the conflict between the two inputs of C20 and C50, for example, according to the timing chart shown in FIG. 3, there is a significant time difference Δt + α with respect to the small time difference of Δt (for example, a difference of 2 to 3 ns.). (For example, α = 10ns.
In this case, a total of 12 to 13 ns.) Is provided and the data is sent to the next data transmission line.

When the contention time difference that causes the above-mentioned logical indefinite state has a time width of, for example, 4 to 7 ns., The data transfer control according to the present invention uses the logical configuration shown in FIG. In the case where the previous data transmission path is vacant or clogged, the self-synchronous handshake control is performed as shown in FIG. 6 and FIG. 6 (when the previous data transmission path is changed from being clogged to empty). Because it is transferred according to
It is not possible to allow or prohibit only a specific time width as the input time difference between C20 and C50. Because, for example, 10ns.
Even if the delay of 1 can be added to one input, if there is a first-arrival input on the transmission path on the opposite side of the transmission path and the transmission path on the other side is blocked, it will wait 10 ns. ,
As a result, there is a timing at which competition still occurs with a time difference of 4 to 7 ns.

Therefore, as an embodiment of the conflict avoidance unit 700, FIG. 2 (A) in the case of avoiding the conflict for each word of the packet data, or the case of avoiding the conflict for each packet in the packet data of 2 words The logical configuration is as shown in FIG.

To simplify the description, the operation in FIG. 2 (A) will be described with reference to the timing chart shown in FIG.

Now, C50 is slightly faster than C20 by Δt.
Suppose that the output is from 40. At this time, the D-type flip-flop 750 causes the AK51 to fall to the "L" level, and the disabling state is set in order to wait for the next data transfer. On the other hand,
REQ which is Q output of D type flip-flop 750 is "H"
Get up to the level. As a result, the output of the NAND gate 712 does not change and remains at the “H” level, but the output of the NAND gate 710 falls to the “L” level because RDY is at the “H” level, and hence the output of the NAND gate 711. INHB
Rises to "H" level. Therefore Nand Gate 712
Output INHA falls to “L” level, and NOR gate 752
Output CKA of is raised to "H" level. On the other hand, when INHB rises to "H" level, the output CKB of the NOR gate 722 is unconditionally set to "L" level.

Such a series of logical operations does not change even if C20 is input by Δt earlier than C50 on the timing chart shown in FIG.

Further, when considering an infinitesimal time difference of Δt → 0, in the time difference in which it is considered that the two inputs of the NAND gate 710, REQ and RDY, simultaneously hold “H” level, the logical operation as described above is performed. The input of C50 is accepted and arbitrated so that the transfer of the other input, C20, is deferred. On the other hand, if REQ and RDY are not considered to be at “H” level at the same time, and if RDY is considered to have quickly fallen to “L” level, then the initial state is retained and INHA is set to “H” level. In addition, INHB remains at "L" level,
Therefore, CKA temporarily holds the input of C50 while maintaining the "L" level, CKB rises to the "H" level in response to the input of the other C20, and the input of C20 is accepted.

In this embodiment, α is the time when the transfer of the first-arrival input to the next stage is completed, and the response signal AK20 or AK50 from the preceding stage is returned to the D-type flip-flop 720 or 750, that is, the handshake. Almost decided at the time of transfer control.

Next, FIG. 7 shows a schematic structure of an embodiment when the packet data has a one-word structure. The difference from FIG. 1 is that the word number counting unit 800 is not necessary and the transmission permission signals AK30 and AK60 from the data transmission lines 30 and 60 are AK32 and AK62, respectively.
Is input directly to the arbitration control unit 80. As the conflict avoidance unit 700, the one shown in FIG. 2 (A) is used.

The data transmission device according to the present invention is applied to, for example, a data flow type information processing device. FIG. 8 is a block diagram showing an example of the configuration of a data flow type information processing apparatus.
Further, FIG. 9 is a diagram showing an example of a field configuration of packet data processed by the information processing apparatus. FIG. 9 shows the case of a 1-word (n-bit) structure. In the case of a 2-word structure, the destination field, instruction field, etc. are divided into two words, and as shown in FIG. 1 to the first bit of word W ₁ is the information "1" indicating the first word, the first bit of the second word W _2, information indicating that the second word "0" is stored It

The configuration and schematic operation of the data flow type information processing apparatus will be described with reference to FIGS. 8 and 9. Destination information of the packet data in FIG. 9 stores destination information, instruction information stores instruction information, and data 1 field or data 2 field stores pellet data.

In FIG. 8, the program storage unit 110 includes a program memory (not shown), and in the program memory, as shown in FIG. 11, a data flow program including a plurality of destination information and a plurality of instruction information is stored. Remembered Program storage unit 110 reads out the destination information and the instruction information by addressing based on the destination information of the packet data, stores the information in the destination field and the instruction field of the packet data, and outputs the packet data.

The paired data detection unit 120 waits for the packet data output from the program storage unit 110. That is, the pair data detection unit 120 detects two packet data having the same destination information, stores the operand data of one packet data in a predetermined data field of the other packet data, and outputs the other packet data. . At this time, the one packet data is deleted.

The arithmetic processing unit 130 decodes the instruction information of the packet data output from the pair data detection unit 120, performs a predetermined arithmetic processing on the two operand data, and stores the result in the data field of the packet data, The packet data is output to the branch unit 140.

The branching unit 140 outputs the packet data to the internal data buffer 150 or the external data memory 160 based on the destination information of the packet data. Internal data buffer 150
And the packet data output from the external data memory 160 is given to the merging unit 170, and the merging unit 170 gives the packet data to the program storage unit 110 on a first-come-first-served basis.

In the data flow type information processing apparatus shown in FIG. 8, the packet data is stored in the program storage section 110, the paired data detection section 120, the arithmetic processing section 130, the branch section 140, the internal data buffer 150 or the external data memory 160. Junction 170
By continuing to rotate in order, the arithmetic processing based on the program stored in the program storage unit 110 proceeds.

The data transmission device according to the present invention can be used as the merging unit 170 of the data flow type information processing device of FIG.

The data transmission device of the present invention is not limited to the data flow type information processing device, but can be widely used for various information processing devices and other devices that require data transmission.

<Effects of the Invention> As described above, according to the present invention, by providing the contention avoidance unit, it is possible to avoid the contention timing of the input signal in which the output of the arbitration control unit is indefinite, and it is possible to avoid a plurality of parallel packets. Even if data arrives in competition, the data can be transmitted without fail by guaranteeing that data is output on a first-come, first-served basis. Therefore, the input order of the packet data input in parallel is strictly maintained, that is, even when input in parallel with a slight time difference, even for application fields such as arbitrating and outputting on a first-come-first-served basis, It can be applied unconditionally.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention, FIGS. 2 (A) and 2 (B) are circuit diagrams showing the configuration of the conflict avoidance unit shown in FIG. 1, and FIG. 2 is a timing chart used for explaining the operation, FIG. 4 is a logic circuit diagram of a transfer control unit constituting the data transmission lines 10, ..., 60 shown in FIG. 1, and FIGS. 5 and 6 are transfer control units. 7 is a block diagram showing a schematic configuration of another embodiment of the present invention, FIG. 8 is a block diagram showing a configuration of a data flow type information processing apparatus as an application example of the present invention, and FIG. FIG. 10 and FIG. 10 are configuration diagrams of packet data circulating in each part of the data flow type information processing apparatus of FIG. 8, and FIG. 11 is stored in the program storage unit of the data flow type information processing apparatus of FIG. FIG. 12 shows a part of a data flow program, and FIG. 12 shows a conventional data transmission device. Block diagram showing the schematic structure,
FIG. 13 is a circuit diagram showing the configuration of a conventional data transmission device,
14 is a logic circuit diagram of the transfer control units 11, ..., 61 shown in FIG. 13, FIG. 15 is a logic circuit diagram of the transfer control unit 101, and FIG. 16 is a logic uncertain in a conventional data transmission device. It is a timing chart which shows operation. Explanation of symbols 10,20,30,40,50,60,100: Data transmission line, 80: Arbitration control unit, 800: Word number counting unit, 700: Contention avoidance unit.

Claims (1)

(57) [Claims] 1. A data transmission device for serially transmitting a plurality of packet data transferred via a plurality of parallel input side transmission lines to an output side transmission line, wherein the output side transmission line is provided. A plurality of packet data based on the transmission permission signal and the signal indicating the arrival of the packet data, and an arbitration control unit that outputs a transmission permission signal for sequentially transmitting to the output side transmission line in the order of arrival, A time difference of a predetermined time or more is set between the input timing of the signal indicating the arrival of packet data to the arbitration control unit and the subsequent input timing of the signal indicating the arrival of another packet data to the arbitration control unit. And a contention avoidance unit for providing the data transmission device.