JPH03273353A - Communication control equipment - Google Patents

Abstract

PURPOSE:To reduce the enlargement of a communication control equipment by sharing a buffer memory and providing channel arbitrating means in plural communication circuits to execute either reception or transmission to control connection with a buffer memory to a non-competitive state. CONSTITUTION:Respective reception circuits RC0-RCn respectively share a data FIFO memory 6 through respectively intrinsic delay registers DREG0- DREGn, and a channel arbitrating circuit 8 controls the connection with this memory 6 to the non-competitive state. Namely, the received data are temporarily stored in the respectively correspondent delay registers and afterwards stored into the memory 6 without competing with the other communication data under the time divisional selection control or polling control of the arbitrating circuit 8. Thus, even when transfer requests are simultaneously generated from the plural reception circuits, the arbitrating circuit 8 prevents malfunction from being generated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a communication control device compatible with multi-channel communication,
In particular, the present invention relates to a communication control device in which a plurality of communication channels rarely perform communication simultaneously, and relates to a technique that is effective when applied to, for example, a semiconductor integrated circuit for communication control.

[Conventional technology]

In conventional communication control devices, a buffer memory such as a first-in first-out memory (hereinafter referred to as FIF○ memory) is provided for each communication circuit that constitutes one communication channel. The number of FIF○ memories equal to the number of FIF○ memories is required, and this has been a major factor in increasing the size of the communication control device. Furthermore, if the communication control device is provided as a single semiconductor integrated circuit and each communication circuit included therein has a buffer memory, a request to transfer received data is issued independently from each communication channel. Therefore, bus arbitration control for connecting each communication channel and a higher-level device must be performed externally, and this control also complicates the overall system configuration.

An example of a document describing a communication control device is Japanese Patent Laid-Open No. 62-225050.

[Problem to be solved by the invention]

As described above, conventional communication control devices have a problem in that they do not take into account the expected future increase in the size of devices due to multichannelization.9According to the inventor's study,
A communication system, such as an Ethernet LAN (Local Area Network), in which transmission and reception do not occur simultaneously, even at high speeds.

Alternatively, in the case of a communication system in which communication frequency is relatively low, the communication standby time in which the FIF○ memory is not substantially used in each communication channel becomes long, and the utilization efficiency of the FIFO memory is low. Additionally, if each communication channel has its own buffer memory, data transfer control procedures such as bus arbitration control associated with data transfer between the communication channel and higher-level devices become more complex, and this becomes even more complex as the number of channels increases. be manifested.

An object of the present invention is to provide a communication control device that can reduce the increase in size due to an increase in the number of communication channels.

Another object of the present invention is to provide a communication control device that can simplify data transfer control procedures such as bus arbitration control associated with data transfer between one communication channel and a host device even when the number of communication channels increases. It is about providing.

The above and other objects and novel features will become clear from the description of this specification and the accompanying drawings. The explanation is as follows.

That is, a buffer memory is shared by a plurality of communication circuits that perform either reception or transmission, and channel arbitration means is provided for controlling the connection between the communication circuits that share the buffer memory and the buffer memory in a non-contention state, This constitutes a communication control device that supports multi-channels. Similarly, a data FIFO memory is shared by a plurality of communication circuits that perform either reception or transmission, and the data FIFO
○ Communication circuit and data FIFO that share the memory ○ Controls the connection with the memory in a non-conflicting state, and also connects the data FIFO
Status F of the identification information of the communication circuit connected to the memory
A communication control device supporting multi-channel is configured by providing channel arbitration means for supplying data to the IF○ memory.4゜As the channel arbitration means, the communication circuit is connected to the buffer memory or the data FIF○ memory in a time-sharing manner. It is possible to adopt a configuration in which connection control is performed or connection conflict avoidance control is performed based on the priority of the communication circuit in response to a request to connect one communication circuit to the FIF○ memory.

[For production]

According to the above means, the plurality of communication circuits are data FIFO
Sharing the memory or buffer memory serves to limit the increase in the size of the communication control device due to an increase in the number of communication channels to just an increase in the number of communication circuits. For example, in the case of the reception control unit, data received by the communication circuit is stored in a temporary storage area such as a delay register, and the stored data is controlled by the 5-channel arbitration means without conflicting with other communication data. Stored in data FIFO memory. The channel arbitration means prevents malfunctions even if transfer requests are generated simultaneously from a plurality of communication generation circuits.

In this way, by ensuring that communication data conflicts are avoided and at the same time sharing a data buffer memory such as a data FIF○ memory, it is possible to reduce the size of the communication control device due to an increase in the number of communication channels.

Data transfer between each communication channel and the host device is performed via a buffer memory or data FIF◯ memory shared by a plurality of communication circuits. This works to minimize the number of data transfer requests exchanged between the communication control device and the host device, regardless of the number of communication channels. This also increases the number of communication channels.

Data transfer control procedures such as bus arbitration control associated with data transfer between a communication channel and a host device are simplified.

[Embodiment 1] Fig. 1 shows a communication system which is an embodiment of the present invention. 1 [device shown. Although this communication control device 1 is not particularly limited,
It is formed on a single semiconductor substrate such as silicon by known semiconductor integrated circuit manufacturing techniques.

This communication control device] includes, but is not particularly limited to, the reception control unit 2. It is composed of a transmission control section 3 and a bus interface section 4.

The communication control unit 2 includes receiving circuits RCO-RCn that individually receive and receive received data bit-serially transmitted from the receiving circuits RXDO-RXDn, and perform serial/parallel conversion in octet units (8-bit units); Receiving circuit RCO = delay register DRE that temporarily stores parallel data output from RCn in octet units
GO-DREGn, this delay register DREGO-
An internal bus 5 to which the outputs of DREGn are commonly connected, a data FIFO memory 6 and a status FIFO memory 7 as buffer memories whose inputs are commonly connected to the internal bus 5, and the receiving circuits RC○ to RCn and the FIFO memory 6.
a channel arbitration circuit 8 for controlling connection with 7 in a non-contention state;
and a received data transfer ready generation unit 9.

The transmission control section 3 converts the parallel data to be transmitted from parallel to serial in units of octets and sends the converted data to a transmission circuit (not shown), the details of which are not shown.

Note that the unit of serial/parallel conversion in the reception control section 2 is not limited to 8 bits, but may be any number of bits as long as it has a finite length and is constant. Further, the last delimiter of the serial data string may be exactly the number of unit focus points or may be left over. The first and last recognition of serial data is
The receiving circuit RCO according to a predetermined procedure
-RCn will do it. Similarly, the transmission control unit 3 adds information to enable recognition of the beginning and end of the transmission data.

These control procedures are determined according to the protocols supported by the communication control device, and their specific contents are not limited.

The bus interface section 4 is not particularly limited, but may include the following:
System bus 11 including data bus, address bus, etc.
CPU (Central Processing Unit) which controls the entire system through 12. DMAC (Direct Addressing) can control data block transfer in single addressing mode or dual addressing mode.
RA (memory access controller) 13, which is used as a data storage area and a work area for the CPU 12.
It is coupled to a host device such as a random access memory (M) 14. The bus interface section 4 receives bus control signals 1 output from bus master modules such as the CPU 12 and DMACl 3 as host devices, such as read/write signals R/W indicating the data transfer direction, and signals on the data bus included in the system bus 11. A data strobe signal DS or the like indicating that the data is valid is supplied.

Next, a detailed example of a configuration in which each communication channel of the reception control section 2 shares the data FIFO memory 6 will be described.

FIG. 1 typically shows details of the delay register DREGn. A D-type flip-flop 2 is connected to each output terminal of the received data and status in the receiving circuit RCn.
0 data input terminal is coupled. A data output terminal Q of each D-type flip-flop 20 is coupled to a corresponding signal line of the internal bus 5 via a tri-state output sofa 21. The receiving circuit RCn outputs a load signal LOADn at an enable level when outputting received data or status. This load signal LADn is supplied to the latch control terminal C of the flip-flop 20, so that the flip-flop 20 latches the received data and status output from the receiving circuit RCn. This latch operation is performed asynchronously with each other according to the receiving operation in each receiving circuit.

Information output to the output buffers 21 included in each of the delay registers DREGO-DREGn is controlled by selection signals 5ELO-5ELn which are sequentially set to an enable level in a time-division manner by the channel arbitration circuit 8 and output. Therefore, data received by a plurality of receiving circuits are not supplied to the internal bus 5 at the same timing. That is, contention on the bus 5 between data received by different receiving circuits is avoided.

The write clock WCLK for the data FIFO memory 6 and the status FIFO memory 7 is an OR gate 2 that receives internal transfer request signals REQO to REQn output from each delay register DREGO to DREGn.
Output from 2.

For example, in order to form the internal transfer request signal REQn, R
5 (set/reset) flip-flops 23, an AND gate 24, and two delay circuits 25 and 26 are provided. The delay circuits 25 and 26 delay the output timing relative to the input by one cycle period of the clock signal CK.

The selection signal 5ELO"SE Ln is controlled to enable level in order every X cycles of the clock signal CK. This situation is shown in FIG. 2. The RS flip-flop 23 receives the load signal LOADn at the enable level.
is set to the set state. In the AND gate 24,
Output signal of RS flip-flop 23 and selection signal 5E
Ln is input in a non-inverted manner, and at the same time, the output signal of the delay circuit 25 which inputs the selection signal 5ELn is inputted in an inverted manner. As a result, when the load signal LOADn is asserted to the enable level and the 1 selection signal 5ELn is asserted to the enable level, the output of the AND gate 24 goes high during one cycle of the clock signal CK due to the action of the delay circuit 25. Asserted to level. The AND gate output signal is further delayed by one cycle period of the clock signal CK by the action of another delay circuit 26, and is then output as the request signal R.
It is assumed to be EQn. This request signal REQn is fed back to the reset terminal R of the RS flip-flop 23, so that it is asserted at a high level for one cycle period of the tarlock signal CK, and the OR gate 22 outputs the write clock signal WCLK only during this high level period. Assert.

When the write clock signal WCLK is asserted, the data FIFO memory 6 and the status FIFO memory 7
At that time, the data supplied via the internal bus 5 is stored in a predetermined storage area.

Here, the channel arbitration circuit 8 uses a clock signal CK
a receiving circuit that includes an encoder E CD O"E CD n that encodes a count value of a clock signal CK/x obtained by dividing the clock signal CK/x by X to form the selection signals 5ELO to 5ELn, and is selected by a selection signal that is sequentially asserted. It has an encoder ECD that generates a communication channel identification code 31 for identifying the type of communication channel.The output of this encoder ECD is supplied to the status FEFO memory 7.

The data FIFO memory 6 and the status FIFO memory 7 function as buffer memories that store data in a first-in, first-out format in a readable/writable manner, and their write access is instructed by the write clock signal WCLK, and their read access is particularly Although not limited to this, the read/write signal R/W output from the DMAC 13, particularly the read clock (not shown), is formed according to the read instruction level thereof.

When even one piece of data is stored in the data FIFO memory 6, or when the number of data stored in the data FIFO memory 6 reaches a predetermined number, the transfer ready generation unit 9
Although not particularly limited, the data transfer request signal DREQ is asserted to DMACl3. As a result, DMAC],
'3 reads the communication channel identification code from the status FIFO memory 7 and determines the receiving source channel of the data to be read from the data FIFO memory 6;
The corresponding predetermined address on the RAM 4 is set as a transfer destination address, and the received data is DMA transferred from the data FIFO memory 6 to the transfer destination address in single addressing mode.

According to the above embodiment, there are the following effects.

(1) Each of the receiving circuits RCO to RCn shares the data FIFO memory 6 via their respective unique delay registers DREGO to DREGn, and controls the connection between the channel arbitration circuit 8 and the data FIFO memory 6 in a non-conflicting state. . As a result, the data received by the receiving circuit is temporarily stored in the corresponding delay register, and the stored data is prevented from competing with other communication data according to the time division selection control or polling control by the channel arbitration circuit 8. The data is stored in the data FrFO memory 6 instead.

In this way, the channel arbitration circuit 8 prevents malfunctions from occurring even if transfer requests are generated simultaneously from a plurality of receiving circuits. Therefore, by sharing the data FIF memory 6 while guaranteeing the avoidance of competition in received data, it is possible to reduce the increase in size of the communication control device due to an increase in the number of communication channels.

(2) Data transfer between each communication channel and the higher-level device is performed via the data FIFO memory 6 shared by the plurality of receiving circuits RCO-RCn. At least one type of data transfer request can be exchanged between the two, regardless of the number of communication channels.

For example, according to this embodiment, the DMA transfer request signal DREQ can be unified. Therefore, even if the number of two communication channels increases, data transfer control procedures such as bus arbitration control associated with data transfer between communication channels and host devices can be simplified.

(3) Due to the above effects, there is no need to provide a special bus arbitration circuit outside the communication control device 1 composed of - semiconductor integrated circuits to control the connection between each communication channel and the host device. It will be done.

(4) Since the channel suspension circuit 8 performs contention avoidance control for received data in a time-division or Bonong format, the control logic therefor is extremely simple, further promoting miniaturization of the communication control device 1.

(5) Since the status FIFO memory 7 that stores the communication channel identification information 31 in synchronization with the write operation of the data FIFO memory 6 is provided, the data FIFO
The attributes of the received data read from the O memory 6 can be easily and reliably known, and the degree of freedom in the data transfer control procedure for the received data to the host device side can be increased.

[Embodiment 2] FIG. 3 shows a communication control device 40 according to another embodiment of the present invention.
is shown. A communication control device 40 shown in the figure is different from the communication control device 1 of the embodiment described above in the configuration of a delay register and a channel arbitration circuit. That is, in the above embodiment, conflict avoidance between the connection between each receiving circuit and the FIF○ memory 6 was performed using time division control or a boring method, but in this embodiment, it is configured to be performed using a request/approval control method. .

When the receiving circuits RCO-RCn included in the receiving control unit 42 output received data and status asynchronously with each other,
Ill-pull level load signal LOADO=L
When OA D n is output, the delay registers DDREGO to DDREGn that receive it assert write request signals W RE Q O to W RE Q n to the channel arbitration circuit 41 . The channel arbitration circuit 41 has priority assigned to the receiving circuit RCO=RCn, and the write request signal WREQO-WR
When requests from a plurality of receiving circuits compete with each other due to E Q n, write approval is given to a receiving circuit with a relatively higher priority. Acknowledgment signals WACKO-WACKn are output to delay registers DDREGODREGn.

FIG. 4 representatively shows details of the delay register DDREGn. This delay register DDREGn
has a D-type flip-flop 44 whose data input terminal is connected to each of the received data and status output terminals in the receiving circuit RCn, and the data output terminal of each D-type flip-flop 44 is connected to a tri-state output buffer 45. It is coupled to the corresponding signal line of the internal bus 5 via. The receiving circuit RCn outputs a load signal LOADn at an enable level when outputting received data or status. This load signal LOADn is supplied to the latch control terminal C of the flip-flop 44, so that the flip-flop 44 latches the received data and status output from the receiving circuit RCn. This latch operation is performed asynchronously with each other according to the receiving operation in each receiving circuit. Further, the load signal LOADn at the enable level sets the R3 type flip-flop 46. This causes a request signal W to be sent from the data output terminal Q of the RS flip-flop 46 to the channel arbitration circuit 41.
RE Q n is asserted.

Information output from the output buffer 45 is performed by asserting the acknowledge signal WACKn outputted from the channel waste stop circuit 41 to a high level. Therefore, data received by a plurality of receiving circuits are not supplied to the internal bus 5 at the same timing. In other words, conflicts between received data of mutually different receiving circuits are avoided.

Note that the actuator signal WA asserted to a high level
CKn is also supplied to the reset terminal R of the RS flip-flop 46, thereby causing the request signal WREQ
n is negated.

The write clock WCLK for the data FIF○ memory 6 and the status FIFO memory 7 is the write clock signal WACKO~W output from the channel arbitration circuit 41.
It is output from the OR gate 47 which receives ACK n.

When the write clock signal WCLK is asserted, the data FIFO memory 6 and the status FIFO memory 7
At that time, the data supplied via the internal bus 5 is stored in a predetermined storage area.

Here, the channel arbitration circuit 41 encodes the acknowledge signals WACKO to WACKn, for example, and
It has an encoder AECD that generates a communication channel identification code 31 for making it possible to identify the type of receiving circuit acknowledged by the acknowledgment signal. This encoder AE
The output of the CD is supplied to the status FIF○ memory 7.

The other configurations are the same as those of the above embodiment.

When the received data is stored in the data FIF○ memory 6,
The transfer ready generation unit 9 is not particularly limited to, but may be
Assert data transfer request signal DREQ to Cl3.

As a result, the DMACl 3 reads the communication channel identification code from the status FIFO memory 7, determines the receiving source channel of the data to be read from the data FIFO memory 6, and sets the corresponding predetermined address on the RAM 14 as the transfer destination address. DMA transfer control of received data from the data FIFO memory 6 to the transfer destination address is performed in single addressing mode.

As in the above embodiment, priorities are set for the receiving circuit and requests are made to avoid conflicts in connection between the receiving circuit and the data FIFO memory.
Even if the admission control method is used, the data FIFO memory 6 can be shared while ensuring that contention of received data is avoided, as in the embodiment described above.

It is possible to reduce the increase in size of the communication control device due to an increase in the number of communication channels. Similarly, data transfer between each communication channel and the host device is performed using the data FIFO memory 6 shared by the plurality of receiving circuits RCO-RCn.
Because it is done through.

At least one type of data transfer request can be exchanged between the communication control device 1 and the host device regardless of the number of communication channels. Therefore, even if the number of communication channels increases, data transfer control procedures such as bus arbitration control associated with data transfer between communication channels and host devices can be simplified. In particular, as in this embodiment, when conflict avoidance control of received data is performed according to the priority order of the receiving circuits, the polling method control provides flexibility such as giving priority to the operation of the receiving circuit with a high communication class. It can be increased more than that. Furthermore, it becomes possible to programmably change the priority of each receiving circuit from the host device side depending on the communication situation.

Although the invention made by the present inventors has been specifically described above based on examples, the present invention is not limited thereto, and various changes can be made without departing from the gist thereof.

For example, in the above embodiment, a case has been described in which the DMAC 13 performs write access control to the data FIF memory 6, but the CPU 12 may perform the write access control. At this time, the communication channel identification code stored in the status FIFO memory 7 is made accessible to the CPU via the system bus 11. Further, even when the DMACl3 performs access control, the communication channel identification code is not limited to the configuration in which the communication channel identification code is transmitted via a dedicated signal line as in the above embodiment, but a system bus may be used. Also,
In the above embodiments, the receiving circuit and the delay register have been described as separate circuit blocks, but the function of the delay register may be included in the receiving circuit.

In the above description, the invention made by the present inventor was mainly applied to a reception control section in a semiconductor integrated circuit for communication control, which is the field of application in which the invention was made, but the present invention is not limited thereto. Therefore, it can be widely applied to the transmission control section of the semiconductor integrated circuit. The present invention can be applied at least to conditions with multiple communication channels.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, even if a plurality of communication circuits share a data FIFO memory or a buffer memory, and transfer requests are generated simultaneously from the plurality of communication circuits, the arbitration control means does not
Since the collision of communication data on the FO memory or buffer memory is controlled to avoid, it is possible to share the buffer memory such as the data FIFO memory while guaranteeing the avoidance of collision of communication data, and to control the communication by increasing the number of communication channels. This has the effect of reducing the size of the device by limiting the increase in size to only the increase in communication circuits6.In addition, data transfer between each communication channel and the host device is shared by multiple communication circuits. Buffer memory or data FIF
Since data transfer is performed via O memory, the number of data transfer requests exchanged between the communication control device and the host device can be reduced regardless of the number of communication channels. This has the effect that data transfer control procedures such as bus arbitration control accompanying data transfer between a communication channel and a host device can be simplified.

By adopting a configuration in which a communication circuit is connected and controlled to a FIFO memory or a data FIFO memory in a time division or polling manner as the channel arbitration means, it contributes to the simplification of the logical scale of communication data conflict avoidance and thus to the simplification of the channel arbitration means. I can do it.

As the channel arbitration means, by adopting a configuration in which control is performed to avoid connection conflicts based on the priority of one communication circuit based on the request to connect a communication circuit to the FrFO memory, communication circuits with high communication frequency can be This method has the advantage that flexibility such as prioritizing operations can be increased more than the polling method.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a communication control device according to an embodiment of the present invention, and FIG. 2 is a timing diagram of an example of a time division selection control operation. FIG. 3 is a block diagram of a communication control device according to another embodiment of the present invention. FIG. 4 is a block diagram of an example of a delay register included in the communication control device shown in FIG. 3. 1. Communication control device, 2. Reception control section, 6. Data F
IF○ memory, 7...Status FIF○ memory, 8...
...Channel arbitration circuit, RCO-RCn/reception M circuit,
DREGO-DREGn...Delay register, 4o...Communication control device, 41 Channel arbitration circuit, 42...Receiving control unit, DDREGO-D: Gn...Delay register. Diagram

Claims (1)

[Claims] 1. A multi-channel communication control device equipped with a plurality of communication circuits that share a buffer memory and perform either reception or transmission, wherein the buffer memory is shared. A communication control device comprising channel arbitration means for controlling the connection between a communication circuit and a buffer memory in a non-conflicting state. 2. The communication control device according to claim 1, wherein the channel arbitration means controls the connection of communication circuits that share the buffer memory to the buffer memory by time division or priority control. 3. A multi-channel communication control device equipped with a plurality of communication circuits that share a data FIFO memory and perform either reception or transmission, wherein the data FIFO
The connection between the communication circuit and the data FIFO memory that shares the FO memory is controlled to be non-conflicting, and the data FIFO
A communication control device comprising channel arbitration means for supplying identification information of a communication circuit connected to an FO memory to a status FIFO memory. 4. The communication control device according to claim 3, wherein the channel arbitration means controls connection of communication circuits that share the data FIFO memory to the data FIFO memory in a time-division manner. 5. The channel arbitration means connects the communication circuit to a data FIF.
5. The communication control device according to claim 4, wherein connection conflict avoidance control is performed based on the priority of the communication circuit in response to a request to connect to the O memory.