JPH10307787A - Buffer memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a buffer memory device capable of obtaining performance equivalent to a case using an expensive dual port memory by comparatively inexpensive memory constitution and eliminating the necessity of complicated control. SOLUTION: A single port memory is divided into memory banks 104, 106. Each of direct memory access(DMA) controllers 102, 103 executes low speed data transfer or high speed data transfer (writing or reading) processing. An access timing generation circuit 101 generates time divided and opposed access timing for writing or reading and outputs the timing to the controllers 102, 103. When both the controllers 102, 103 access the same memory bank, a competition control circuit 105 sends a wait signal to the controller 102.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer memory which absorbs a data transfer speed difference between data processing devices and is particularly accessed in an interleaved manner from two or more direct memory access controllers (hereinafter abbreviated as DMAC). Related to the device.

[0002]

2. Description of the Related Art Conventionally, this kind of buffer memory device has
It is used for an input / output (I / O) interface or the like to absorb a difference in transfer speed between data processing devices (input side devices, output side devices) having different data transfer speeds. That is, the data DMA-transferred from the low-speed data transfer side (or the high-speed data transfer side) is written to the memory through the DMA controller, and is read out at high speed through another DMA controller to the high-speed data transfer side (or the low-speed data transfer side). Used for forwarding purposes.

[0003] The following three typical conventional examples are known as such a method of accessing a buffer memory. (1) A method in which the access time is time-divided from a plurality of DMA controllers to one memory bank constituted by a single-port memory. (2) A method of using a dual port memory as a memory bank. (3) A memory access conflict control circuit that performs conflict control for one memory bank constituted by a single port memory based on memory access signals from a plurality of DMA controllers, and a gate that separates a bus line between DMA controller memories A method using a circuit.

Normally, a bus master that performs memory access outputs an address signal before outputting a memory access signal, and holds the address signal for a while after the end of the memory access signal.

FIG. 5 is a block diagram showing a configuration for performing time-division processing of access times from a plurality of DMA controllers (DMACs) to the memory bank of (1).
Is an access timing chart in the time division processing. 5 and FIG. 6 show that the DMA controller 2 and the DMA controller 2 are stored in the single-port memory 1 as in the case of the above (1).
3, the access time is time-divisionally processed at the timing from the access timing generation circuit 4.

In this example, each memory access is valid prior to a memory access signal. Therefore, it has the access right for a while after this access is completed. Therefore, invalid timing occurs in which the single port memory 1 is not actually accessed from any of the bus masters (DMA controllers 2 and 3). Here, the free block queue FIFO memory 5 processes the low-speed interface. That is,
The processing is performed by the first-in first-out method, the processed block number is re-registered, and the free block number is read.
Similarly, the effective block queue FIFO memory 6 serves as an interface on the high-speed data transfer side, registers a write block number, and detects a read block number.

FIG. 7 is a block diagram showing a configuration when the above-mentioned (2) dual port memory is used as a memory bank, and FIG. 8 is an access timing diagram of this configuration. 7 and 8 show two bus masters (DMA controllers 11, 1) in the process of using the dual port memory 10 as the memory as in the case of (2) above.
The dual port memory 10 which is not affected by the signal from 2) is used. Therefore, there is no invalid timing in the access timing, and ideal access timing can be established.

FIG. 9 shows the above-mentioned (3) contention control circuit and DM
FIG. 10 is a block diagram showing a configuration when a gate circuit that separates a bus line between A controller memories is used.
Is an access timing chart. 9 and 10 use the single-port memory 20 and use the memory access contention control circuit 2 as in the case of the above (3).
1, and gate circuits 24, 25, 26 and 27 for separating bus lines between the DMA controllers 22 and 23 and the single port memory 20.
And a bus master (DMA controllers 22, 23)
The gate circuits 24 to 27 are controlled by the memory access contention control circuit 21 based on the memory access signal output from the CPU so that the signal from the bus master does not collide on the address bus and the data bus.

In this process, when only one bus master accesses, the access can be performed at substantially the same timing as the process (2) using the dual port memory. However, it is impossible to prevent memory access from conflicting between both bus masters. For this reason, an arbitration circuit and a gate circuit having a complicated configuration for performing control so that signals on the address bus and the data bus do not collide with each other are required.

[0010]

As described above, the conventional buffer memory has the following disadvantages. The above (1)
In the process of time-dividing the time for accessing the memory from the plurality of DMA controllers as in the conventional example, the speed-up process cannot be performed. That is, useless processing time occurs at the memory access timing.

In the processing using a dual port memory as in the above-mentioned conventional example (2), the cost of the apparatus increases.
That is, the dual-port memory cannot increase the memory capacity of the single chip as compared with the single-port memory, resulting in an increase in cost.

When a contention control circuit and a gate circuit for separating a bus line between a DMA controller and a memory are used as in the prior art (3), the control is complicated. That is, a memory access signal is always input from a plurality of bus masters (DMA controllers), and the contention control circuit arbitrates which of the bus masters gives priority to the access. It is necessary to control a gate circuit for cutting off the data bus.

The present invention solves such a problem in the prior art, and can be constituted by a relatively inexpensive memory, and at the same time, obtains the same performance as when an expensive dual-port memory is used. Another object of the present invention is to provide a buffer memory device capable of eliminating complicated control.

[0014]

According to a first aspect of the present invention, there is provided a buffer memory device which absorbs a difference in data transfer speed between data input / outputs. A first DMA controller that performs low-speed or high-speed data transfer, a second DMA controller that performs low-speed or high-speed data transfer opposite to the first DMA controller, and the first and second DMA controllers time-divide data. Access timing generation means for generating and outputting an access timing signal for contradictory transfer; and transmitting a wait signal to the first DMA controller when the first and second DMA controllers access the same memory bank in a race condition. And a conflict processing means.

In the buffer memory device according to the present invention, a free block queue FIFO memory for re-registering a processed block number as an interface process for data transfer and reading a free block number, and an interface process for data transfer And an effective block queue FIFO memory for registering a write block number and detecting a read block number.

According to a third aspect of the present invention, in the buffer memory device, one or both of the first and second DMA controllers is n.
DMA controllers, and n
Arbitration processing means for arbitrating DMA transfers from the DMA controllers and sending the arbitration result to the n DMA controllers.

According to a fourth aspect of the present invention, in the buffer memory device, as the contention processing means, an address from a DMA controller is input, and an access timing signal is input as it is or after being inverted through an inverter. And a comparator for sending a wait signal obtained by comparing the output of the flip-flop circuit to one of the DMA controllers.

According to a fifth aspect of the present invention, the memory is a single-port memory.

According to a sixth aspect of the present invention, in the buffer memory device, one of the two memory banks dividing the memory is divided into fixed-length blocks having even block numbers, and the other is divided into fixed-length blocks having odd block numbers. There is a divided configuration.

[0020] Claims 1,2,4,5,5
In the buffer memory device according to the invention described in the sixth aspect, unnecessary processing time does not occur at the memory access timing, and the access waiting time is minimized, so that high speed operation is performed. Further, since a single-port memory is used, the memory capacity of a single chip can be increased as compared with a case where a dual-port memory is used, resulting in a reduction in price. Further, there is no need to control a gate circuit for interrupting the data bus between the memory and a bus master other than the arbitrated bus master. That is, complicated control is not required.

According to a third aspect of the present invention, there is provided a method for transmitting a DMA from a DMA controller comprising n DMA controllers.
Since the transfer is arbitrated, n low-speed data transfer sides (or high-speed data transfer sides) can be multiplexed into one high-speed data transfer side (or low-speed data transfer side) line.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a buffer memory device according to the present invention will be described in detail with reference to the drawings. FIG.
FIG. 1 is a block diagram showing a configuration of a buffer memory device according to a first embodiment of the present invention. The buffer memory device shown in FIG.
An access timing generation circuit 101 for generating access timing (access right) to the MA controller;
DMA controller 1 for accessing by DMA transfer
02, 103 [DMAC (A), DMAC (B)].

Further, this buffer memory device is constituted by a single port memory, and has a memory bank 104 storing even-numbered fixed-length blocks (0, 2,..., N-2) and odd-numbered fixed-length blocks (1, 3). .. N-1) are stored, and both bus masters determine whether or not to access the same bank, and transmit a wait signal when accessing the same bank. It has a control circuit 105.

An interface (I / F) on the low-speed data transfer side, a free block queue FIFO memory 107 for re-registering a processed block number by a first-in first-out method and reading a free block number; It is an I / F on the high-speed data transfer side, and has an effective block queue FIFO memory 108 for registering a write block number by a first-in first-out process and detecting a read block number.

FIG. 2 is a block diagram showing a detailed configuration of the conflict control circuit 105. The competition control circuit 105 of FIG.
Address (A) from DMA controllers 102 and 103
drs) are input to the data terminal (D), respectively, and the access timing signal is input to the clock terminal (CK) as it is or after being inverted through an inverter, and flip-flop (F / F) circuits 201 and 202;
And a comparator 203 for sending to the DMA controller 102 a wait signal obtained by comparing the outputs of the output terminals (Q) of the F / F circuits 201 and 202.

Next, the operation of the first embodiment will be described. First, the overall operation will be briefly described. Here D
The MA controller 102 is used for low-speed data transfer, and the DMA controller 103 is used for high-speed data transfer. Further, the DMA controller 102 is dedicated to writing (transmission side), and the DMA controller 1
It is assumed that 03 is read-only (receiving side). In addition,
Even if the transmitting side and the receiving side are opposite, the same operation is performed as follows.

In the access timing generation circuit 101, the DMA controller 102 has an access right when a clock signal having a duty ratio of 50 to 50 is at a high (H) level, and has an access right when the clock signal is at a low (L) level. , DMA controller 103 has an access right. The high-level and low-level times of one clock signal (one pulse) are set to the minimum accessible values.

The DMA controller 102 performs access when a high-level access timing signal is output from the access timing generation circuit 101.
The controller 103 includes the access timing generation circuit 10
When a low-level access timing signal is output from 1, the access is performed. Contention control circuit 105
Are the address valid signals from the DMA controllers 102 and 103 input to the F / F circuits 201 and 202, and the address bits indicating which of the memory banks 104 and 106 are to be accessed, as shown in FIG. Based on the respective DMA controllers 102 and 103,
Access the memory banks 104 and 106,
The comparator 203 determines whether access is possible or not by comparing them.

That is, it is determined whether or not access is possible by interleaving or the same memory banks 104 and 106 are accessed and their address signals collide, and whether or not access by interleaving is impossible. Here, when access by interleaving is impossible, the comparator 203
To DMA controller 102 (Wait)
Send a signal. This wait signal causes the DMA controller 102 to temporarily suspend the DMA transfer.

In the memory banks 104 and 106, the blocks have odd and even block numbers (0, 2,...
2, 1, 3... N-1), and if these block numbers are used in order, access is not biased to one side. If the memory bank (104, 1
06, hereinafter, the number in parentheses indicates one of them)
Is performed by both of the DMA controllers 102 and 103, the interleaving is performed when the time corresponding to the access for one block at the maximum elapses.
3 can be accessed from both.

Free block queue FIFO memory 10
7 and the effective block queue FIFO memory 108 store, as an initial state, empty block numbers in order so that accesses are performed alternately without being concentrated on one side during a write process to the memory banks 104 and 106. An empty block number is read from the DMA controller 102 on the writing side, and a writable block number is stored.

This empty block number is stored in the DM on the writing side.
The A controller 102 reads the data, performs DMA transfer to the block number, and thereafter sets this block number as valid and stores it in the valid block queue FIFO memory 108. The other DMA controller 103 can recognize the block number in which the valid data is stored from the valid block queue FIFO memory 108 by reading the data, and thus reads the data of this block number by DMA transfer. All the data in the memory banks 104 and 106 are read, and after the completion, the block number is re-stored in the free block queue FIFO memory 107 as processed.

Further, this operation will be described in detail. FIG.
Is a timing chart showing the processing timing of the operation. Here, when the access time in the single port memory of the memory banks 104 and 106 requires, for example, 20 ns, the access timing generation circuit 101
The frequency of the clock signal is 25 MHz, and the duty ratio is 50:50.

The DMA controller 102 to which this clock signal is supplied, when the access signal is at a high level, outputs a single port memory (memory banks 104, 10).
6) is accessed. Then, before the access signal goes high to satisfy the address setup time / address hold time required by the single port memory, for example, if the address setup time is 5 ns, the address is made effective 5 ns before. The address is retained even after this access is completed. For example, if the address hold time is 3 ns, 3 ns
Hold the above.

As described above, the contention control circuit 105 uses a single port memory (memory banks 104 and 106) having an access time of 20 ns, and
The same memory bank (104, 10
When detecting whether or not to access (6), the access timing is switched as shown in FIG. At the time of this switching, the address bits of the outputs of the DMA controllers 102 and 103 are respectively latched and compared. For example, a block number (0, 2... N-2, 1, 3... N-1)
Is 64 words, the address bits 6 are respectively latched and compared.

The 64-bit address bits are assigned so that the address valid signals of the DMA controllers 102 and 103 and the odd / even number of the block number to be accessed can be determined. For example, block numbers (0, 2,..., N−2, 1, 3
If the capacity of... N-1) is 64 words, the address 000
000H-00003fH is assigned to block number 0. In addition, address 000040H-00007fH is assigned to block number 1.

If the comparisons by the conflict control circuit 105 are the same, the D
Temporarily stop MA transfer. In addition, the access by the DMA controllers 102 and 103 is performed in one of the memory banks 10.
The free block queue FIFO memory 107 holds a free block number so as not to be biased to 4,106. In this case, the free block queue FIFO memory 107 holds the data in order from the number 0 in the initial state. If the free memory has data to be written, the free block number is read and the block number to be written is set to the DM.
Notify the A controller 102. After the DMA controller 103 completes the reading, the block number is restored.

Similarly, the valid block queue FIFO memory 108 stores the currently used memory bank 104,
The block numbers of 106 are sequentially stored. That is, DM
A controller 102 to memory banks 104 and 106
And the DMA controller 1
03 recognizes the block number to be DMA-transferred by this reading. These two free block queues F
The IFO memory 107 and the block queue FIFO memory 108 are processed only immediately before or immediately after the processing for the block number, respectively, and otherwise only store the stored data without access.
It is not particularly necessary to establish synchronization with the access timing.

Next, a description will be given based on the processing timing of the operation in FIG. One clock signal Ta, Tb in FIG.
For example, the clock signal is 20 ns, the frequency is 25 MHz, and the duty ratio is 50 to 50. When the clock signal is at a high-level interval, the DMA controller 1
02 accesses the memory banks 104 and 106. Also, when the clock signal is at low level, DM
The A controller 103 accesses the memory banks 104 and 106. This access timing indicates that each access valid signal is active.

The memory banks 104 and 106 require that the address bus be valid before the access timing, and it is necessary to secure a value that satisfies the address setup time. For this reason, a time period of Tc = 5 ns or more is secured so that the address bus becomes effective before the actual access. Similarly, since the address hold time needs to be satisfied, the address is made valid in a time period of Td = 3 ns or more.

As a result, the DMA controller 103 can access the other memory banks 104 and 106 in an interleaved manner while waiting after the DMA controller 102 accesses the memory banks (104 and 106).

FIG. 4 is a block diagram showing the configuration of the second embodiment. In the second embodiment shown in FIG. 4, a low-speed data transfer side of n lines is multiplexed with a high-speed data transfer side of one line. Here, a DMA controller composed of n DMA controllers for low-speed data transfer is used. 102 a and an arbitration circuit 109. Other configurations are the same as those of the first embodiment in FIG.

Next, the operation of the second embodiment will be described. The DMA controller 102a sends the DMA transfer to the arbitration circuit 109 at the time of the data transfer request,
The arbitration result is transmitted to each DMA controller 1
02a, 103. One of the DMA controllers 102a having the transfer right interleaves with the DMA controller 103 to access the memory banks 104 and 106.

In this embodiment, the DMA controller 102a is dedicated to writing (transmitting side) and the DMA controller 103 is dedicated to reading (receiving side). However, when the transmitting side and the receiving side are configured to be opposite, DM
The A controller 103 may be composed of n DMA controllers.

[0045]

As is apparent from the above description, according to the buffer memory device of the present invention, no unnecessary processing time is generated at the memory access timing, and the access wait time is reduced. Since time is minimized, high-speed operation is possible. Further, since a single-port memory is used, the memory capacity of a single chip can be increased as compared with the case of using a dual-port memory, and the cost is reduced. Further, there is no need to control a gate circuit for cutting off a data bus between the memory and a bus master other than the arbitrated bus master, and thus complicated control is not required.

According to the third aspect of the present invention, n DMs are provided.
The DMA transfer from the DMA controller composed of the A controller is arbitrated. As a result, n low-speed data transfer sides (or high-speed data transfer sides) can be multiplexed into one high-speed data transfer side (or low-speed data transfer side) line.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a buffer memory device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of a contention control circuit in FIG.

FIG. 3 is a timing chart of an operation in the embodiment.

FIG. 4 is a block diagram illustrating a configuration of a second embodiment.

FIG. 5 is a block diagram showing a configuration for time-dividing access times from a plurality of DMA controllers in a conventional example.

FIG. 6 is an access timing chart in the processing state shown in FIG. 5;

FIG. 7 is a block diagram showing a configuration when a dual-port memory is used in a conventional example.

FIG. 8 is an access timing chart in the processing state shown in FIG. 7;

FIG. 9 is a block diagram showing a configuration when a gate circuit is used in a conventional example.

FIG. 10 is an access timing chart in the processing state shown in FIG. 9;

[Explanation of symbols]

101 access timing generation circuit 102, 102a DMA controller [DMAC
(A)] 103 DMA controller [DMAC (B)] 104, 106 memory bank 105 contention control circuit 107 free block queue FIFO memory 108 effective block queue FIFO memory 109 arbitration circuit 201, 202 F / F circuit 203 comparator

Claims (6)

[Claims] 1. A buffer memory device for absorbing a speed difference when a data transfer speed in data input / output differs, a memory divided into two memory banks, a first DMA controller performing low-speed or high-speed data transfer, A second DMA controller that performs low-speed or high-speed data transfer opposite to the first DMA controller; and an access in which the first and second DMA controllers generate and output an access timing signal for transferring data in a time-division and contradictory manner. A buffer memory, comprising: timing generation means; and contention processing means for sending a wait signal to the first DMA controller when the first and second DMA controllers access the same memory bank in a contention state. apparatus. 2. A free block queue FIFO memory for re-registering a processed block number which is an interface process of data transfer and reading a free block number, and a write block number which is an interface process of data transfer. 2. The buffer memory device according to claim 1, further comprising an effective block queue FIFO memory for detecting a read block number. 3. One or both of the first and second DMA controllers are composed of n DMA controllers, and DMAs from the n DMA controllers are provided.
2. The buffer memory device according to claim 1, further comprising arbitration processing means for arbitrating the transfer and sending the arbitration result to the n DMA controllers. 4. Two flip-flop circuits, as the contention processing means, to which an address from a DMA controller is input and an access timing signal is input as it is or inverted through an inverter, and an output of the flip-flop circuit 2. The buffer memory device according to claim 1, further comprising: a comparator that sends a wait signal obtained by comparing the two to the one DMA controller. 5. The buffer memory device according to claim 1, wherein said memory is a single port memory. 6. The memory bank according to claim 1, wherein one of the two memory banks dividing the memory is divided into fixed-length blocks having even block numbers, and the other is divided into fixed-length blocks having odd block numbers. The buffer memory device according to claim 1.