KR970004522B1 - Preempt request arbitrator among bus masters - Google Patents

Abstract

A device for mediating preempt request between bus masters is disclosed. The device comprises a bus master control means outputting a response signal to a requested signal when a state control signal for controlling the response signal is inputted after a preempt request signal between a plurality of bus masters is stored when the preempt request signal is input, and a mediation control means outputting the state control signal to the bus master control means by receiving a response signal after the response signal is transferred to a main processor by receiving an external mediation mode determination signal and a plurality of the request signal. Thus, the bus master operation is not disturbed and the mediation time is reduced.

Description

Arbitration request mediation device between bus masters

1 is a block diagram of a lien request arbitration apparatus according to the present invention.

2 is a detailed view of a bus master controller according to the present invention.

3 is a detailed view of an arbitration control unit according to the present invention.

4 is a timing diagram according to the present invention.

* Description of the symbols for the main parts of the drawings *

1: bus master control unit 2: arbitration control unit

11 to 11n: Latch 12 to 12n: NAND gate

21: timer 22 to 22n: state control unit

23 to 23n: Inverter 24: Multiplexer

25: Andgate

The present invention relates to a preempt request mediation device between bus masters.

Conventional bus master arbitration methods are serial, parallel, and recursive. In the above three cases, when a lower bus master request is generated, even if the bus master with the higher priority has to wait until the current request is completed, the next bus master request is requested through mediation again when the current bus master request is completed. You must decide. In other words, in the case of commonly used bus master arbitration, there is a concept of priority, but if the currently requested bus master operation is not terminated, the higher priority request cannot receive a response and mediates again even if the current request is terminated. You must get a response through the process. This is to prevent the system from malfunctioning by protecting the current operation. In this case, despite the high priority, there is a waiting time until the current request ends. There was a problem to have.

The present invention devised to solve the problems of the prior art is to give a priority to the lower bus priority by giving up the request to the lower priority currently in progress when a request conflict between the bus master occurs and the higher priority request occurs, while at the same time lower priority After detecting that the request has been released, the sub-bus master whose priority has been suspended is given time to recover, and again, without having to go through the bus ownership process through arbitration, and using the rights of the lower-priority already terminated. It is an object of the present invention to provide a preemptive request arbitration device between bus masters that can prevent malfunctions and shorten the time required to recalibrate bus master arbitration.

In order to achieve the above object, a device of the present invention may be configured to temporarily store a plurality of bus master preempt request signals and then, if a state control signal for control of a response signal is input, to a request signal. Bus master control means for outputting a response signal; And receiving an arbitration mode determination signal through the plurality of request signals and data lines from the outside, sending a request signal to the main processor, and receiving a response signal to output a state control signal to the bus master control means. And an arbitration control means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram of a preemptive request arbitration apparatus according to the present invention, in which 1 represents a bus master controller and 2 represents an arbitration controller.

As shown in the figure, in the present invention, there are several bus master routes having a pair of requests and responses, and when a request is made to the bus master controller 1 via the bus master route, the arbitration control unit 2 arbitrates the request. It then sends a final request signal to the main processor unit (MPU) (not shown).

When the response signal is received from the main processor unit (MPU) by this request signal, the arbitration control unit 2 outputs a state control signal to the bus master control unit 1, and the bus master control unit 1 controls the state. It will receive a signal and send a response signal for the preferred request route. In addition, the arbitration control unit 2 transmits and receives to and from the outside so as to program the preemption function and timing through the data line.

2 is a circuit diagram of a bus master controller according to the present invention. First, when a request signal is input, the latches 11 to 11n corresponding to the number of request signals inputted temporarily store the input request signal.

A plurality of NAND gates 12 to 12n connected to the plurality of latches respectively receive outputs from the plurality of latches 11 to 11n and receive state control signals from the arbitration control unit 2. Output a response signal to the request signal.

3 is a detailed block diagram of an arbitration control unit according to the present invention. As shown in the figure, the first request signal inputted is inverted through the inverter 23, and the state controller 22 delays the request signal inverted by the inverter 23, and then the control signal from the timer 21 If it is input, the status signal for request signal 0 is outputted as 0.

From the second request signal to the nth request signal, the corresponding request signal is inverted through each inverter, and the AND gate 25 receives an AND signal of the request signal and the request signal up to the request signal before the request signal. Output to state controller 22n.

In addition, an externally input preamble enable signal is input to the multiplexer 24, and the multiplexer 24 is controlled by the preemp enable signal to multiply the reference potential (high) by the AND gate 25. )

The AND gate 25 receives the request signal corresponding to its own number, the request signal until its own request signal, and the output of the multiplexer 24, and outputs the AND signal to the state controller 22n.

The state controller 22n receives an output from each AND gate 25 and outputs a state control signal for controlling the output of a response signal to each request signal under the control of the timer 21. Output to 1). The arbitration control unit configured as described above is for the upper signal to interrupt the request for the lower signal.

Programmable arbitrators enable the preemption signal to be disabled when there are no performance differences between bus masters and enable if there is a performance difference, allowing the high speed bus master to reduce arbitration time Allows the master to borrow the responses obtained.

Also, by arranging a value in the timer, the host bus releases the response of the active bus master and then responds to the host bus master by the programmed time without waiting for the request of the master bus master to be released. You can save more time.

The timer program must be determined within a range that does not affect system operation.

As shown in FIG. 4, when the lower request is first generated, the arbitration control unit 2 recognizes the lower request and generates an MPU request as shown in A. FIG. When the MPU response occurs, it generates a lower response like C for the recognized lower request. This is done through the logic of FIG. If an upper request is generated while the lower request is in progress, the upper request releases the response of the lower request, as shown in D in FIG. 4, and when the lower response is released, the lower bus master releases its request as E. . The lower bus master must then save the operating state and prepare for the next request. The response signal is then sent as F, where the MPU request and response are kept in the state obtained by the lower request.

After the upper request obtains the response, the operation can be performed, and the upper bus master is released in order of FIG. 4 in the order of G, H, and I.

The present invention is applicable to all bus structures that require premute operation, particularly where arbitration between bus masters is required.

According to the present invention, the upper bus master accurately guarantees the request of the upper bus master, and also provides a time for the lower bus master in progress to prepare for the sudden release of the request. Obtaining a response can save arbitration time.

Claims (3)

Bus master control means for temporarily storing a plurality of bus master preempt request signals and then outputting a response signal to the requested signal when a state control signal for controlling the response signal is input; And an arbitration mode receiving signal for receiving an arbitration mode decision signal through the plurality of request signals and data lines from the outside, and receiving a response signal, and outputting a status control signal to the bus master control means. A preemption request arbitration device between bus masters, comprising a control means. 2. The apparatus of claim 1, wherein the bus master control means comprises: a plurality of latch means for receiving a plurality of premite request signals and temporarily storing and outputting the received signal; And a plurality of negative logical multiplication means connected to each latch means for receiving an output of the latch means and a state control signal from the arbitration control means and outputting a response signal to the request signal. Preemption Arbitration Device. 2. The apparatus of claim 1, wherein the arbitration control means comprises: inverting means for inverting a request signal corresponding to its own th; Counting means for counting according to data input from the outside and outputting the count value; First state control means for receiving the output of the first inverting means and outputting a state control signal for the first request signal to the bus master control means (1) when a control signal is input from the counting means; Selection means connected to the reference potential and controlled by an external premite enable signal to output a reference potential; A plurality of logical multiplication means for receiving an output from the inverting means corresponding to its own number, receiving a first previous request signal except for a first request signal, and receiving and outputting the output of the selection means; And a plurality of second state control means for receiving outputs of the plurality of logical multiplication means, respectively, and outputting a state control signal for each request signal to the bus master control means under control of the counting means. Arbitration request mediation device between bus masters.