JPS60222951A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS60222951A
JPS60222951A JP59078427A JP7842784A JPS60222951A JP S60222951 A JPS60222951 A JP S60222951A JP 59078427 A JP59078427 A JP 59078427A JP 7842784 A JP7842784 A JP 7842784A JP S60222951 A JPS60222951 A JP S60222951A
Authority
JP
Japan
Prior art keywords
register
input
request
processor
processing device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59078427A
Other languages
Japanese (ja)
Inventor
Chihiro Tsuchiya
土屋　千尋
Kazuya Hori
堀　一哉
Noboru Kinoshita
登 木下
Masayuki Nakamura
雅幸 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59078427A priority Critical patent/JPS60222951A/en
Publication of JPS60222951A publication Critical patent/JPS60222951A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To change easily the data transfer speed of an input/output controller by transferring a request demand from a request demand generating means to a processor in accordance with the counted result of a counting means to perform direct memory access (DMA). CONSTITUTION:Information which designates a transfer speed is set to a register 6 through a programmable IO bus 4 by an instruction from a processor 1. At a DMA transfer time, this information is transferred to a count register 7, and counting is performed synchronously with clocks from a clock generating circuit 8, and contents of the register 7 are sent to a NAND gate 9. Meanwhile a request demand from a request generating circuit 10 is given to the gate 9. The request demand is transferred to the processor 1 through a signal line 12 synchronously with the counted result of the register 7 in accordance with speed information set to the register 6. Data received from the processor 1 through a DMA5 is stored temporarily in a buffer 11 and is sent to an input/output device 3.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明はデータ転送方式に係り、特に処理装置と入出力
制御装置の間でＤＭＡ転送を行う場合のデータ転送方式
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data transfer method, and particularly to a data transfer method when performing DMA transfer between a processing device and an input/output control device.

〔発明の背景〕[Background of the invention]

処理装置とそれに接続される入出力制御装置から構成さ
れるシステムにおいて、これらの装置間で転送されるデ
ータの転送速度は、一般に、入出力制御装置を設計する
時に決定され、ハードウェア的に固定した転送速度とな
っている。このためデータの転送速度を容易に変更する
ことは出来ない。In a system consisting of a processing unit and an input/output control device connected to it, the transfer rate of data transferred between these devices is generally determined when designing the input/output control device and is fixed in terms of hardware. It has a high transfer speed. Therefore, the data transfer speed cannot be easily changed.

例えば、制御方式が同様の入出力制御装置％ＤＭＡ処理
速度の異なる処理装置に接続しようとした場合、処理装
置のパススルーブツトに対し、入出力装置の占有率が高
（なりすぎ、システムが動作不能に陥いるという事態が
生ずる。For example, if you try to connect to a processing device with the same control method but a different DMA processing speed, the occupancy rate of the input/output device will be too high (too high, and the system will not work properly) with respect to the pass throughput of the processing device. A situation arises where you become incapacitated.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、入出力制御装置のデータ転送速度を容
易に変更することができるデータ転送方式を提供するも
のである。An object of the present invention is to provide a data transfer method that allows the data transfer rate of an input/output control device to be easily changed.

〔発明の概要〕[Summary of the invention]

本発明は、処理装置とこの処理装置に接続され、処理装
置との間でＤＭＡ転送を行なう入出力制御装置を含むシ
ステムにおいて、入出力制御装置に、任意のデータ転送
速度を指定するための情報をセットするレジスタと、こ
のレジスタの出力情報をあるタイミングで計数する計数
手段と、リクエスト要求を発生するリフニスＩ・要求発
生手段を設け、この計数手段の計数結果に従って、リク
エスト要求発生手段からの請求を処理装置に転 送してＤ　ＭＡ転送を行なう様にしたものである。The present invention provides information for specifying an arbitrary data transfer rate to the input/output control device in a system including a processing device and an input/output control device connected to the processing device and performing DMA transfer between the processing device and the input/output control device. A register for setting a register, a counting means for counting the output information of this register at a certain timing, and a request generation means for generating a request, and a request from the request request generation means is provided according to the counting result of the counting means. The data is transferred to the processing device for DMA transfer.

〔発明の実施例〕[Embodiments of the invention]

以下、不発明の一％施例を図面を用いて説明する。第１
図は一実施例によるシステムのフロック図である。この
図において、処理１装置１にはＰ　ｉＯハス４、ＤＭＡ
データバス５、リクエスト（）もＢＱ）信号線１２を介
して複数の入出力制御装置２が接続される。また、各入
出力制御装置２には、夫々、入出力装置３が接続される
。Hereinafter, a 1% embodiment of non-invention will be described with reference to the drawings. 1st
The figure is a block diagram of a system according to one embodiment. In this figure, a processing device 1 includes a P iO lotus 4, a DMA
A plurality of input/output control devices 2 are connected via a data bus 5 and request () and BQ) signal lines 12. Further, each input/output control device 2 is connected to an input/output device 3, respectively.

この様な構成のシステムにおいて、入出力制御装置２よ
りＲＥ　Ｑ信号線１２ヲ介してリクエスト要求か処理装
置１に転送され、ｆ）　Ｍ　Ａデータバス５を介してデ
ータが転送される。In a system having such a configuration, a request is transferred from the input/output control device 2 to the processing device 1 via the REQ signal line 12, and f) data is transferred via the MA data bus 5.

本実施例においてこのリクエスト信号の発生間隔を容易
に変更制御するものである。このため、入出力制御装置
２には、転送速度情報を格納−するレジスタ６及びカウ
ントレジスタ７か設けられる。In this embodiment, the generation interval of this request signal can be easily changed and controlled. For this reason, the input/output control device 2 is provided with a register 6 and a count register 7 for storing transfer rate information.

即ち、レジスタ６には、処理装置】からの命令によって
ＰＩＯパス４を介して送られてくる転送速度を指定する
ための情報がセットされる。ｆ）　Ｍ　Ａ転送時には、
この情報かカウントレノスタフに移され、クロック発生
回路８から出力される内部クロックに同期してカウント
される。このカウントレジスタ７の出力はＮＡＮＤケー
ト９に送られる。That is, information for specifying the transfer rate sent via the PIO path 4 is set in the register 6 by a command from the processing device. f) During M A transfer,
This information is transferred to the count reno stave and counted in synchronization with the internal clock output from the clock generation circuit 8. The output of this count register 7 is sent to a NAND gate 9.

一方、このＮＡＮＤケ−１・９には、リクエスト要求発
生回路１０からリクエスト要求が与えられる。On the other hand, a request request is given to the NAND keys 1 and 9 from the request request generation circuit 10.

而して、レジスタ６にセットされる速度情報に従ってカ
ウントレジスタ７０カウント結果に同期してリクエスト
要求かＲｚ　Ｑ信号線１２ヲ介して処理装置１に転送さ
れることになる。また、処理装置１からＤＭＡデータバ
ス５を介して受信されたデータはデータバッファ１１に
一時格納され、入出力装置３に送られる。逆に、入出力
装置３で発生したデータは、データバッファｌｌ、ＤＭ
Ａデータバス５を介して処理装置１に送られる。Accordingly, in accordance with the speed information set in the register 6, the request is transferred to the processing device 1 via the RzQ signal line 12 in synchronization with the count result of the count register 70. Further, data received from the processing device 1 via the DMA data bus 5 is temporarily stored in the data buffer 11 and sent to the input/output device 3. Conversely, data generated in the input/output device 3 is transferred to the data buffer ll, DM
The data is sent to the processing device 1 via the A data bus 5.

このように、本実施例によれば、入出力制御装置２をＤ
　Ｍ　Ａ処理能力の異なる処理装置１に接続することか
できる。また入出力ｔｌＩｌ制御装置２におけるデータ
の転送速度を、入出力抜Ｎ３等の転送速度に合わせて使
用することもできる。すた処理装置１に複数の入出力制
御装置２を接続したシステムにおいて、優先処理力）必
要となる場合には優先度の高い入出力制御装置の転送速
度を速くすることにより、システムの使用方法に最適な
構成とすることができる。In this way, according to this embodiment, the input/output control device 2 is
The MA can be connected to processing devices 1 having different processing capacities. Further, the data transfer rate in the input/output tlIl control device 2 can be used in accordance with the transfer rate of the input/output controller N3, etc. In a system in which a plurality of input/output control devices 2 are connected to a data processing device 1, priority processing power can be achieved by increasing the transfer speed of a high-priority input/output control device if necessary. The configuration can be optimized for

〔発明の効果〕〔Effect of the invention〕

本発明によれば、入出力制御装置のテ′−り転送速度を
任意に変更設定することかできる。According to the present invention, it is possible to arbitrarily change and set the data transfer speed of the input/output control device.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明の一実施例による処理装置と、複数の
入出力制御装置およびｉ０装置を含むシステムを示すブ
ロック図。 １・・処理装置　２・・・入出力制御装置３・入出力装
置　４・・・ＰＩＯハス ５・・・］）ＭＡデータバス ６・・・レジスタ ７・・カウントレジスタ ８・・・クロック発生回路 ９・・ＮＡＮＤゲート １０・・・リフニスト要求発生回路 １トテータパノファ １２・・凡ＢＱ信号線 代理人弁理士　高　橋　リＪＪ　夫FIG. 1 is a block diagram illustrating a system including a processing device, a plurality of input/output control devices, and an i0 device according to an embodiment of the present invention. 1... Processing device 2... Input/output control device 3... Input/output device 4... PIO bus 5... ]) MA data bus 6... Register 7... Count register 8... Clock generation circuit 9...NAND gate 10...Riffist request generation circuit 1 Totator panopher 12...Bon BQ signal line agent patent attorney Takahashi Ri JJ Husband

Claims (1)

【特許請求の範囲】[Claims] 処理装置と、該処理装置に接続され処理装置との間でＤ
ＭＡ転送を行なう入出力制御装置を含むシステムにおい
て、該入出力制御装置に任意のデータ転送速度を指定す
るための情報をセットするレジスタと、該レジスタの出
力情報をあるタイミングで計数する計数手段と、リクエ
スト要求を発生するリクエスト要求発生手段を設け、該
計数手段の計数結果に従って該リクエスト要求発生手段
からのリクエスト要求を処理装置に転送してＤＭＡ転送
を行なうことを特徴とするデータ転送方式。D between a processing device and a processing device connected to the processing device
In a system including an input/output control device that performs MA transfer, there is provided a register for setting information for specifying an arbitrary data transfer rate in the input/output control device, and a counting means for counting output information of the register at a certain timing. . A data transfer system, characterized in that a request generating means for generating a request is provided, and the request from the request generating means is transferred to a processing device to perform DMA transfer according to the counting result of the counting means.
JP59078427A 1984-04-20 1984-04-20 Data transfer system Pending JPS60222951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59078427A JPS60222951A (en) 1984-04-20 1984-04-20 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59078427A JPS60222951A (en) 1984-04-20 1984-04-20 Data transfer system

Publications (1)

Publication Number Publication Date
JPS60222951A true JPS60222951A (en) 1985-11-07

Family

ID=13661740

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59078427A Pending JPS60222951A (en) 1984-04-20 1984-04-20 Data transfer system

Country Status (1)

Country Link
JP (1) JPS60222951A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5016165A (en) * 1987-01-12 1991-05-14 Fujitsu Limited Direct memory access controlled system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5016165A (en) * 1987-01-12 1991-05-14 Fujitsu Limited Direct memory access controlled system

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