JPS63153635A - Specification system for data transfer speed - Google Patents

Abstract

PURPOSE:To shorten a system start-up time by making a data transfer speed at the time of microprogram loading and setting the data transfer speed suitable to a system after the loading. CONSTITUTION:A microprocessor 16 sets the minimum value of a DMA interval in a DMA interval register 10 when a command written in a command register 6 indicates the microprogram loading. Consequently, the time between DMA requests is set to the shortest time with which the system can operates. The DMA request interval corresponding to the system is put in data of the loaded microprogram as a parameter after the end of the microprogram loading, and the microprocessor 16 refers to the parameter at the time of initial processing to set the DMA request interval in the DMA interval register 10.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data transfer method when performing DMA transfer between a processing device and an input/output control mechanism, and relates to a data transfer method for performing DMA transfer between a processing device and an input/output control mechanism. This concerns the designation method.

・[Prior art] Conventionally, when loading a microprogram to an input/output control mechanism using microprogram control using DMA & transmission, it is difficult to load the same type of microprogram to multiple input/output control mechanisms. For information on reducing microprogram load time, please contact @Kaikai57-15204
Although it was described in Publication No. 4, no consideration was given to shortening the time when loading different microprograms to a plurality of input/output control mechanisms.

[Problem that the invention seeks to solve]

The purpose of the present invention is to reduce the startup time related to microprogram loading of the input/output control mechanism, which increases in proportion to the size of the system configuration, and to optimize the input/output control mechanism determined by the system configuration. The main advantage is that you can set the data transfer rate.

[Means for solving problems]

The above purpose is to load microprograms to each input/output control mechanism at system start-up by increasing the data transfer rate of each input/output control mechanism, and then loading the microprograms to other input/output control mechanisms connected to the system. This is achieved by restoring the data transfer rate determined by the relationship number with the input/output control mechanism.

[Effect]

During system operation, each input/output control mechanism may operate simultaneously, so the path throughput of the processing unit
The bus occupancy rate of each input/output control mechanism is considered to be a problem, but since multiple input/output control mechanisms do not operate simultaneously at the time of system startup, the data transfer speed is increased only when loading the microprogram. However, the system will not become inoperable.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

When the power is turned on and the system is reset, the initial program stored in the read-only memory 14 causes the microprocessor 16 to perform initial processing, and the processing device 1 sends the microprogram to the input/output control mechanism 2. Rotation instruction is command register 6
When the command is written to the command register 6 through the data bus 17, an instruction reception interrupt is generated to the microprocessor 16 via the instruction reception interrupt line 7, and the microprocessor 16 receives the command written to the command register 6 from the microprogram (microprogram). In the case of instructions, DMA interval register 10
Then, set the minimum value of the DMA interval to 1. When the microprocessor 16 activates DMA, the DMA request circuit 12 outputs a DMA request signal to the NAND gate input 111120.

DMA set in DMA interval register 10
The request interval value is counted down sequentially,
When the value becomes 0, the DMA is sent to the NAND gate input line 18.
Outputs an interval signal. The DMA request signal is an output signal of the DMA request circuit 1υ2 and the DMA interval register 1o, and is outputted to the processing device 1 via the DMA request signal line 18 according to the conditions of the NAND gate 11. Therefore, the time between DMA requests is the minimum time that the system can operate. After the microprogram load is completed, the DMA request interval corresponding to the applicable system is incorporated as a parameter in the data loaded with the microprogram in the memory 9 during system generation in advance, and the microprogram is loaded after the microprogram is loaded. Microprocessor 1 when initial processing is performed by the program.
6 refers to the parameter and sets the DMA request interval in the DMA interval register 1o. Thereby, the subsequent DMA transfer rate between the input/output control mechanism 2 and the processing device 1 can be freely set according to the system configuration at the time of system generation.

〔Effect of the invention〕

According to the present invention, the data transfer speed to the input/output control mechanism at the time of system start-up can be made faster than during system operation, so the system start-up time can be shortened, and after the system start-up, it can be set freely depending on the system configuration. Since the data transfer speed can be increased, the capabilities of the human output control mechanism and the input/output device can be fully utilized.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram of a processing device, a plurality of input/output control mechanisms, and input/output devices, and a block diagram of the input/output control mechanism according to an embodiment of the present invention. 1... Processing device, 2... Input/output control mechanism,
3... Input/output device, 4... Input/output control mechanism B,
5... Input/output device B, 6... Command register, 7... Instruction reception interrupt line, 8... Data buffer,
9...Memory, 13...Person output buffer, 16...
・Microprocessor. 7・8・

Claims (1)

[Claims] 1. In a system consisting of an input/output control mechanism that loads microprograms and transfers data using a processing unit and DMA transfer, an instruction for specifying a data transfer rate to the input/output control mechanism, and the speed specified by that instruction. It has a register and a counter to store values, and by controlling the generation interval of the data transfer request signal using the above value and the counter, the data transfer speed is increased when loading the microprogram, and after the loading of the microprogram is completed,
A data transfer rate specification method that sets a data transfer rate suitable for the system by referring to parameters transferred by microprogram loading.