JPH0262649A - Input/output controller - Google Patents

Abstract

PURPOSE:To enable other CPUs to successively use the input/output controllers even in the case these controllers are occupied and become inactive by releasing the occupation of the controllers with the multi-address communication. CONSTITUTION:An occupation instruction given from a CPU is inputted to an input/output instruction control circuit 103 via a common input/output bus 101 and a common input/output bus control circuit 102. At the same time, the CPU number is stored in a CPU member register 110. In the case the CPU that instructed the occupation becomes inactive by some factor, a system controller detects this fact and inputs the multi-address communication to instruct the release of the occupation state. The multi-address communication is received by a multi-address communication control circuit 105, and the CPU number whose occupation should be released is stored in a CPU number register 111. The CPU number is compared with the contents of the register 110 by a comparator 108. When the coincidence is obtained from this comparison, the occupation state is released by an occupation state releasing circuit 106.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a common input/output bus for CPU, 5crs
Regarding the input/output control device connected to the CPU,
The present invention relates to an input/output control device that operates exclusively by a specific CPU according to an exclusive command from the CPU.

2. Description of the Related Art Conventionally, in this type of input/output control device, it has been possible to release an occupied state only by a release command from a CPU that has issued an instruction for occupancy.

Problems that the invention aims to solve Therefore, in the conventional input/output control device described above.

If the CPU that was instructed to be occupied becomes inoperable for some reason, it will remain occupied and other CPUs will
The PU was no longer usable.

The present invention has been made in view of the above-mentioned conventional situation,
Accordingly, an object of the present invention is to provide a novel input/output control device that makes it possible to solve the above-mentioned problems inherent in the conventional technology.

Means for Solving the Problems In order to achieve the above object, 11 an input/output control device according to the present invention includes means for receiving a circular communication instructing release of occupation from a common input/output bus; CPU
The computer is configured to include means for comparing the CPU number with the CPU number of the CPU it is occupying, and means for canceling its own exclusive state if the two match as a result of the comparison.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an input/output control device according to the present invention.

Referring to FIG. 1, the input/output control device 1.00 of the present invention
is connected to the CPU and SCP via the common input/output bus 101 (
system controller).

Occupancy commands from the CPU are input to the input/output command control circuit 103 via the common input/output bus 101 and the common input/output bus control circuit 102. The input/output control device 100 stores the CPU number of the occupying instruction in the CPU number register 110, and enters a state in which it accepts only the instructions of the CPU that is instructed to be occupied. In the input/output control device that has become occupied, the input/output command output from the CPU is input to the input/output command control circuit 103 via the common input/output bus control circuit 102, and the CPU number of the input/output command is It is stored in number register 109.

CPU number register 109 and CPU number register 110
The contents of are compared by the comparator 107, and the comparison result is transmitted to the input/output command control circuit 103. If the comparison results match, the input/output command is accepted and executed by the execution control circuit 104. If the comparison results do not match, the input/output instruction is not executed.

If the CPU that was instructed to occupy becomes inoperable for some reason, the SCP that monitors the system
detects the inoperability of the terminal, and outputs a broadcast communication to the common input/output bus lO1 instructing release of the occupied state. The input/output control device 100 receives the broadcast communication via the common input/output bus control circuit 102, and the CPU number to be released from occupation by the 0 round communication received by the 1 round communication control circuit 105 is stored in the CPU number register 111. . The contents of CPU number register 110 and CPU number register 111 are compared by comparator 108, and the comparison result is transmitted to occupied state release circuit 106. When the comparison results match, the occupied state release circuit 106 controls the input/output command control circuit 103 to release the occupied state. The input/output control device dloO, whose occupied state has been released, thereafter accepts input/output commands from any CPU until a new occupied command is executed from another CPU.

FIG. 2 is a diagram showing an example of the configuration of a data processing system using the input/output control device of the present invention.

Referring to FIG. 2, CPU 201. CPU202
．． 5CP203゜I/O control bag! 100 and 100' are connected by a common input/output bus 101.

The input/output control bags @100 and 100' are used by the CPU 201 or 202, and the input/output control device occupied by one CPU cannot be used by the other CPU.CPU 201 occupies the input/output control bag @100. The CPU 202 cannot use the input/output control device 100 when the input/output control device 100 is in use. In this case, if the CPU 202 becomes inoperable, the input/output control bag @100 remains occupied and the CPU 202 cannot be used.

The 5CP 203 constantly monitors the CPU 201 and the CPU 202, and detects when the CPU 201 becomes inoperable.

Then, the 5CP 203 outputs a relay communication to instruct the common input/output bus lot to release the occupied state. When the input/output control devices 100 and 100' receive the broadcast communication, they compare the CPU number of the CPU they are occupying with the CPIJ number shown in the broadcast communication, and if they match, they change their own occupation state. If they are released and they do not match, the occupied state remains as is. Therefore, the input/output control device lOO releases its own exclusive state, and the CPU 202 becomes able to use the input/output control device 100.

As described in detail, by using the input/output control device of the present invention in a data processing system, when a certain CPU becomes inoperable while occupying the input/output control device, other CPUs can
The effect is that the PUs can continue to use their input/output control devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an input/output control device according to the present invention, and FIG. 2 is a diagram showing an example of the configuration of a data processing system using the input/output control device of the present invention. 100, 100', input/output control device of the present invention, 10
1. ,. common input/output bus, 102. ,,Common input/output bus control circuit. 103, , input/output command control circuit, 104. ,,Execution control circuit.

Claims (1)

[Claims] An input/output control device for a data processing system in which a central processing unit (hereinafter abbreviated as CPU), a system control device (hereinafter abbreviated as SCP), and an input/output control device are connected via a common input/output bus, An input/output control device that enters an occupied state in which it executes only instructions from a specific CPU in response to an occupation instruction from the CPU, and thereafter does not accept instructions from any CPU other than the occupied CPU until it receives an occupation release instruction from the occupied CPU. means for receiving a broadcast communication instructing release of exclusive use from the common input/output bus;
means for comparing the CPU number indicated in the broadcast communication with the CPU number of the CPU it is occupying; and means for canceling its own exclusive state if the comparison result of the comparison means matches the CPU number; An input/output control device comprising: