JPH05158708A - Interruption control circuit - Google Patents

Abstract

PURPOSE:To provide an interruption control circuit which can output an interruption request in response to the request of a CPU and regardless of an edge or level sense of the CPU interruption acceptance specifications against plural interruption requests of the same level and also can surely input even the interruptions subsequent to the first one with no regeneration of an edge in the edge sense mode. CONSTITUTION:When plural interruptions of the same level are inputted, these interruptions are outputted to a CPU after the interruptions of higher priority are accepted or negated. Under such conditions, an edge control circuit (changing means) 33 can output again the interruptions of the same level after outputting once a non-interruption level. Furthermore an edge control designating register (selection means) 34 sets the validity or the invalidity of the circuit 33.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control circuit, and more particularly to improvement of an interrupt control circuit capable of assigning a plurality of interrupt factors to one interrupt level of a CPU.

[0002]

2. Description of the Related Art A mask, which is arranged between a CPU and an external interrupt generator, selectively masks an external interrupt request input to the CPU, expands the number of interrupt factors, and further CPs.
An interrupt control circuit is used to generate and return a vector number returned to U.

FIG. 3 shows a simple example of a conventional interrupt control circuit.

The interrupt control circuit has seven interrupt input terminals of negative logic LIR0 # to LIR6 # as interrupt inputs. These seven interrupt input terminals are connected to this interrupt control circuit from a device or circuit that generates an interrupt, and are called local interrupts. Further, this interrupt control circuit has interrupt input terminals BIR0 # to BIR.
It has seven interrupt input pins of negative logic of IR6 #. These interrupt input terminals are provided to expand the number of interrupt factors, are input from other interrupt control circuits or interrupt generating devices or circuits, and are called bus interrupts. These interrupt inputs are prioritized as interrupt levels, exist from level 0 to level 6, and level 0 has the highest priority. The interrupt input terminals corresponding to level 0 that generate interrupts that cannot be masked to the CPU are LIR0 # and BIR0 #, and up to LIR6 # and BIR6 # corresponding to level 6. There is also a priority order between local interrupts and bus interrupts, with local interrupts having higher priority.

Further, this interrupt control circuit has IRL0:
There is a bus that outputs an interrupt request to the CPU called 2. Since IRL0: 2 is composed of three signal lines 0, 1, and 2, it is referred to as IRL0: 2. These three signal lines have a value of 0 to 7, and 0 to 6 are levels. 0 to level 6 interrupts, 7 CPU
Indicates that there is no interrupt request.

In FIG. 3, 1 is a local interrupt input unit, 2 is a bus interrupt input unit, and 3 is an interrupt output unit. Reference numeral 11 arranged in the local interrupt input unit 1 is an interrupt request register that holds the local interrupt input to the interrupt control circuit for each level, and 12 is an interrupt mask register that can set whether or not to mask each local interrupt level. is there. Reference numeral 21 is a bus interrupt request register which is arranged in the bus interrupt input unit and holds the bus interrupt input for each level. An interrupt level determination unit 31 arranged in the interrupt output unit 3 determines the highest priority interrupt request from the masked local interrupt request from the local interrupt input unit 1 and the bus interrupt request from the bus interrupt input unit 2. A circuit 32 is an interrupt level output circuit which receives the output of the interrupt level determination circuit 31, encodes the interrupt level into IRL 0: 2, and outputs it to the CPU.

Next, the operation of the interrupt control circuit configured as described above will be described.

When a single interrupt input is input to this interrupt control circuit, for example, when LIR2 # is asserted, a level 2 interrupt is held in the interrupt input register 11. If a mask is specified for level 2 in the interrupt mask register 12, this level 2
Interrupt input cannot be accepted. But level 2
If no mask is specified for, the level 2 interrupt request is transmitted to the interrupt level determination circuit, it is determined that there is no bus interrupt, and the interrupt request is only level 2 of the local interrupt, and acceptance of the level 2 local interrupt is determined. Then, the interrupt level output circuit 32 is instructed to output the interrupt of level 2. Interrupt output circuit 3
At 2, the level 2 is encoded and 2 is output to IRL 0: 2. The CPU starts the interrupt service when the interrupt level 2 is input. The interrupt factor is
Receive an interrupt acknowledge signal from the CPU or C
When the PU executes the handler for this level 2 interrupt, by negating LIR2 #, the level 2 information held in the interrupt request register 11 is cleared and resolved. Here, the method of eliminating the interrupt factor will not be described in detail.

Next, the case where a plurality of interrupts are input to the interrupt control circuit will be described. When only a plurality of local interrupts are input, an interrupt with a low level number and a high priority is first output to the CPU, and an interrupt with a next low priority is output to the CPU. The same applies when multiple bus interrupts are input. Also,
When local interrupts and bus interrupts are mixed and input, if the levels are different, the highest priority is processed first, and if the levels are the same, the local interrupt is preferentially output. These arbitrations are held in the interrupt request register 11, and are processed in the interrupt level determination circuit 31 which receives the local interrupt processed by the interrupt mask register 12 and the bus interrupt held in the bus interrupt request register 21 as inputs.

As an example of multiple interrupt inputs, LIR0
The case where # and BIR0 # are asserted will be described. This state is shown in FIG. First, the local interrupt LI
When R0 # is asserted, the interrupt request register 11
Level 0 interrupt information is latched at. If the level 0 mask is not specified in the interrupt mask register 12, the generation of level 0 is transmitted to the interrupt level determination circuit 31, and the interrupt level output circuit 32 sends I to the CPU.
0 is output to RL0: 2. Then bus interrupt BI
R0 # is asserted and the mask information of level 0 is latched in the bus interrupt request register 21. The generation of the level 0 interrupt is transmitted to the interrupt level determination circuit 31, but since the level 0 interrupt of LIR0 # is already being processed, the level 0 interrupt request of BIR0 # is temporarily held. After that, when the level 0 interrupt of LIR0 # is accepted by the CPU or cleared by the level 0 handler, the level 0 interrupt information latch of the interrupt request register 11 is released, and then BIR0 #.
Level 0 interrupt request is processed to 0 at IRL0: 2
Will continue to be output. Further, when a level 0 interrupt request by BIR0 # is accepted by the CPU or BIR0 # is negated by the handler,
Level 0 latched in the bus interrupt request register 21
The interrupt input state of is cleared, and the interrupt level output circuit 32 outputs 7 to IRL 0: 2, that is, no interrupt request.

[0011]

In the interrupt control circuit as described above, when the interrupt request of the same level is generated by the local interrupt and the bus interrupt, the interrupt request of the same level is continuously output to the CPU. Become. When the CPU accepts these interrupts by level sense, the interrupts of the same level are sequentially processed. However, for example, when a level 0 non-maskable interrupt occurs in a local interrupt and a bus interrupt, and when the CPU accepts a level 0 interrupt by edge sensing, a subsequent level 0 interrupt request cannot be accepted. Occur. In this case, in addition to this interrupt control circuit, it is necessary to add a circuit for validating the subsequent level 0 interrupt, resulting in an increase in the number of parts.

[0012]

In order to solve the above problems, in the interrupt control circuit of the present invention, when a plurality of interrupts of the same level are input, interrupts of the same level are accepted after the interrupt of high priority is accepted or negated. To C
When outputting to PU, once the level without interruption is
After that, the changing means for outputting the interrupt of the same level to the CPU again is provided.

Further, a selecting means for selectively setting whether the changing means is valid or invalid is also provided.

[0014]

In the interrupt control circuit provided with the above-mentioned changing means, when a plurality of interrupts of the same level are input, an edge is provided between the interrupt input which is preferentially processed and the interrupt request which is subsequently processed. Enabled, CP
It becomes possible to process a plurality of interrupts in sequence with respect to the edge-sensing interrupt level of U.

Further, since the selecting means can enable / disable the changing means for temporarily generating a level without an interrupt request to the CPU, both level sense and edge sense interrupts can be dealt with and a dedicated addition is made for each CPU. It is not necessary to provide a circuit.

[0016]

【Example】

Example 1. An example of the interrupt control circuit of the present invention is shown in FIG.

This interrupt control circuit has seven negative logic interrupt input terminals LIR0 # to LIR6 # as interrupt inputs. These seven interrupt input terminals are connected to this interrupt control circuit from a device or circuit that generates an interrupt, and are called local interrupts. Further, this interrupt control circuit has interrupt input terminals BIR0 # to BIR.
It has seven interrupt input pins of negative logic of IR6 #. These interrupt input terminals are provided to expand the number of interrupt factors, are input from other interrupt control circuits or interrupt generating devices or circuits, and are called bus interrupts. These interrupt inputs are prioritized as interrupt levels, exist from level 0 to level 6, and level 0 has the highest priority. The interrupt input terminals corresponding to level 0 that generate interrupts that cannot be masked to the CPU are LIR0 # and BIR0 #, and up to LIR6 # and BIR6 # corresponding to level 6. There is also a priority order between local interrupts and bus interrupts, with local interrupts having higher priority.

Further, this interrupt control circuit has IRL0:
There is a bus that outputs an interrupt request to the CPU called 2. IRL0: 2 has a value of 0 to 7, 0 to 6 indicate level 0 to level 6 interrupts, respectively, and 7 indicates that there is no interrupt request to the CPU.

In FIG. 1, 1 is a local interrupt input unit, 2 is a bus interrupt input unit, and 3 is an interrupt output unit. Reference numeral 11 arranged in the local interrupt input unit 1 is an interrupt request register that holds the local interrupt input to the interrupt control circuit for each level, and 12 is an interrupt mask register that can set whether or not to mask each local interrupt level. is there. Reference numeral 21 is a bus interrupt request register which is arranged in the bus interrupt input unit and holds the bus interrupt input for each level. An interrupt level determination unit 31 arranged in the interrupt output unit 3 determines the highest priority interrupt request from the masked local interrupt request from the local interrupt input unit 1 and the bus interrupt request from the bus interrupt input unit 2. A circuit, 32 receives the output of the interrupt level determination circuit 31, encodes the interrupt level into IRL 0: 2, and outputs it to the CPU. An interrupt level output circuit 33 outputs from the local interrupt input unit 1 and the bus interrupt input unit 2. The interrupt level is monitored, and when there is an interrupt request of the same level and one of the requests is subsequently negated, IRL0: 2 is temporarily set to 7 for the interrupt level output circuit, that is, no interrupt request is sent to the CPU. Edge control circuit that outputs a signal instructing to output (an example of a changing unit) 34 is an edge control designation register for holding one of the information to enable or disable the edge control circuit 33 (an example of the selection means). The edge control designation register 34 can individually designate validity or invalidity of the edge control circuit 33 for each of interrupt request levels 0 to 6.

Next, the operation of the interrupt control circuit configured as described above will be described.

When a single interrupt input is input to this interrupt control circuit, for example, when LIR2 # is asserted, a level 2 interrupt is held in the interrupt input register 11. If a mask is specified for level 2 in the interrupt mask register 12, this level 2
Interrupt input cannot be accepted. But level 2
If no mask is specified for, the level 2 interrupt request is transmitted to the interrupt level determination circuit, it is determined that there is no bus interrupt, and the interrupt request is only level 2 of the local interrupt, and acceptance of the level 2 local interrupt is determined. Then, the interrupt level output circuit 32 is instructed to output the interrupt of level 2. Interrupt output circuit 3
At 2, the level 2 is encoded and 2 is output to IRL 0: 2. The CPU starts the interrupt service when the interrupt level 2 is input. The interrupt factor is
Receive an interrupt acknowledge signal from the CPU or C
When the PU executes the handler for this level 2 interrupt, by negating LIR2 #, the level 2 information held in the interrupt request register 11 is cleared and resolved. Here, the method of eliminating the interrupt factor will not be described in detail.

When a single interrupt request is generated, the operation is the same as that of the conventional interrupt control circuit regardless of the contents of the edge control register 34.

Next, the case where a plurality of interrupts are input to the interrupt control circuit will be described. When only a plurality of local interrupts are input, an interrupt with a low level number and a high priority is first output to the CPU, and an interrupt with a next low priority is output to the CPU. The same applies when multiple bus interrupts are input. Also,
When local interrupts and bus interrupts are mixed and input, if the levels are different, the highest priority is processed first, and if the levels are the same, the local interrupt is preferentially output. These arbitrations are held in the interrupt request register 11, and are processed in the interrupt level determination circuit 31 which receives the local interrupt processed by the interrupt mask register 12 and the bus interrupt held in the bus interrupt request register 21 as inputs.

As an example of multiple interrupt inputs, LIR0
The case where # and BIR0 # are asserted will be described. This state is shown in FIG. In this case, the edge control designation register 34 sets the level 0 to the edge control register 33.
Is set to operate.

First, when the local interrupt LIR0 # is asserted, the interrupt information of level 0 is latched in the interrupt request register 11. Interrupt mask register 1
If the masking of level 0 is not specified for 2, the occurrence of level 0 is transmitted to the interrupt level determining circuit 31, and the interrupt level output circuit 32 outputs 0 to IRL0: 2 to the CPU. Thereafter, the bus interrupt BIR0 # is asserted and the level 0 mask information is latched in the bus interrupt request register 21. The generation of the level 0 interrupt is transmitted to the interrupt level determination circuit 31, but the LI has already been transmitted.
BIR because level 0 interrupt of R0 # is being processed
A 0 level 0 interrupt request is temporarily held.
After that, when the level 0 interrupt of LIR0 # is accepted by the CPU or cleared by the level 0 handler, the level 0 interrupt information latch of the interrupt request register 11 is released.

The edge control circuit 33, which monitors the outputs of the local interrupt input unit 1 and the bus interrupt input unit 2, monitors that the local interrupt LIR0 # is negated and sends the interrupt level output circuit 32 to the CPU. The instruction to negate the interrupt output is output. In response to this signal, the interrupt output circuit 32 temporarily sets IRL0: 2 to 7, and then issues an interrupt request of level 0 which the bus interrupt input unit 2 continues to output to the interrupt level determination circuit 3
When it is received through 1, the interrupt request of level 0 is output again at 0, that is, the interrupt request of IRL 0: 2.

Further, when a level 0 interrupt request by BIR0 # is accepted by the CPU or BIR0 # is negated by the handler, the level 0 interrupt input state latched in the bus interrupt request register 21 is cleared and an interrupt level output is made. Circuit 32 to CP
7 is output to U at IRL 0: 2, that is, no interrupt request is output.

As described above, in this embodiment, a plurality of interrupts of the same level and priorities are defined, and when a plurality of interrupts of the same level occur, the interrupt of high priority is determined and the CPU is notified. When the interrupt control circuit that makes a request accepts or completes the processing of the interrupt output to the CPU by the CPU and the interrupt factor is withdrawn by the interrupt control circuit, the interrupt request with the next highest priority is issued to the CPU. In the case of outputting to the CPU, the means for continuously outputting to the CPU without changing the level, and the interrupt request of the same level to the CPU once after making the interrupt request level no interrupt request
The interrupt control circuit having the means for outputting to U and the means for selecting one of the above-described means has been described.

Example 2. In the interrupt control circuit of the present invention, the edge control designating register 34 for designating the enable / disable of the edge control circuit 33 is shown as an example of the selecting means, but as another example of the selecting means, a signal line is directly applied from the outside. Even if you get the edge generation specification information for each level,
It goes without saying that the interrupt request signal for the same CPU can be controlled.

[0030]

Since the interrupt control circuit of the first invention is configured as described above, when a plurality of interrupts of the same level are input, the interrupt input processed preferentially and the interrupt input are successively processed. An edge can be provided between the interrupt request and a plurality of interrupts can be sequentially processed for the edge sense interrupt level of the CPU.

The interrupt control circuit of the second invention is
Since the selecting means can enable / disable the changing means for temporarily generating a level without an interrupt request to the CPU, it is possible to deal with both level sense and edge sense interrupts, and a dedicated additional circuit is provided for each CPU. It is possible to meet the external interrupt acceptance specification of the CPU.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of an interrupt control circuit of the present invention.

FIG. 2 is a timing chart showing a characteristic operation of the interrupt control circuit of the present invention.

FIG. 3 is a diagram showing an embodiment of a conventional interrupt control circuit.

FIG. 4 is a timing chart showing the operation of a conventional interrupt control circuit.

[Explanation of symbols]

 1 Local Interrupt Input Unit 2 Bus Interrupt Input Unit 3 Interrupt Output Unit 11 Local Interrupt Request Register 12 Local Interrupt Mask Register 21 Bus Interrupt Request Register 31 Interrupt Level Determining Circuit 32 Interrupt Level Output Circuit 33 Edge Control Circuit (Example of Changing Means) 34 Edge control designation register (an example of selection means)

Claims (2)

[Claims] 1. An interrupt control circuit having the following elements: (a) an input unit for inputting a plurality of interrupt requests of the same level; and (b) one of the interrupt requests input by the input unit is selected and externally set to that level. Output means for outputting a corresponding interrupt signal, and (c) a case where the interrupt request corresponding to the interrupt signal output by the output means is canceled,
Changing means for changing the output level of the interrupt signal by the output means for a predetermined period when there is another interrupt request of the same level as the interrupt request to be released among the interrupt requests input by the input means. 2. The interrupt control circuit according to claim 1, further comprising selection means for selectively operating the changing means in the interrupt control circuit.