JPH10302389A - Data processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a processing speed by holding a data time relationship by page unit so as to eliminate the necessity of a management table and reduce a burden placed on a system control unit, dividing regions into page and buffer regions so as to prevent a reduction in memory use efficiency based on page unit processing and effectively utilizing the buffer memory. SOLUTION: For a DRAM 2, by the processing of a data processing circuit 100, pages 0-to (n) are allotted to have constant sizes as page areas, and pages n+1 and after are allotted to have nonconstant sizes as buffering areas. Upon receiving serial data from a digital signal processor 19, a CD-DA interface 6 stores it in a paging area so as to make one block of CD-DA data correspond to one page, and a subcode interface 7 stores it in a buffering area so as to make the subcode data of one frame correspond to one page.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CD-ROM,
The present invention relates to a data processing circuit provided in a player or the like corresponding to a recording medium such as a DR and a CD-DA and processing data read from the recording medium or data to be written in the recording medium.

[0002]

2. Description of the Related Art Data is recorded on a recording medium such as a CD-ROM in a predetermined format for each sector.
In the case of a CD-ROM, the format has a format in which header data, user data, synchronization data, other data, and subcode data are stored in that order.
The above-mentioned subcode data and user data need to maintain a mutual time relationship, but when managing these user data and subcode data in a linear buffer area, it is necessary to separately prepare management table information. (See JP-A-2-310658).

[0003]

However, if the management table information is separately prepared and the system control unit performs necessary control by looking at the table information, the burden of the system control increases, and the speed is increased by 8 times. Or, it is difficult to deal with high-speed processing such as 10 times speed.

In view of the above circumstances, it is a first object of a data processing circuit of the present invention to eliminate the need for a management table by maintaining the time relationship of data in page units and to reduce the load on a system control unit. I do. It is another object of the present invention to eliminate the inefficient use of memory when processing in page units by dividing the page area and the buffer area, and to improve the processing speed by effectively utilizing the buffer area. I do. It is another object of the present invention to suitably perform various processes associated with the above-described page area having a ring structure (see Japanese Patent Application Laid-Open No. 63-177244).

[0005]

A data processing circuit according to the present invention is a data processing circuit for storing data input from the outside in a buffer memory, accessing the buffer memory to process data, and outputting the data to the outside. A plurality of main processing circuits involved in the input / output of the data and the data processing; a page register used as a pointer for each main processing circuit to access an arbitrary page of the buffer memory; An update control unit that performs update control of the page register, and an end page setting unit that sets an end page for accessing the buffer memory as a ring page area;
A memory control unit that uses a memory area after the end page as a buffering area and accesses the buffering area in response to a request from a specific main processing circuit.

According to the above configuration, unit data (for example, data in a sector unit in a CD-ROM) is stored in a page indicated by a page register, so that it is possible to maintain a time relationship of data in a page unit. Become. Therefore, the management table is not required, and the load on the means for controlling the system can be reduced. Here, if all of the buffer memory is handled in page units,
Since the area to be reserved as a page is made larger than the amount of unit data, an unused area is generated in each page, and the memory usage efficiency is reduced by setting more pages. As in the above configuration, it is possible to set an end page, use a subsequent memory area as a buffering area, and perform access control to the buffering area in response to a request from a specific main processing circuit. Thus, the use efficiency of the buffer memory can be improved. In particular, for example, only data of a processed valid portion processed by a certain main processing circuit is transferred to the buffering area, and the processed main data is read out by another main processing circuit for processing or to the outside. By outputting the data, the memory can be effectively used.

Means for arranging, on a buffering area, original data which is a source of specific data constituting subcode data for each unit data during encoding processing, and generating the specific data from the original data; Means for outputting the data of the sub-code data together with other data constituting the sub-code data held in the ring page area. The specific data includes subcode P data and subcode Q data, and the other data includes subcode R to W data.

Here, when the subcode Q data and the subcode P data for each frame (sector) are stored in the subcode Q area in each page of the ring page area,
Since the main processing circuit accesses this frequently, the frequency of access arbitration increases and the processing speed decreases. Focusing on the fact that the subcode P data and the subcode Q data that is time-related information can be automatically generated by giving an initial value, the subcode Q data and the subcode P data are stored in a buffering area. By automatically generating the data from the original data arranged in the master, the access frequency of each master can be reduced.

It is desirable to have an abnormality avoiding means for performing an abnormality avoiding process based on a difference value between each page register. This is because when processing is performed in page units, the processing end time differs in page units for each main processing circuit, so that a page that has not been processed by one main processing circuit is processed by another main processing circuit. This is in order to avoid the situation (abnormal processing).

The abnormality avoiding means includes a difference value calculating means for calculating a difference value between each page register, a setting difference value holding means for holding a setting difference value, and a setting difference value and a setting difference value. The comparing means may include a comparing means and a notifying means for notifying that the abnormality processing is approaching based on the comparison result. Here, in order to avoid the abnormal processing, if the means for controlling the system constantly monitors the value of the page register of each main processing circuit,
The processing by the means responsible for controlling this system becomes complicated,
The burden increases, but with such a configuration, the increase in the burden can be avoided.

[0011] The difference value calculation means may comprise a flag which is inverted each time each page register loops over the ring page area, and means for selecting a difference value calculation formula based on the inversion information of each flag. In the ring page area, for example, assuming that the end page is “100”, the update value of the page register holding “100” is “0” (that is, page 0). Therefore, the difference value cannot be calculated simply by subtracting the value of each page register. Leaving the processing in view of this point to means for controlling the system complicates the processing and increases the load. With such a configuration, the loopback is performed while avoiding the increase in the load. Can be easily dealt with in such a case that the difference value calculation formula differs depending on the presence or absence.

The difference value calculation means may comprise means for selecting a difference value calculation formula based on information indicating whether the state is an encoding state or a decoding state. Since the processing order of each master differs between the encoding state and the decoding state, the difference value calculation formula also differs. Leaving the processing in view of this point to the means for controlling the system complicates the processing and increases the load. With such a configuration, the encoding is performed while avoiding the load increase. It is possible to easily cope with a situation where the difference value calculation formula is different between the state and the decode state.

A main processor capable of accessing both the ring page area and the buffering area has a second page register in addition to a page register used as a pointer for accessing an arbitrary page of the buffer memory. And when the abnormality avoidance means reports an abnormality about the underrun during encoding, the second
Means for writing data indicating invalidity to an area up to the page register. When an underrun occurs (an unprocessed page of a main processing circuit to be read ahead by a main processing circuit to be read ahead) occurs at the time of encoding, for example, an undesired CRC that is not added to the recording medium A situation occurs in which unnecessary data is written. In this case, in the case where rewriting is to be performed on an unrecorded area of the recording medium without discarding the recording medium, it is necessary to determine where the invalid data is. For this reason, data indicating invalidity is prepared in place of the undesired data. Here, if the process of preparing the invalid data is entrusted to the means for controlling the system, the process becomes complicated and the load increases. With such a configuration, this load increase can be avoided. It is possible to easily cope with an increase in processing speed such as 8 × speed or 10 × speed.

It is also possible to provide two or more interrupt input terminals having different levels from each other, and a selecting means for selecting which interrupt input terminal is to receive an interrupt based on the abnormality notification from the abnormality avoiding means. Good. Here, when a plurality of different interrupts can occur, if there is only one interrupt input, the interrupt level cannot be set, so that the interrupt generated at the time of abnormal processing, the interrupt generated at the normal end, Since both are treated the same, and the factors are investigated each time they occur, the processing by means for controlling the system becomes complicated, and the processing time when interrupts are concentrated is increased. With the above configuration, an interrupt level can be given to an interrupt based on the abnormality notification, so that the load on the means for controlling the system can be reduced.

Means for masking an interrupt based on the abnormality notification from the abnormality avoiding means; selecting means for inputting a signal after masking by the masking means or a signal before masking and providing one of them to the status section; May be provided. Here, when performing an arbitrary interrupt process, in order to reduce overhead, there is a case where it is desired to perform the process by polling instead of the cause of the occurrence as an interrupt. In this case, the interrupt is masked. Therefore, the means for controlling the system cannot read the status, so that polling cannot be performed and processing cannot be performed efficiently. According to the above configuration, even when the mask is activated, the signal before the mask is given to the status unit, and the polling process can be performed.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A data processing circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a data processing circuit 100 of this embodiment and its peripheral circuits. The data processing circuit 100 includes a system controller (System
Controller) 17, AT attachment (ATA) 1
8, and a digital signal processor (DSP) 19
Are connected to DR and the buffer memory DR.
Signal writing and reading processes are performed with AM2. The data processing circuit 100 includes various masters (main processing circuits, specific names and functions of which will be described later) 3 to 7, a buffer manager 16 and a DRAM controller 1.
It is provided with.

The system controller 17 controls the data processing circuit 100 and is a master system controller interface (System Controller).
oller if) 3 to send and receive data. The AT attachment forms a host bus, and sends and receives data to and from a master host interface (Host if) 4. Digital signal processor (DS
P) 19 is an EFM (Eight-Fourteen Modul) not shown.
)) Divides the data sent from the processing unit into CD-DA data and subcode data, and divides the CD-DA data into the master CD-DA interface 6 and converts the subcode data into the master subcode interface (Subcode
if) 7 is given as serial data (at the time of decoding), while CD given from CD-DA interface 6
-The combination of the DA data and the subcode data provided from the subcode interface 7 is sent to the EFM processing unit.

The DRAM 2 includes a data processing circuit 100
As shown in FIG. 2, the paging area (Paging area) and the buffering area (Buffer
ingarea). Pages 0 to n (constant size) are assigned to the paging area, and pages n + 1 (constant size) and subsequent pages are set as buffering areas. Each page has a CD-
Various data for one sector in a recording medium such as a ROM or a CD-DA can be stored. The details of FIG. 2 will be described later.

The system controller interface 3 serving as a master stores data transferred from the system controller 17 in a system buffer page (SysBufPag).
e) Perform processing such as transfer to the area of one page indicated by the numerical value stored in 8.

The master sector processor (Se)
The ctor processer 5 is a processing block for performing, for example, EDC (error correction) / ECC (error detection) processing of CD-ROM data, and is represented by a numerical value 1 stored in a sector processor buffer page (SPBufPage) 11. The processing is performed on the data stored in the area of the page.

The CD-DA interface (CD-DA if) 6 serving as a master is provided with a digital signal processor 19.
From the serial data sent from the CD buffer page (CDBufPage) 12
Processing such as storing in a page is performed. At the time of storage, if the data is CD-ROM data, a sync pattern of one block is detected, and control is performed so that one block corresponds to one page.

A subcode interface (Subcode if) 7 serving as a master converts serial data for subcode input from the digital signal processor 19 into one page indicated by a numerical value stored in a subcode buffer page (SubBufPage) 13. And the like. At the time of storage, a sync pattern of subcode data is detected for each frame, and control is performed so that one frame corresponds to one page.

The master host interface (Host if) 4 is connected to the AT attachment 18 or SC
Processing such as transferring data transferred from the host bus such as SI to one page indicated by a numerical value stored in the host buffer page (HostBufPage0) 9a is performed for each sector. The host can access a buffering area (Buffering area) described later. The host buffer page (HostBufPage) indicates the page.
1) It has 9b. However, this host buffer page (HostBufPage1) 9b is not necessarily used to indicate only the page in the buffering area, but is also used for the processing of FIG. 13 described later.

Buffer Manager 1
Reference numeral 6 denotes a page controller (Page control) 14 connected to each of the masters 3 to 7, and various page registers (specific names will be described later) 8, 9a, and 9
b, 11 to 13, masters 3 to 7 and an address generator (Address generate) 15 connected to a page register corresponding to each of them, and a ring end page storing a ring end page (n in the example of FIG. 2). (RingEndPage) The storage unit 10 comprises a storage unit 10 for arbitrating access from the masters 3 to 7 and a DRAM.
Address for controller 1 (Current address)
Is generated. Specifically, each master issues an access request to the buffer manager 16 by expressing a request (req). When requests from the masters overlap, arbitration is performed by priority control, and an acknowledgment signal (ack) is returned to one master to perform data access therewith. Further, each master can notify the update request of the page register by expressing the addition (inc). Each page controller 14 receiving this update request updates each corresponding page register with reference to the ring end page stored in the ring end page storage unit 10.

The DRAM controller 1 is connected to the masters 3 to 7 by data lines, and responds to a request from the buffer manager 16 by a DRA.
Various signals and addresses for controlling the M2 are generated, and data is exchanged with the master that has made the request. Note that 8-bit data transfer is performed with the system controller interface 3 and 16-bit data transfer is performed with the other masters 4 to 7.

FIG. 2 is an explanatory diagram showing how each master accesses buffer data. Each master
Manage the data currently being processed in page units. DRAM
Buffer RAM configuration of page 2
To page n (n is the value of the ring end page) is a paging area, and the area indicated by pages n + 1 to the last (mounting memory last) page is a buffering area (Buffering area). You. Whether each master can access only the paging area, or both the paging area and the buffering area, and whether there is a difference between decoding and encoding when both can be accessed, are described in Table 1 below. Shown in Here, the master, which can access only the ring page, processes page 0 after the processing up to page n is completed. The processing for that is performed by the page register corresponding to the master. On the other hand, a master having access to the buffering area can process page n + 1. FIG. 2 shows a state at the time of decoding, and the CD-DA interface 6 and the subcode interface 7 write data read from the recording medium in the order of pages 0, 1, 2,. ), The sector processor 5 sequentially accesses pages 0, 1,..., Which are already written data, reads out the data, corrects the error, and returns to the page (in the drawing, the page 1 is being processed). , AT Attachment 18
Indicates a state in which page 0 is accessed via host interface 4 to receive corrected data.

FIG. 3A shows a buffer RAM configuration in the DRAM 2, FIG. 3B shows a data format in a page in the case of a CD-ROM, and FIG.
FIG. 4 is an explanatory diagram showing a data format in a page in the case of D-DA. A 3072-byte amount is allocated to each page, and user data and subcode data are stored. The data amount occupying each page is smaller than the size of the page, and 288 bytes are generated as an unused area in the figure. The subcode data uses 96 bytes and consists of data represented by symbols such as P, Q, R, S, T, U, V, and W, the details of which will be described later.

Table 1 below clarifies offsets and access areas of each master and the like.

[0030]

[Table 1]

FIG. 4 is a flow chart showing the contents of the page register update control in the page controller 14, and shows a case where the master is the CD-DA interface 6. After the initial setting (step 1), it is determined whether there is a page register update signal (Inc) from the master (step 2).
It is determined whether the current CD buffer page (CDBufPage) is smaller than the ring end page (RingEndPage) (step 3). If it is smaller, 1 is incremented and the process proceeds to step 2. On the other hand, if not smaller, the CD buffer page (CDBufPage) is updated to 0 (ie, 0x000), and the CD buffer flag (CDBufFlg) is toggled (0 →
1, 1 → 0). The toggle state of the CD buffer flag is used in a difference calculation described later with reference to FIG.

FIG. 5 shows a system controller interface (System Controller if) 3 as an example of a master, and a corresponding system buffer page (SysBufPa).
FIG. 2 is a block diagram illustrating a connection relationship between the DRAM controller 1 and the address generator 15 and the address generator 15.
A [11: 0] in the figure is address information (information indicating a specific address in a page) given from the system controller interface 3 to the buffer manager 16, and D [7: 0] is a data line from the system controller interface 3. Data supplied to the DRAM controller 1 through the The DRAM is obtained by adding the upper 13 bits of address information (address specifying the page) of the system buffer page (SysBufPage) 8 and the 12-bit address of A [11: 0] as shown in the figure.
2 to generate a 24-bit address for accessing. The request control unit 3a of the system controller interface 3 sends the access signal (CS1B, REB, WE
A request (Req) signal is generated based on
Access the AM controller 1. The other masters are similarly configured.

FIG. 6 is an explanatory diagram showing a signal flow when the decoding processing is executed in the data processing circuit of FIG. In this decoding process, the data read from the recording medium is supplied to the data processing circuit 100 via the DSP 19 as a CD-DA input and a subcode input, and is supplied to the AT attachment 18 via the data processing circuit 100 and the DRAM 2. Can be The data (approximately 3 Kbytes) is synchronized with the block synchronization signal (BSYNC) in synchronization with the page indicated by the CD buffer page (CDBufPage) and the subcode buffer page (SubBufPage).
(A) and (b) in FIG.
(See (c), (d) and (e)). The sector processor buffer page (SPBufPage) is a CD buffer page (CDBu) because the sector processor (Sector Processer) performs error detection processing and the like using the already written data.
fPage) holds a value corresponding to a page before the page indicated by (see (f) and (g) in the figure). Since it is only necessary to avoid catching up, it does not matter how long it is before, and the control relating to this will be described later.

The system controller interface (System Controller if) stores a necessary portion (for example, about 2 Kbytes) of the data processed by the sector processor (Sector Processor) in a buffering area (Buffering area). I do. Therefore, the sector processor buffer page (SPBufP
age), the read operation is performed with the value corresponding to the page before the page indicated by the buffering area (Bufferin
A write operation of a necessary portion of the processed data is performed on the (n + 1) th page of the (g area) (see (h) and (i) of FIG. 11).
The host interface (Host if) takes out the corrected data stored in the buffering area (Buffering area) and supplies the corrected data to the AT attachment 18 by using a transfer counter (a transfer number set in the host page control unit 14). Will be) and HostBufPage1
(At the time of decoding, the processed data is read from the (n + 1) th page in the buffering area at the transfer start address specified by the transfer start address specified by the buffering area. reference). When each master finishes the process for the page, it outputs an addition (inc) signal to cause each page controller 14 to perform a page update process.

FIG. 7 is an explanatory diagram showing a signal flow when an encoding process is executed in the data processing circuit of FIG. In this encoding process, the AT attachment 1
8 is a data processing circuit and DRA
The signal is supplied to the DSP 19 (EFM encoder) via M2. The host interface (Host if) 4 transfers the data to the page indicated by the host buffer page (HostBufPage0) (see FIGS. 3A and 3B). In addition,
Other masters are ESFS (Encode Subcode Frame Synchronization), which is one sector processing unit output from the CD encoder.
Control is performed so as to complete the process in page units for each c) (see FIG. 9E). Sector processor (Sector
Processer) 5 performs a parity addition process using the data already written by the host interface 4.
Sector processor buffer page (SPBufPage)
Holds a value corresponding to a page preceding the page indicated by the host buffer page (HostBufPage0) (see (c) and (d) in FIG. 3).

Then, the CD-DA interface 6 provides a sector processor buffer page (SPBufP) so as to supply the data processed by the sector processor (Sector Processor) to the DSP 19 (EFM encoder).
age) CD corresponding to the page before the page indicated by
A read operation is performed based on the value of the buffer page (CDBufPage) (see FIGS. 3F and 3G). Note that Trn 0,
Trn 1... Are data respectively corresponding to CD-ROM sectors. Subcode interface (Subcode
if) 7 is also the same as the sector processor (Sector Pro)
cesser), the subcode buffer page (SubBufPag) corresponding to the page preceding the page indicated by the sector processor buffer page (SPBufPage) in order to provide the data processed by the DSP 19 (EFM encoder).
A read operation is performed using the value of e) (see FIGS. 7H and 7I). .., Trn 0, Trn 1,... Are data corresponding to 96 bytes of the subcode frame.

In the EFM encoder, the CD data and the subcode data are EFM together, converted into serial data, and output to a laser pickup (not shown) as write data to a recording medium.

As described above, the buffer RAM configuration is divided into the paging area (Paging area) and the buffering area (Buffering area), and the data required by the AT attachment (stored in the original page) is stored in the buffering area during decoding. Since the stored amount (about 3 Kbytes → about 2 Kbytes) is smaller than the stored amount, the memory utilization efficiency can be significantly improved.

Here, at the time of encoding, the data given from the AT attachment 18 is stored in a predetermined page in the buffer RAM of the DRAM 2, and each master accesses the page and sequentially processes the page.
Data to be supplied to the encoder is serially output. At this time, all of the subcode data are stored in each page together with the user data as the main data. The subcode data is P,
It consists of data represented by symbols such as Q, R, S, T, U, V, W.
It is time-related information and can be automatically generated,
This subcode Q data is stored in a paging area (Paging a
In order to generate a page in rea), the page must be accessed frequently, and the frequency of access arbitration between masters increases, thereby reducing the processing speed. Further, in a configuration requiring a circuit for storing the subcode Q data in a page, the circuit becomes complicated. Also, the subcode P
The data is information on the interval between music pieces, which is either 1 or 0 in a subcode (96 bytes) in one sector, and can be automatically generated. Frequent access is required to store data, and the frequency of access arbitration between masters increases, thereby reducing the processing speed. Further, in a configuration requiring a circuit for storing the subcode P data in a page, the circuit becomes complicated.

Therefore, a method for utilizing the buffering area during encoding will be described. FIG. 8 shows an example in which the original data of the subcode Q data and the subcode P data of the subcode data is automatically generated on the buffering area (this is called automatically generated data, and in FIG. FIG. 7 is an explanatory diagram showing a configuration in which this automatically generated data is sometimes serially output together with another subcode portion. As the automatically generated data, Cont / Adr that gives meaning to each group (TNO, INDEX, etc.), for example, TNO that carries information such as the track number of the first song, INDEX that carries predetermined information, and relative time (RMIN) , RSE
C, RFRAME), ZERO, absolute time (AMIN,
ASEC, AFRAME), MODE, Repeat,
It consists of POINT and PMSE. One second is 75 frames (sectors). The absolute time can be automatically generated after the start time is determined, and the relative time can be automatically generated after the initial value is determined.

The details of the automatic generation will be described with reference to FIGS. 9A shows the configuration of a buffer RAM, FIG. 9B shows the configuration of one page, FIG. 9C shows the configuration of a buffering data area for subcode, and FIG. Shows automatically generated data, and FIG. 4E shows subcode data in a page. FIG. 10A shows the subcode data in the page as in FIG. 9E, FIG. 10B shows the automatically generated data as in FIG. 9D, and FIG. FIG. 8 is a diagram showing an output data configuration in which automatically generated data is incorporated in another subcode portion (P, RW or RW).

(Generation of Subcode Q Data) The subcode Q data for each frame is generated by the automatically generated data 30. The automatically generated data 30 is 16 bytes (Offse
t 0x00 to 0x0F). Since FIG. 8 shows the time of encoding, FIG.
The areas of 0x0A and 0x0B related to CRC are omitted.

The RTIM counter 31, ZERO counter 32 and ATIM counter 33 have load
= 1 (predetermined bit in 8-bit data stored in MODE is 1), Offset 0x03 to 0x09
The data of (RMIN to AFRAME) is stored as an initial value. On the other hand, when load = 0 (predetermined bit in 8-bit data stored in MODE is 0), MODE
Is incremented / decremented for each frame depending on whether a predetermined bit of the 8-bit data stored in the. When Repeat = 0 in the Repeat decremented for each frame, processing is performed on automatically generated data in the buffering area (Buffering area) indicated by n (ring end page) +1 and POINT (see FIG. 9). ). In addition,
The initial value of POINT is 0.

The selector 34 has a RTIMselect function.
When = 1 (the predetermined bit in the 8-bit data stored in MODE is 1), the value of the RTIM counter 31 is selected, and this is output as constituting the encode sub-Q data 37.

The selector 35 is ZEROselect.
When = 1 (the predetermined bit in the 8-bit data stored in MODE is 1), the value of the ZERO counter 32 is selected and output as constituting the encoded sub Q data 37.

The selector 36 has ATIMselect.
When = 1 (the predetermined bit in the 8-bit data stored in MODE is 1), the value of the ATIM counter 33 is selected and output as constituting the encode sub-Q data 37.

Then, for each frame, the encoding sub Q
The data 37 is latched, and the CRC calculator 39 calculates and adds a CRC 38 to the latched data.

(Generation of Subcode P Data) The subcode P data is stored in a buffering area (Bu
automatically generated data 30 stored in the ffering area)
Generated by the or paging area (Paging
generated by the data stored in area). Specifically, the selector 43 that outputs the subcode P data
Is, when use PMSB = 1 (predetermined bit in 8-bit data stored in MODE is 1), PMSB (7
Bit) is output as encoded sub-P data,
When use PMSB = 0 (predetermined bit in the 8-bit data stored in MODE is 0), the value of P stored in paging area 45 (selected by selector 44) is output as encoded sub-P data I do.

The other subcode data (R to W) is EF
Request from M encoder 40 (ESUBREQ
According to the value of the offset counter 41 counted for each B), selectors 42 and 44 select from among 96 bytes. The selected one byte is output to the EFM encoder 40 as encoded subcode serial data.

As described above, even at the time of encoding, the sub-code P
Data and subcode Q data are automatically generated, and such automatically generated data is added to other subcode data when serially output to the EFM encoder. Therefore, subcode P data and subcode Q data are stored in a paging area. In this case, it is possible to avoid a reduction in processing speed and a complicated circuit configuration.

As described above with reference to FIGS. 6 (at the time of decoding) and FIG. 7 (at the time of encoding), after a certain master processes a certain page, another master processes the corresponding page. In addition, since the processing order is determined, it is not allowed that the processing page of the other master catches up with the processing page of the certain master. On the other hand, since each master advances the processing at its own timing, the page is automatically updated at the timing. Therefore, the data processing circuit 100 includes
A detection circuit 500 (see FIG. 11) for examining the page register and detecting the possibility of catching up is provided.

The points to be considered here are that the processing order between the two masters is reversed between the time of encoding and the time of decoding, and that the paging area (Paging area) adopts a ring buffer configuration. Regarding the point that the ring buffer configuration is adopted, each flag (CDBuf in FIG.
Flg only, but also SPBufFlg and H
There is stBufFlg. ) State is useful. For example, focusing on the host buffer page (HostBufPage0) and the CD buffer page (CDBufPage), the CD buffer page (CDBufPage) has the preceding value at the time of decoding, and CDBufFlg and HstBufF.
If lg indicates the same state, the difference can be obtained by subtracting as it is (see FIG. 12A).
On the other hand, if either flag is inverted, for example, CD
Assuming that ring wrapping occurs in the buffer page (CDBufPage), subtract the value of the host buffer page (HostBufPage0) from the value obtained by adding the value of the ring end page (RingEndPage) to the value of the CD buffer page (CDBufPage). (See FIG. 12B).

FIG. 11 is a circuit block diagram of the detection circuit 500. The sequencer (PAGETIM) 55 is a functional block for performing arithmetic control, and each of the flags (Fl
g) and the encode / decode identification signal (ENC
/ DECB) Selector (4 to 1 mux × 2) 53 so as to select two sets of page registers for performing the difference operation
To the select signal. Further, a calculation method is determined, and information indicating the calculation method is stored in a calculation unit (13-bit Sub /
Adder) 54.

The selector 53 has a CD buffer page (CD
BufPage), Sector Processor Buffer Page (SP
BufPage) and host buffer page (HostBufPage0) are selected and output based on the select signal. The ring end page (RingEndPage
) Is input in order to add the value of the ring end page to the value of the predetermined buffer page when the ring is turned back.

The arithmetic unit 54 receives the two buffer page values output from the selector 53 and executes a predetermined difference calculation process based on the information indicating the arithmetic method.
The difference value is given to a comparator (Comparator) 51.

The selector (2 to 1 mux) 50 selects one of the value of the overrun page (maximum 7) and the value of the underrun page (maximum 7) and supplies it to the comparator 51. Overrun means, for example, in decoding, when the CD-DA interface, which should precede, is too premature, and writes to the untransferred page of the host, which should be followed in a folded state,
The underrun refers to, for example, in decoding, a case in which a host, which is to follow, reads an unprocessed page of a sector processor, which is to precede.

The comparator 51 compares the value of the overrun page or the value of the underrun page with the difference value of the arithmetic unit 54, and gives the comparison result to the interrupt control unit 52.

The interrupt controller 52 generates an interrupt signal for the system controller based on the result of the comparison.

When an interrupt occurs, the CD-DA interface (CD
-DA if), Sector Processe
r), the operation of the host interface (Host if), and the conditions for determining the occurrence of an interrupt are shown in Table 2 below.

[0060]

[Table 2]

If a plurality of arithmetic units are provided to perform various calculations related to the condition setting shown in Table 2 above, the circuit configuration becomes complicated. However, as shown in the circuit configuration of FIG.
A single arithmetic unit 54 is provided, and a sequencer (PAGETI
M) Since the necessary calculations are performed at the required timing by the time division under the control of 55, the circuit configuration can be simplified as compared with the case where a plurality of arithmetic units are provided.

Here, at the time of encoding, since the CD-DA interface is involved in the process of writing to the recording medium, it is not possible to wait for the process of another master to process a given page until the process is completed. . That is, the occurrence of an underrun interrupt in which the CD-DA interface reaches the unprocessed area of the sector processor means that data to be written on the recording medium cannot be prepared. Therefore, it is necessary to prepare some data as write data to the recording medium. Therefore, control is performed so that, for example, 0x000 (0 Fill) indicating invalid data is written instead of the data to be written. How much to write depends on the contents of the host buffer page (HostBufPage1). Here, the area to which data is to be written is transferred from the host (AT attachment) in advance, and its size is known, so that the last page corresponding to this size can be known from the calculation. If an error notification for an underrun is issued during writing to the last page and 0x000 is written, the last page may be set as the host buffer page (HostBufPage1). That is, the value of the host buffer page (HostBufPage1) can be determined when the data is determined at the start of writing.

In Table 2, “HostBufPage0 to Ho
0 Fill for the area specified by TFMT (transfer format) up to stBufPage1-(minus) 1 "
And Here, the host transfers continuous data without worrying about page breaks. The structure of the continuous data can be specified by TFMT (there is a bit string for performing the specification). 0
When performing Fill, it is sufficient to perform only the portion corresponding to the main data (user data) regardless of the subcode.
This is performed only for the portion corresponding to the main data specified by the TFMT.

FIG. 13 is a flowchart showing the control contents for this. When an underrun interrupt occurs (step 10), the process proceeds to an interrupt process (step 1).
1) First, the page indicated by HostBufPage0 is HostBufPage1
It is determined whether the page is larger than the page indicated by (step 1)
2). If the page indicated by HostBufPage0 has not reached the page indicated by HostBufPage1, the write data (HostBufWri
teData) is 0x000, and 1 indicated by HostBufPage0
Transfer to a page (step 13). Then, after the transfer is completed, HostBufPage0 is incremented (step 1).
4) Go to step 12. When the page indicated by HostBufPage0 is one page before the page indicated by HostBufPage1, the process exits from the underrun interrupt process.

FIG. 14 shows an interrupt generation circuit 60 including a circuit 500 composed of the circuit of FIG. 11 described above, and an overrun interrupt and an underrun interrupt generated by the interrupt generation circuit 60 are transmitted to the system controller. This circuit is responsible for controlling whether to actually give or to give priority in relation to other interrupts even if given. Each interrupt output from the interrupt generation circuit 60 is input to one input gate of each of AND circuits 62 and 63. The other input gates of the AND circuits 62 and 63 receive information (0/1) from the mask setting circuit 61 as to whether or not to perform masking. Outputs of the AND circuits 62 and 63 are output from selectors 66 and 67.
Grp0 and Grp1 depending on the setting of IntGrpSel0 or IntGrpSel1
And divided into Grp0 and Grp1 are OR circuits 6
9, and 70 are output as Int0 and Int1.

Here, when a plurality of different interrupts occur, if there is only one interrupt input, the level cannot be set for the interrupt. Therefore, an interrupt that occurs at the time of abnormal processing and an interrupt that occurs at the time of normal termination are treated the same, and the factor is investigated every time an interrupt occurs. This complicates the processing in the system controller and increases the processing time when interrupts are concentrated. As described above, IntGrp is selected by selectors 66 and 67.
Since the configuration is made so that Grp0 and Grp1 can be divided by setting Sel0 or IntGrpSel1, it is possible to improve the processing speed and simplify the processing without the need for factor investigation.

In FIG. 14, the AND circuit 6
The signal before the AND operation and the signal after the AND operation are given to selectors 64 and 65, respectively.
Either one is selected according to the setting of the sSrc signal, and is output to the status 68.

Here, when processing an arbitrary interrupt, there is a case where it is desired to process the cause of occurrence by not policing but policing in order to reduce overhead. If the interrupt and the underrun interrupt are masked, the system controller cannot perform polling processing. As described above, even if the mask is set, the polling process can be performed without generating an interrupt by acquiring the information before the mask in the status 68, and the processing efficiency is improved. Become.

[0069]

As described above, by maintaining the time relationship of data on a page-by-page basis, a management table becomes unnecessary and the load on the system control unit can be reduced. In this way, the inefficient use of memory when processing is performed on a page-by-page basis can be solved by dividing the memory into a page area and a buffer area, and the processing speed can be improved by effectively utilizing the buffer area. Further, there is an effect that various processes associated with the above-described page region having the ring structure can be suitably performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a data processing circuit of the present invention and its peripheral circuits.

FIG. 2 is an explanatory diagram showing a configuration of a buffer RAM of the present invention.

FIG. 3 is an explanatory diagram showing a format of each page according to the present invention.

FIG. 4 is a flowchart showing the contents of page update control according to the present invention.

FIG. 5 is a block diagram showing a relationship between a request section of a system controller interface, a DRAM controller, and a buffer manager according to the present invention.

FIG. 6 is a diagram showing a signal flow at the time of decoding according to the present invention.

FIG. 7 is a diagram showing a signal flow at the time of encoding according to the present invention.

FIG. 8 is an explanatory diagram showing a state of generation of subcode P and Q data according to the present invention.

FIG. 9 mainly shows a buffering area (Buffer) of the present invention.
FIG. 2 is an explanatory diagram showing a configuration.

FIG. 10 is an explanatory diagram showing how the generated subcodes P and Q data of the present invention are combined with other data.

FIG. 11 is a block diagram illustrating a detection circuit that performs notification of overrun or underrun according to the present invention.

FIG. 12 is an explanatory diagram showing an overrun determination formula in the case where there is no wrapping of the ring page area and in the case where there is wrapping during decoding according to the present invention.

FIG. 13 is a flowchart showing the contents of processing for underrun during encoding according to the present invention.

FIG. 14 is a block diagram of a circuit for processing or masking a notification of an overrun or underrun by a two-level interrupt according to the present invention;

[Explanation of symbols]

1 DRAM controller 2 DRAM 3 System controller interface (System
Controller if) 4 Host interface (Host if) 5 Sector processor (Sector Processer) 6 CD-DA interface (CD-DA if) 7 Subcode interface (Subcode if) 8 System buffer page (SysBufPage) 9a Host buffer page (HostBufPage0) 9b Host buffer page (HostBufPage1) 10 Ring end page (RingEndPage) 11 Subcode buffer page (SubBufPage) 12 CD buffer page (CDBufPage) 13 Subcode buffer page (SubBufPage) 14 Page controller 15 Address generator 16 Buffer manager 17 System controller 18 ATA 19 DSP

Claims (9)

[Claims] 1. A data processing circuit for storing data input from the outside in a buffer memory, processing the data by accessing the buffer memory, and outputting the data to the outside, the data processing circuit being involved in the input / output of the data and the data processing. A plurality of main processing circuits, a page register used as a pointer for each main processing circuit to access an arbitrary page of the buffer memory, and an update control unit for performing update control of the page register according to an instruction of each main processing circuit. When,
End page setting means for setting an end page for accessing the buffer memory as a ring page area; and using a memory area subsequent to the end page as a buffering area, wherein the buffer is used in response to a request from a specific main processing circuit. A data processing circuit comprising: memory control means for accessing a ring area. 2. A means for arranging, on a buffering area, original data which is a source of specific data constituting subcode data for each unit data during encoding processing, and generating the specific data from the original data; 2. The data processing circuit according to claim 1, further comprising means for outputting the specific data together with other data constituting the subcode data held in the ring page area. 3. The data processing circuit according to claim 1, further comprising abnormality avoiding means for performing abnormality avoiding processing based on a difference value between each page register. 4. The abnormality avoiding means includes: a difference value calculating means for calculating a difference value between respective page registers; a setting difference value holding means for holding a setting difference value; and the calculated difference value and a setting difference value. 4. The data processing circuit according to claim 3, further comprising: means for comparing the data and a notification means for notifying that the abnormality processing is approaching based on the comparison result. 5. The method according to claim 1, wherein the difference value calculating means includes a flag which is inverted each time the page register loops back the ring page area, and means for selecting a difference value calculating formula based on the inversion information of each flag. The data processing circuit according to claim 4, wherein: 6. The apparatus according to claim 4, wherein said difference value calculation means includes means for selecting a difference value calculation formula based on information indicating whether the state is an encoding state or a decoding state.
2. A data processing circuit according to claim 1. 7. A main processing circuit capable of accessing both the ring page area and the buffering area may further include a page register used as a pointer for accessing an arbitrary page of the buffer memory. A page register, and a means for writing data indicating invalidity to an area from the page register to the second page register when an abnormality about the underrun is reported from the abnormality avoiding means during encoding. 7. The data processing circuit according to claim 3, wherein: 8. An input device comprising two or more interrupt input terminals having different levels from each other, and selecting means for selecting which interrupt input terminal to input an interrupt based on the abnormality notification from the abnormality avoiding means. 8. The data processing circuit according to claim 3, wherein: 9. A means for masking an interrupt based on an abnormality notification from the abnormality avoiding means, and a selection for inputting a signal after masking by the masking means or a signal before masking and giving one of the signals to the status unit. 9. The data processing circuit according to claim 3, further comprising: