JPH10334586A - Signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lighten a processing burden of a system controller at the time of reading out data recorded on an optical disk. SOLUTION: When a target sector address for showing a sector to be started for its read-out is set in a target sector register 21, and a read-out starting command is issued, the signal processing circuit is operated as follows. A decoded data obtained by specifically decoding a data read out of the optical disk is received, and a sector address in this data is secured and stored in a read-out sector register 22a, and then this sector address stored in the read-out sector register 22a is compared with the target sector address (in the case of no erroneous detection). This comparison is performed whenever a sector address is secured from a decoded data, and as a result of a comparison, when both sector addresses coincide with each other, an access request for starting storing the decoded data into a buffer memory is issued to a buffer management part 12, and is also advised to the system controller.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit used in an information processing apparatus using an optical disk, and more particularly, to reading information recorded on an optical disk.

[0002]

2. Description of the Related Art FIG. 1 shows a compact disk (CD) (C
ompact Disk), compact disk ROM (CD-RO)
M) (Compact Disk-Read Only Memory), write-once compact disc (CD-R) (Compact Disk-Recordabl)
e), CD rewritable (CD-RW) (Compact Disk-R)
ewritable), Digital Video Disc (DVD) (Digit
FIG. 2 is a functional block diagram showing a configuration example of a conventional CD-ROM device for reading data from an optical disk such as an alVideo Disk together with a host computer 55. However, parts unnecessary for the description of reading data from the optical disk are omitted. This CD-ROM device includes a disk reading section 50, a CD decoding section 51, a buffer memory 52, a signal processing circuit 53, and a system controller 54.
And a host computer (hereinafter referred to as “host”) 55 is connected to the signal processing circuit 53. Host 5
Reference numeral 5 denotes a personal computer (personal computer). When a host 55 requests reading of data from an optical disk, a signal processing circuit 53 operates under the control of a system controller 54, and data to be read is stored in an optical disk. Read by the disk reading unit 50 from the CD
After predetermined decoding is performed by the decoding 51, once
The signal is stored in a predetermined area of the buffer memory 52 by the signal processing circuit 53. Hereinafter, operations from reading data to the optical disk to storing data in the buffer memory 52 when a data reading request is received from the host will be described.

[0003] Data recorded on an optical disc is first read by a disc reading section 50, and then, by a CD decoding circuit 51, EFM (Eight to Fourteen Modul).
)) and CIRC (Cross Interleave)
Predetermined decoding including error correction by Reed-Solomon Code) is performed, and the decoded data (hereinafter, referred to as “decoded data”) is input to the signal processing circuit 53. The signal processing circuit 53 has a CD interface unit inside,
The CD interface receives the decoded data from the CD decode circuit 51. Then, while storing the sector address of the received decoded data in a predetermined register provided for storing the sector address,
The system controller 54 is notified by an interrupt that the contents of the register have been updated. The system controller 54 holds, as a target sector address, a sector address at which reading is to be started based on a data read request from the host 55, and upon receiving the notification from the CD interface unit, the register in the signal processing circuit 53. Is compared with the target sector address. Then, based on this comparison, the system controller issues a reading start command to the signal processing circuit 53 before the number of sectors ready to start reading. Upon receiving the read start command, the signal processing circuit 53 prepares for data capture, detects a sector synchronization signal (hereinafter referred to as a “sync pattern”) from the decoded data input from the CD decode circuit 51, and The operation of storing the decoded data in the buffer memory 52 is started.

In the process of starting the storage of the decoded data in the buffer memory 52 based on the target sector address in this manner, the C in the signal processing circuit 53
The D interface unit stores the sector address for the decoded data in the register as described above, and also stores the error flag for the sector address in the internal register. System controller 54
Reads the error flag for the sector address stored in the register when referring to the register, determines whether the sector address is reliable, and determines that the sector address is not A reading start command is issued by performing processing such as complementation and retry of a read operation.

[0005]

SUMMARY OF THE INVENTION As described above, the conventional C
In the D-ROM device, when data reading from the optical disk is started, an interrupt occurs to the system controller 54 every time the register storing the sector address is updated. Therefore, the system controller 54 has to process the interrupt for each sector to manage the sector address information, so that the management is very complicated. In order to accurately start reading (storage in the buffer memory 52) from the target sector address, a reading start command is issued to the signal processing circuit 53 before the number of sectors ready to start reading. It is necessary to pay attention to the timing at which the system controller 54 issues a read start command.

[0006] In recent years, with the improvement of the processing capability of personal computers, there has been a demand for an improvement in the processing capability of a CD-ROM device as a peripheral device thereof. Processing digital data has become commonplace. When processing at several times, for example, 12 times, the reproduction speed of audio data (1/75 second per sector), the system controller 54
The above processing (management of sector address information by interruption and control of the signal processing circuit 53) must be performed within 1/900 second per sector, and a high processing capability is required for the system controller 54. As a result, a high-performance CPU (C
entral Processing Unit), and this is a CD-
This is a factor that increases the cost of the entire ROM device.

Therefore, in the present invention, it is necessary to reduce the processing load on the system controller when reading data recorded on the optical disk, and to pay attention to the timing of issuing a read start command from the system controller as in the prior art. It is an object of the present invention to provide a signal processing circuit having no signal.

[0008]

A first signal processing circuit according to the present invention, which has been made to solve the above-mentioned problems, performs a predetermined decoding on data recorded on an optical disk. Decod- ing means for outputting data, system control means for determining a target sector address indicating a sector from which reading is to be started on the optical disc and issuing a control instruction, and buffer memory for temporarily storing data. Signal processing circuit, when a predetermined control command is issued from the system control means,
A signal processing circuit for storing predetermined data in the decoded data in the buffer memory based on the control instruction; an address obtaining means for sequentially obtaining a sector address from the decoded data; Holding means, and when the predetermined control command is issued, comparing means for comparing a read sector address, which is a sector address sequentially obtained by the address obtaining means, with the target sector address held in the holding means,
When the comparison result by the comparison means indicates that the read sector address matches the target sector address, storage control means for starting storage of the predetermined data in the decoded data in the buffer memory is provided.

In a second signal processing circuit according to the present invention, in the first signal processing circuit, the address obtaining means obtains a sector address from header information in main data included in the decoded data. Features.

[0010] A third signal processing circuit according to the present invention, in the second signal processing circuit, a flag obtaining means for obtaining an error flag for header information in main data included in the decoded data; Indicates that there is an error in the header information,
Supplementing means for supplementing a correct value for the read sector address obtained from the header information, wherein the comparing means, when the error flag indicates that the header information has an error, It is characterized in that a read sector address obtained by the complementing means is compared with the target sector address instead of the obtained read sector address.

In a fourth signal processing circuit according to the present invention, in the first signal processing circuit, the address obtaining means obtains a sector address from SUBQ data in subcode data included in the decoded data. It is characterized by.

In a fifth signal processing circuit according to the present invention, in the fourth signal processing circuit, a check means for determining whether there is an error in the SUBQ data by performing a cyclic redundancy check on the SUBQ data. And the SUB
If it is determined that there is an error in the Q data, the SUB
Complementing means for complementing a correct value for the read sector address obtained from the Q data, wherein the comparing means comprises:
When it is determined that there is an error in the SUBQ data,
It is characterized in that a read sector address obtained by complementing means is compared with the target sector address instead of a read sector address obtained from the SUBQ data.

In a sixth signal processing circuit according to the present invention, in the first signal processing circuit, the address obtaining means obtains a sector address from header information in main data included in the decoded data. Acquiring means for acquiring a sector address from SUBQ data in subcode data included in the decoded data;
Acquiring means for changing one of a sector address acquired by the first acquiring means and a sector address acquired by the second acquiring means based on a predetermined control command issued from the system control means to the read sector address. And selecting means for selecting as.

In a seventh signal processing circuit according to the present invention, in any one of the first to sixth signal processing circuits, as a result of the comparison by the comparing means, the read sector address is larger than the target sector address. In this case, the system further comprises a notifying means for notifying the system control means of a target sector passage error.

[0015]

According to the first to seventh signal processing circuits of the present invention, when a predetermined control instruction is issued from the system control means, the decoded data (header information in main data or SUBQ data in subcode data) ) Are compared with the target sector address, and when the two sector addresses match, storage of the predetermined data in the decoded data in the buffer memory is started. This eliminates the need for the system control means to process an interrupt generated every time a sector address is acquired and to compare the interrupt with the target sector address when reading data from the optical disk. Thus, the processing load on the system control means is reduced. Therefore, a high-performance CPU is not required to realize the system control means, and the cost of the CD-ROM device can be reduced. When a predetermined control command is issued from the system control unit, the signal processing circuit finds a target sector and starts storing data in the buffer memory.
The system control means does not need to pay attention to the timing at which the control command for starting the reading is issued as in the related art.

According to the third signal processing circuit of the present invention, when a predetermined control command is issued from the system control means and the sector address is obtained from the header information in the main data, the header information is obtained by the error flag. Is determined to have an error, the correct value for the sector address obtained from the header information is complemented, and the sector address obtained by the complementation is compared with the target sector address. Thereby, the reliability of the control operation for reading data from the optical disk is improved.

According to the fourth signal processing circuit of the present invention, when a predetermined control command is issued from the system control means, the read sector address to be compared with the target sector address is sequentially determined from the SUBQ data in the subcode. Be acquired. Therefore, even in the case of CD-DA format data having no header information in main data such as music data, the signal processing circuit obtains the sector address of the data read from the optical disk in the signal processing circuit. Can be compared with the target sector address, thereby reducing the processing load on the system control means.

According to the fifth signal processing circuit of the present invention, when a predetermined control command is issued from the system control means and the sector address is obtained from the SUBQ data in the subcode, the cyclic redundancy for the SUBQ data is obtained. A check is performed, and if it is determined that there is an error in the SUBQ data, the correct value for the sector address obtained from the SUBQ data is complemented, and the sector address obtained by the complementation is set as the target sector address. Be compared. Thereby, the reliability of the control operation for reading data from the optical disk is improved.

According to the sixth signal processing circuit of the present invention, the sector address can be obtained from either the main data or the subcode by selection, so that any data can be obtained within the signal processing circuit. The sector address of the data read from the optical disk can be obtained and compared with the target sector address, thereby reducing the processing load on the system control means.

According to the seventh signal processing circuit of the present invention, when the sector address obtained from the data read from the optical disk is larger than the target sector address, the target sector passing error is reduced by the system control means. Therefore, even when the system control unit does not compare the read sector address with the target sector address, as in a CD-ROM device using the signal processing circuit according to the present invention, If it has already passed the target sector, it can be detected as a target sector passage error. Thus, it is possible to avoid a situation in which the pickup is already passing the target sector and the data is wastefully monitored in spite of the fact that the read sector address may not match the target sector address.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a signal processing circuit according to an embodiment of the present invention will be described with reference to the accompanying drawings.

<Configuration and Operation of CD-ROM Device> A CD-ROM device using the signal processing circuit of this embodiment has basically the same configuration as the conventional example shown in FIG. It includes a disk reading unit 50, a CD decoding unit 51, a buffer memory 52, a signal processing circuit 53, and a system controller 54, and a host 55 is connected to the signal processing circuit 53. The operations of these units are basically the same as in the conventional example. However, in this CD-ROM device, the system controller 54 sets a target sector address as a sector address to start reading in the signal processing circuit 53, and the signal processing circuit 53
This is different from the conventional example in which the system controller compares these sector addresses in that the sector address of the decoded data input from 1 to the signal processing circuit 53 is compared with the target sector address. Therefore, in this CD-ROM device, the system controller 54 is not interrupted each time the register storing the sector address is updated (for each sector).

<Configuration of Signal Processing Circuit> FIG. 2 is a functional block diagram showing the configuration of the signal processing circuit 53 of the present embodiment. The signal processing circuit 53 includes a host interface unit 11, a buffer management unit 12, and a sector processor 1.
3, a CD interface unit 14, a subcode interface unit 15, and a system control interface unit 17. The CD interface unit 14
The main data and its error flag among the decoded data input from the D decoding unit 51 are received and stored in a predetermined area of the buffer memory 52. The subcode interface unit 15 receives the subcode data among the decoded data input from the CD decoding unit 51 and stores the subcode data in a predetermined area in the buffer memory 52.
The sector processor 13 includes a CD interface unit 14
, The decoded data stored in the buffer memory 52,
That is, when the main data after the error correction by the EFM demodulation and the CIRC is the data of the CD-ROM format (details will be described later), the error detection and the error correction are further performed on the data. The buffer management unit 12 receives the buffer memory 52 from each block (the sector processor 13, the CD interface unit 14, and the subcode interface unit 15) in the signal processing circuit 53.
Arbitrates access requests to the buffer memory 5
Execute access to 2. The host interface unit 11 is an interface circuit for transferring data between the host 55 and the signal processing circuit 53. The system control interface unit 17 is an interface circuit for the system controller 54. The system controller 54 controls the operation of the signal processing circuit 53 via the system control interface unit 17.

FIG. 3A shows the data allocation in the buffer memory 52. The area in the buffer memory 52 is
Each page area is divided into 3072 bytes as one page. The page area is associated with the sectors on a one-to-one basis, and access to the buffer memory 52 is managed in page units.

FIGS. 3B and 3C are diagrams showing an example of the configuration in one page area, that is, an example of the data configuration in one sector. In the case of the CD-DA format, FIG.
As shown in (c), a 2352-byte main data area has a 294-byte EDB area (CD decoding section 51).
, An area for storing an error detection byte, which is information on an error after error correction), a 16-byte SUBQ area, and a 96-byte subcode area.
A 72-byte area is treated as one page. In addition,
SUBQ data is also stored in the subcode area.
The SUBQ area is separately provided as described above to facilitate access to UBQ data.

In the case of the CD-ROM format, FIG.
As shown in (b), the main data area in the CD-DA format is set as one sector, and for example, a mode 2 (MOD
E2), in the case of form 1 (FORM1), one sector is composed of a 12-byte sync pattern area, a 4-byte header area,
An 8-byte subheader area, a 2048-byte user data area, and a 4-byte error detection code CR
It comprises a C code area, a 172 byte P code parity area, and a 104 byte Q code parity area.
In the example shown in FIG. 3B, an additional 29
A 3072-byte area including a 4-byte EDB area, a 16-byte SUBQ area, and a 96-byte subcode area is treated as one page.

<Detailed Configuration of Main Part of Signal Processing Circuit> In a CD-ROM device using the signal processing circuit of the present embodiment,
When data is read from the optical disk, a predetermined decoding including demodulation for EFM and error correction by CIRC is performed by the CD decoding circuit 51 on the data read by the disk reading unit 50 as in the conventional example described above. Then, the decoded data is input to the signal processing circuit 53. The signal processing circuit 53 temporarily stores data to be read out of the decoded data in the buffer memory 52.
The present embodiment is characterized in the operation from when the decoded data is input to the signal processing circuit 53 to when the data to be read is stored in the buffer memory 52. Hereinafter, the configuration of a part (main part) related to this operation in the signal processing circuit of the present embodiment will be described.

FIG. 4 is a functional block diagram showing main parts of the CD interface unit 14 and the subcode interface unit 15 in the signal processing circuit 53 in the present embodiment. As shown in FIG. 4, the CD interface unit 14 includes a target sector register 21, a read sector register 22a, a complement register 22b, an error detection unit 23, a sector address acquisition unit 24, a selector 25, and an addition for incrementing a sector address by +1. Unit 26, comparator 27,
And a data storage control unit 28 for storing main data in the buffer memory 52. The subcode interface unit 15 includes a data storage control unit 38 for storing subcode data in the buffer memory 52. I have.

In the CD interface section 14, the sector address obtaining section 24 receives main data from among the decoded data input from the CD decoding section 51, obtains a sector address from header information in the main data, and Is stored in the read sector register 22a. The error detection unit 23 receives an error flag corresponding to the main data received by the sector address acquisition unit 24, and detects whether there is an error in the header information in the main data. Complementary register 22b and adder 26
Is used to supplement a correct value when the sector address obtained by the sector address obtaining unit 24 is not reliable (details will be described later). The selector 25 stores the sector address stored in the read sector register 22a when the error in the header information is not detected in the error detection unit 23, and stores the sector address in the complementary register 22b when the error in the header information is detected. Each sector address is selected, and the selected sector address (hereinafter referred to as “read sector address”) is input to the comparator 27 and also to the adder 26. The adder 26 increments the read sector address output from the selector 25 by 1, and stores the incremented sector address in the complement register 22b as a value for complementing the sector address obtained from the next main data. . The target sector address is stored in the target sector register 21 in advance by the system controller 54, and the comparator 27 compares the read sector address output from the selector 25 with the target sector address stored in the target sector register 21. Then, the comparison result is input to the data storage control unit 28. When the read sector address matches the target sector address, the data storage control unit 28
A buffer memory 5 for main data is stored in the buffer management unit 12.
2, and interrupts the system controller 54. At the same time, the data storage control unit 28 sends a signal to the data storage control unit 38 in the subcode interface unit 15 via a predetermined signal line C1.
The coincidence of the two sector addresses is notified. The data storage control unit 38 having received the notification causes the buffer management unit 12 to start storing the subcode data in the buffer memory 52.

<Operation of Signal Processing Circuit> FIG. 5 is a flowchart showing the operation of the CD interface unit 14 when reading data from an optical disk. Hereinafter, the operation of the signal processing circuit 53 when starting data reading will be described with reference to this flowchart, focusing on the operation of the CD interface unit 14 at this time.

CD using the signal processing circuit of the present embodiment
In the ROM device, when reading data from the optical disk, the system controller 54 sets a target sector address in the target sector register 21 in the signal processing circuit 53, and then starts reading from the signal processing circuit 53. Issue an instruction. At this time, the signal processing circuit 53 includes C
The decoded data including the main data, the error flag corresponding to the main data, and the subcode data is continuously input from the D decoding unit 51. That is, the main data and the error flag are sent to the CD interface unit 14,
The subcode data is stored in the subcode interface unit 15
Are input in synchronization with a predetermined clock.

When a read start command is issued, the CD interface unit 14 first issues a sector address acquisition unit 24.
Finds a 12-byte sector synchronization signal (sync pattern) from the main data in the decoded data input from the CD decoding unit 51, and when it finds a sync pattern, resets an internal word counter (not shown) to reset the sector synchronization. Perform the conversion. Then, 0, following the sync pattern,
Recognize 1, 2, and 3 bytes of data as header information (in the decoded data input to the signal processing circuit 53, unlike the configuration example in one page area shown in FIG. 3B,
Header information immediately follows the sync pattern). The header information includes 0: 00: 0 sector to 99: 59: 7.
The address (sector address) for each sector up to four sectors is stored.
This sector address is obtained from the header information and stored in the read sector register 22a. At this time, the error detection unit 23
Stores an error flag corresponding to the header information on a one-to-one basis in an internal error register (not shown) (step S12).

Next, the error detection unit 23 determines whether or not there is an error in the header information from the error flag stored in the error register (step S14). Based on the result, if there is no error, the selector 25 selects a sector address stored in the read sector register 22a. The comparator 27 compares the selected sector address (read sector address) with the target sector address stored in the target sector register 21. As a result of this comparison, if the read sector address is smaller than the target sector address, a value obtained by incrementing the read sector address by +1 is stored in the complement register 22b (however, in the configuration shown in FIG. Regardless of whether it is smaller than the target sector address or not, a value obtained by incrementing the read sector address by +1 is stored in the complement register 22b), and the process returns to step S12 (see steps S16, S18, and S20). Thereafter, as long as there is no error in the header information of the main data in the input decoded data (no error flag is set) and the read sector address obtained from the header information is smaller than the target sector address, Steps S12 → S14 → S16 → S18 → S20 are repeatedly executed. During this execution, when the read sector address matches the target sector address, reading is started. That is, the data storage control unit 28 sends an access request req to the buffer memory 52 to the buffer management unit 12, and when the access permission ack is obtained from the buffer memory management unit 12, the decoding input from the CD decoding unit 51 is performed. The main data in the data is sent to the buffer management unit 12 together with the address for the buffer memory 52. The buffer management unit 12 receives the main data and the address, and stores the main data in a predetermined area of the buffer memory 52 specified by the address. When the read sector address matches the target sector address, the data storage control unit 28 notifies the data storage control unit 38 in the subcode interface unit 15 of a match between the two sector addresses via a predetermined signal line C1. Upon receiving this notification, the data storage control unit 38 sends an access request req to the buffer memory 52 to the buffer management unit 12, and when an access permission ack is obtained from the buffer memory management unit 12, the data storage control unit 38 The data is sent to the buffer management unit 12 together with the address for the memory 52. Therefore, when the read sector address matches the target sector address, both the main data and the subcode data are stored in respective predetermined areas in the buffer memory 52 (FIG. 3).
(B)). Further, when reading is started in this way, the data storage control unit 28 notifies the system controller of the start of reading by interruption (step S24).

Step S12 → S14 → S16 → S18
→ If it is determined that there is an error in the header information (the error flag is set) while repeatedly performing the above-described processing of S20, the sector address stored in the read sector register 22a is not reliable. When it is determined that the read sector address cannot be read, the read sector address is complemented using the complement register 22b. That is, 1 is set in the complement register 22b.
Since a value which is incremented by +1 with respect to the read sector address of the previous sector is stored, the selector 25
Selects the value of the complement register 22b as the read sector address for the current sector based on the detection result of the error detection unit 23. Then, the comparator 27 compares the read sector address with the target sector address. As a result of this comparison, when the read sector address obtained by the complementation is smaller than the target sector address (step S2).
6, see S28), the value stored in the complement register 22b (the value output from the selector 25) incremented by +1 is stored again in the complement register 22b, and the process returns to step S12. On the other hand, as a result of the comparison, if the two sector addresses match, the process proceeds to step S22,
The data storage control unit 28 starts reading (storage in the buffer memory 52) in the same manner as described above.

When reading data from an optical disk, the system controller 54 normally activates the decoding section 51 first while controlling the disk motor, pickup, and the like, and activates the signal processing circuit 53 slightly before the target sector. Control to operate. Thereby, when the read sector address is compared with the target sector address in the above-described processing shown in FIG. 5 (steps S16, S18, S26, S28), the read sector address does not become larger than the target sector address. . However, when the read sector address is already higher than the target sector address for some reason (when the pickup has passed the target sector).
However, even if data is monitored any more, the read sector address cannot match the target sector address.
Then, based on the comparison result of the comparator 27, the data storage control unit 28, as shown in steps S16 and S26,
As a result of comparing the read sector address (including the sector address obtained by complementation) with the target sector address, if the read sector address is larger than the target sector address, a "target sector passage error" is interrupted by the system controller 54 to the system controller 54. Notify (step S32,
S34).

<Effect> In the signal processing circuit of the present embodiment, when a target sector address is set in the target sector register 21 by the system controller 54 and a read start command is issued, the decoding input from the CD decoding unit 51 is performed. The sector address is obtained from the header information in the main data in the encoded data, and the sector address is compared with the target sector address to find the target sector from which reading is to be started, and the main data and subcode data buffer memory 52 is read. Starts storing in. Accordingly, the system controller 54 interrupts each time a sector address is newly acquired from the decoded data.
The processing load on the system controller 54 is reduced as compared with the conventional case where the processing is performed to manage the sector address information. When a read start command is issued from the system controller 54, the signal processing circuit finds a target sector and starts storing main data and the like in the buffer memory as described above. There is also an effect that it is not necessary to pay attention to the timing of issuing an instruction as in the related art.

When the header information in the main data contains an error, the signal processing circuit according to the present embodiment replaces the sector address obtained from the header information with the read sector address one sector before by +1. The incremented value is used as the current read sector address (complement of the read sector address), and is compared with the target sector address. Therefore, it is not necessary to retry the read operation.
The reliability of the control operation for starting reading can be improved.

Further, according to the signal processing circuit of the above embodiment, when the sector address obtained from the data read from the optical disk is larger than the target sector address, a target sector passing error is sent to the system controller 54. Notified. Therefore, even when the system controller 54 does not compare the read sector address with the target sector address as in the CD-ROM device using the signal processing circuit of the above-described embodiment, the pickup has already detected the target sector. If so, it can be detected as a target sector pass error. As a result, it is possible to avoid a situation in which the pickup is already passing the target sector and the data is wastefully monitored in spite of the fact that the read sector address may not match the target sector address.

<Modification> In the signal processing circuit of the above embodiment, the sector address is obtained from the header information in the main data in the decoded data input from the CD decoding unit 51. The sector address may be obtained from the SUBQ data in the code.
Hereinafter, as a modified example of the above embodiment, a signal processing circuit that acquires a sector address from SUBQ data and performs a read start operation will be described.

In this modification, the sub-code interface unit 15 sends the signal from the CD decoding unit 51 to the signal processing circuit 5
A sector address is obtained from the SUBQ data in the subcode data of the decoded data input to 3, and it is determined whether or not the obtained sector address is reliable. That is, as shown in FIG. 6, the subcode interface unit 15 in this modification
A data extraction unit 32, a sector address acquisition unit 34, an error detection unit 36, and a data storage control unit 38 are provided.
And processing corresponding to S14. The processing of the other steps in this flowchart is performed by the CD interface unit 14 as in the above embodiment. The configuration of the CD interface unit 14 in this modification is basically the same as that of the above embodiment as shown in FIG. 6 (FIG. 4).
reference). However, since the processing corresponding to steps S12 and S14 is performed by the subcode interface unit 15 as described above, the error detection unit 23 and the sector address acquisition unit 24 in the CD interface unit 15 in FIG. Are not provided in the CD interface unit 15 of the first embodiment. Hereinafter, the operation of this modified example when reading data from an optical disk will be described in step S1.
2 and S14 will be mainly described.

When reading data from the optical disk, the system controller 54 sets a sector address at which reading is to be started in the target sector register 21 in the CD interface unit 14 of the signal processing circuit 53 as a target sector address. And then the signal processing circuit 5
3 is issued a read start instruction. At this time, the signal processing circuit 53 includes the CD decoding unit 5 as in the above embodiment.
1, the main data and the error flag are continuously input to the CD interface unit 14, and the subcode data is continuously input to the subcode interface unit 15, respectively.

As subcode data, P, Q, R,
One frame of information called S, T, U, V, and W (a total of eight bits) is included in one frame.
Since 96 sectors constitute one sector, each sector has 96 bits of Q-bit information (“SUBQ
SUBQ data includes address information corresponding to header information of main data. Therefore, the subcode interface unit 15
In the step corresponding to step S12 in FIG.
SUBQ data is extracted from the subcode data sequentially received from the subcode data 1, and the sector address acquisition unit 34
A sector address is obtained from the Q data and stored in the read sector register 22a in the CD interface unit 14. At this time, the error detection unit 36 performs error detection using a CRC (Cyclic Redundancy Check) code included in the SUBQ data (error detection by a cyclic redundancy check). In a step corresponding to step S14 in FIG. 5, it is determined whether or not the obtained sector address (the sector address stored in the read sector register 22a) is reliable by using the CRC code in the SUBQ code instead of the error flag. Judge by error detection.

With respect to steps other than steps S12 and S14, the same processing as in the above embodiment shown in FIG. That is, each time a sector address is obtained from the SUBQ data in the subcode data sequentially input to the signal processing circuit 53 and stored in the read sector register 22a, the sector address (obtained as a result of error detection by CRC) is obtained. If it is determined that the sector address is unreliable, the sector address complemented by using the complement register 22b is compared with the target sector address. As a result, when a target sector to start reading is found (when the read sector address and the target sector address match), the data storage control unit 28 stores the main data in the buffer memory of the main data in the buffer management unit 12 in the same manner as in the above embodiment. At the same time, the data storage control section 38 in the subcode interface section 15 is notified of the coincidence of the two sector addresses on a predetermined signal line C1. Upon receiving the notification, the data storage control unit 38 causes the buffer management unit 12 to start storing the subcode data in the buffer memory 52. Therefore, when a target sector to start reading is found, storage of both the main data and the subcode data in the buffer memory 52 is started. Further, when the data storage control unit 28 in the CD interface unit 14 starts reading in this way, it notifies the system controller by an interrupt that the reading has started.

According to the signal processing circuit as described above, the sector address is obtained from the subcode data.
In addition to D-ROM format data, CD-DA which has no header information in main data like music data
For the format data (FIG. 3C), the system controller 54 only needs to set a sector address to start reading in the target sector register 21 and issue a read start command. , The processing load on the system controller 54 is reduced. In addition, error detection is performed using the CRC code included in the SUBQ data, and when an error is detected, the correct value of the read sector address is complemented. The reliability of the control operation for starting can be improved.

<Others> As a means for obtaining a read sector address to be compared with a target sector address at the start of reading, the CD interface unit 1 as in the above embodiment is used.
4, a means for acquiring the read sector address from the header information in the main data, and a means for acquiring the read sector address from the SUBQ data in the subcode in the subcode face unit 15 as in the above-described modification, Preferably, the system controller 54 can switch which of these two means is used. In this way, since the sector address can be obtained from both the main data and the subcode data, the control operation for starting the reading can be performed for any data as in the above-described embodiment and the modification. And the system controller 54
Burden can be reduced.

Further, in the above-described embodiments and modifications, the function of comparing the read sector address with the target sector address, the function of complementing the correct value of the read sector address when the read sector address is determined to be unreliable, The CD interface unit has a function of starting storage of main data and subcode data in the buffer memory 52 when the read sector address matches the target sector address, and a function of notifying the system controller 54 of a start of reading or a passing error by interruption. 14, the present invention is not limited to such a configuration, and the same effects can be obtained as long as these functions are realized in the signal processing circuit 53. Further, in the above modification, some of these functions may be realized in the subcode interface unit 15.

In the above-described embodiment and modifications, the processing shown in the flowchart of FIG. 5 is executed by hardware (see FIGS. 4 and 6). May be executed.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing a configuration of a CD-ROM device for reading data from an optical disk.

FIG. 2 is a functional block diagram showing a configuration of a signal processing circuit according to an embodiment of the present invention.

FIG. 3 is a CD using the signal processing circuit of the embodiment.
(A) showing data allocation in the buffer memory in the ROM device, (b) showing a configuration example in one page in the case of the CD-ROM format, and (b) in one page in the case of the CD-DA format. FIG. 3C shows a configuration example.

FIG. 4 is a functional block diagram showing a configuration of a main part of a CD interface unit and a subcode interface unit in the signal processing circuit of the embodiment.

FIG. 5 is a flowchart showing the operation of the CD interface unit when reading data from an optical disk.

FIG. 6 is a functional block diagram showing a configuration of a main part of a CD interface unit and a subcode interface unit in a signal processing circuit according to a modification of the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Host interface part 12 ... Buffer management part 14 ... CD interface part 15 ... Subcode interface part 17 ... System control interface part 21 ... Target sector register 22a ... Read sector register 22b ... Complementary register 23 ... Error detection part 24 ... Sector address Acquisition unit 25 ... Selector 26 ... Adder 27 ... Comparator 32 ... SUBQ data extraction unit 34 ... Sector address acquisition unit 36 ... Error detection unit 38 ... Data storage control unit 51 ... CD decoding unit 52 ... Buffer memory 53 ... Signal processing circuit 54: System controller 55: Host computer

Claims (7)

[Claims] 1. A decoding means for performing predetermined decoding on data recorded on an optical disc and outputting decoded data, and determining a target sector address indicating a sector from which reading on the optical disc is to be started. A signal processing circuit connected to a system control means for issuing a control instruction and a buffer memory for temporarily storing data, wherein when a predetermined control instruction is issued from the system control means, A signal processing circuit for storing predetermined data in the decoded data in the buffer memory based on an instruction; address obtaining means for sequentially obtaining a sector address from the decoded data; and holding means for holding the target sector address. When the predetermined control command is issued, the control command is sequentially obtained by the address obtaining means. Comparing means for comparing a read sector address, which is a sector address, with the target sector address held in the holding means; as a result of comparison by the comparing means, when the read sector address matches the target sector address, Storage control means for starting storage of predetermined data in the buffer memory. 2. The signal processing circuit according to claim 1, wherein said address obtaining means obtains a sector address from header information in main data included in said decoded data. 3. The signal processing circuit according to claim 2, wherein: a flag acquisition unit that acquires an error flag for header information in main data included in the decoded data; and wherein the error flag has an error in the header information. Means for complementing a correct value for the read sector address obtained from the header information, wherein the comparing means indicates that the error flag indicates an error in the header information. Wherein the read sector address obtained by the complementing means is compared with the target sector address in place of the read sector address obtained from the header information. 4. The signal processing circuit according to claim 1, wherein said address obtaining means obtains a sector address from SUBQ data in subcode data included in said decoded data. 5. The signal processing circuit according to claim 4, wherein the SUBQ data is subjected to a cyclic redundancy check to determine whether the SUBQ data has an error. If it is determined that there is
Supplementing means for supplementing a correct value for the read sector address obtained from the SUBQ data, wherein the comparing means reads the read sector obtained from the SUBQ data when it is determined that the SUBQ data has an error. A signal processing circuit for comparing a read sector address obtained by a complementing means with the target sector address instead of an address. 6. The signal processing circuit according to claim 1, wherein the address obtaining means obtains a sector address from header information in main data included in the decoded data, and the decoded data. Second obtaining means for obtaining a sector address from the SUBQ data in the subcode data included in the sub-code data, and a sector address and a second obtaining means obtained by the first obtaining means based on a predetermined control command issued from the system control means. Selecting means for selecting any of the sector addresses obtained by the means as the read sector address. 7. The signal processing circuit according to claim 1, wherein as a result of the comparison by said comparing means, when said read sector address is larger than said target sector address, a target sector passing error is generated. Signal processing circuit, comprising: a notifying unit for notifying the system control unit of the following.