JPS63311455A - Copy protection device for software - Google Patents

Abstract

PURPOSE:To secure copy protection even to remodeling by collating data on software simultaneously with the reading action of the software and fetching a copy protection code via a register to inhibit the output of said code to the outside. CONSTITUTION:A decoder 24 is connected to an address bus 23 and outputs H as a selection signal when an address reaches another address where copy protection data is written. A gate circuit 25 receives a selection signal from the decoder 24 and switches a control bus 21. Then a selection signal SEL of H is supplied to the circuit 25 from the decoder 24 with a copy protection code when a floppy disk FD40 is read. At the same time, a chip-enable signal of the bus 21 is supplied to a register 11 and the copy protection code is written in the register 11. In this case, nothing is written in a cache RAM41. Thus a copying action is impossible for the floppy disk even with remodeling.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus for reading software on a recording medium and restricting copying to another recording medium.

Specifically, the present invention relates to a computer device that reads and executes software from a recording medium such as a floppy disk, and relates to a floppy disk copy protection device that prevents the read software from being copied to other floppy disks without restriction.

[Prior art]

As a device to prevent copying of software,
No. 9-157747 and the like are publicly known. In such technology, original software data and copy protection data are generally recorded on the floppy disk in a mixed manner, and the computer device uses the copy protection data to make a self-judgment and perform an operation to prohibit copying. Such a device will be described in detail with further reference to the drawings.

FIG. 3 shows the configuration of a computer device 30 according to the present application. The computer device 30 has a processor 31 (hereinafter c
pu) and a main RAM 32 are connected via a bus 33, and further includes a floppy disk drive device 35 (hereinafter referred to as FDD). This FDD
35 has an IC built into it. It has a floppy disk controller 36 (hereinafter referred to as FDC). The FDC 36 has a controller 37 and a recording/reproducing circuit 38 inside.

The recording/reproducing circuit 38 uses a magnetic head 39 to read and write data on a floppy disk 40 (hereinafter referred to as FD).Furthermore, a relatively large capacity cache RAM 41 is connected to the FDC 35. This cache RAM 41 has the effect of a cache register and a buffer register for access from the CPU 31.

Now, data in the format shown in FIG. 4 is written on the FD 40. In order to simplify the explanation, data that is not directly related to the present application is indicated by diagonal lines, and the explanation thereof is omitted. a indicates the data format of one track, one track consists of four sectors S (1) to 5 (4
), and each sector is determined to be 5765B (bytes) of data. b shows the internal structure of each sector, and there are data frames DF numbered from 0 to 127 inside.
(0) to DF (127) are divided into 128 data frames. Each data frame has a capacity of 44B. Furthermore, as shown in C, each data frame is divided into IB subcodes ( SC), 32B of coding data (CD), and 8B of parity data (PD) for error correction.There is an IB subcode in each data frame, and the entire data frame has 128B of subcodes. There will be a code.These subcodes consist of four sets of the same subcodes as shown in d.
2B copy protection code (CPC) for each 32B
exists.

Now, FDC36 is based on various data of FD40.

It is possible to output error-corrected data and a copy protection code to the outside. Normally, these data are stored in the cache RAM 41, and only the data is transferred to the main RAM 32 upon request from the CPU 31.

The method of using the copy protection code will be explained below with reference to FIGS. 5 to 7.

First, in Fig. 5, 50 and 51 are the main RAMs, respectively.
32. This is a schematic representation of the memory map of the cache RAM 41. The CPU 31 reads the copy protection code (000) in the cache 41 and compares it with the copy protection code (000) that the CPU 31 itself has. The copy protection code of this CPU is in the ROM52.
It is incorporated into the CPU 31 as a. If the read data is from the original FD, the copy protection code (000) matches and the software transferred to the main RAM 32 executes normally.

Now, when copying the software in the main RAM 32 to another FD (X), the controller 37 replaces the original (000) as the copy protection code with the ROM
It operates to write a dummy code in 52, for example (XXX). The FD (X) software copied in this way has only the copy protection code (X).
The software becomes (Figure 6).

When attempting to read and operate this copy of FD (X), the copy protection code of the cache RAM 41 is (x x x), which is different from the copy protection code (○○○) of the CPU 31. So CP
U31 can detect that FD (X) has been illegally copied and prohibit normal operation (FIG. 7).

Now, according to two or more configurations, it has been found that although FD (X) cannot be operated by normal actions, it is possible to operate it by the first modification. That is, when the original FD is read in advance, the cache R
AM41 written copy protection code (○O○
).

Next, when data is read from the copy FD (X), the copy protection code (XX
X) is rewritten to (000) by an external operation. If you do this.

9 CPU even though FD (X) is a copy
If you access the copy protection code from 31,
(000) exists, the software in the main RAM 32 becomes executable.

Since the cache RAM 41 is external to the FDC 36, a jig for rewriting the contents of the memory is inserted into the bus 34 between them.

Partial rewriting is relatively easily possible for those with advanced electronic technology. Although such modification clearly violates copyright law and is subject to punishment, it is preferable that it can be prevented.

[Purpose of the invention]

An object of the present invention is to enable copy protection even against the above-mentioned modifications, and specifically, to prevent copy protection codes from being output to an external cache RAM.

More specifically, a relatively small-capacity register is installed inside the single-chip FDC, and 1 normal data is stored in an external register.
It is characterized in that it can be output to the AM, and that the copy protection code is prohibited from being output to the outside and is written to a register within the FDC.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 shows the configuration of an FDC according to the present invention. For the same parts as before, the numbers used in the explanation of FIG. 3 are used as they are. The characteristics of the present invention are as follows.

The point is that a register 11 is provided within the FDCIO, which is a one-chip IC. This register 11 may have a relatively small capacity that can temporarily store copy protection data.In the embodiment of the present invention, it is configured with 2B. controller 37
detects a data string or address, and when the copy protection code portion is reached, data output to the cache RAM 41 is prohibited and a write operation to the register 11 is performed.

Data transfer from cache RAM 41 to main RAM 32 is performed as usual. During execution, the CPU
31 requests a copy protection code, controller 37 returns the copy protection code of register 11.

As mentioned above, if it is an original FD, there is no difference in operation from the conventional one.

When reading the copy FD(X), the cache RA
Data is written to M41, and a copy protection code (X X X) is written to register 11.

Since this copy protection code (X There is a possibility that the copy protection data may be stolen via the bus 33 between the CPU 31 and the FDD 35, but since the copy protection code in the register 11 cannot be rewritten,
It is impossible to perform D (X).

FIG. 2 shows a more specific configuration of the above-described embodiment. There are a control bus 21, a data bus 22, and an address bus 23 within the FDCIO. Each bus is connected to each device described below. Recording/playback circuit 38. Since the controller 37 and the controller 37 have already been described, their explanation will be omitted. The register 11 is connected to each bus and is provided in parallel with the cache RAM 41.

The decoder 24 is connected to the address bus 23, and outputs rHJ as a 2 selection signal when the address reaches an address where copy protection data is written. The gate circuit 25 receives the selection signal from the decoder 24 and switches the control bus 21.

The control bus 21 is 1, for example, the cache RAM 41.
Since it is connected to the chip enable terminal (CE) of the register 11, the cache RAM 41 or the register 11 is selectively operated.

In the read operation of the FD 40, since the gate circuit 25 selects the cache RAM 41 for one normal data string, data is written onto the cache RAM 41.

When the predetermined address is reached and the copy protection code is reached, the rHJ selection signal (SEL) is sent from the decoder 24.
is supplied to the gate circuit 25, and the gate circuit 25 transfers the chip enable signal from the control bus 21 to the register 11.
The copy protection code is written to register 11. At this time, nothing is written to the cache RAM 41.

In this embodiment, the input of the decoder 24 is connected to the address bus 23 on the premise that the address of the copy protection code is determined. Another method is to connect a circuit that constantly monitors data to the data bus 22 and detects the presence of a code indicating the start of a copy protection code on the data bus.

A selection signal (SEL) may be supplied to the gate circuit 25.

〔Effect of the invention〕

As explained above, according to the copy protection device of the present invention, it becomes impossible to copy a floppy disk even if it is modified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the concept of a copy protection device of the present invention, FIG. 2 is a block diagram showing an embodiment of the invention in detail, FIG. 3 is a block diagram of a conventional copy protection device, and FIG. 4 1 is a conceptual diagram of a data format on a floppy disk according to the present invention, and FIGS. 5 to 7 are memory maps for understanding the present invention. system + tomoe

Claims (1)

[Claims] In addition to reading the recording medium on which the software is written,
A device for writing software, which consists of a control circuit that controls writing and reading, a register provided in this control circuit, and a recording/playback circuit that performs writing and reading operations on a recording medium using this control circuit. , the data of the software is collated simultaneously with the read operation of the software, normal data can be outputted to the outside, and copy protection codes are prohibited from being outputted to the outside by being captured in the above-mentioned register. Software copy protection device.