JPS58223860A - Magnetic disk controller - Google Patents

Magnetic disk controller

Info

Publication number
JPS58223860A
JPS58223860A JP57107406A JP10740682A JPS58223860A JP S58223860 A JPS58223860 A JP S58223860A JP 57107406 A JP57107406 A JP 57107406A JP 10740682 A JP10740682 A JP 10740682A JP S58223860 A JPS58223860 A JP S58223860A
Authority
JP
Japan
Prior art keywords
magnetic disk
control circuit
time
control
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57107406A
Other languages
Japanese (ja)
Inventor
Fumio Kuroiwa
黒岩 文雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57107406A priority Critical patent/JPS58223860A/en
Publication of JPS58223860A publication Critical patent/JPS58223860A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers

Abstract

PURPOSE:To reduce the effect of a CPU to the control time and to prevent deterioration of the control processing capacity of an information processor, by performing a verifying operation in the idle processing time of a magnetic disk device under the control of a magnetic disk controller. CONSTITUTION:An idle time control circuit 9 monitors the time interval during which an instruction is transmitted to a magnetic disk controller from a CPU. The idle processing time is decided when an interval longer than a fixed time is detected, and a verifying operation is indicated to a sequence control circuit 1. Then the verifying operation is controlled while reading successively the contents of a verifying control circuit 7 and an index register 8. Thus the verifying operation is carried out while an error is detected by a redundant bit control circuit 4. The contents of the register 8 are successively reset when a verifying operation is over. The verifying operation completes when the contents of the register 8 are all reset.

Description

【発明の詳細な説明】 本発明は磁気ディスク制御装置に関し、特に電子計算機
等の情報処理装置に使用されるハードディスク装置およ
びフロッピィディスク装置の磁気ディスク制御装置に関
する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic disk control device, and more particularly to a magnetic disk control device for a hard disk device and a floppy disk device used in an information processing device such as an electronic computer.

従来、この種の磁気ディスク装置においては書込み動作
のエラー検出はヘッドが1個のため適当な検出方法がな
く書込み動作後ソフトウェア的に読出し動作(通常ベリ
ファイ動作と云う)を行なうことによりエラー検出を行
なっている。
Conventionally, in this type of magnetic disk drive, there is no appropriate detection method for detecting errors in write operations because there is only one head, so errors are detected by performing a read operation (usually called a verify operation) using software after the write operation. I am doing it.

従来の磁気ディスク制御装置は第1図に示すようにシー
ケンス制御回路1により各動作モードでの信号の送受制
御を行ない、指標レジスタ2で各動作モードでの信号の
記憶および磁気ディスク装置の動作状況の記憶を行ない
、この結果をこのシーケンス制御回路10制御により中
央演算処理装置(以下CPUと云う)へ報告する。デー
タ変換回路は記録型式によりデータの変換を行なうもの
で、冗長ビット制御回路4は書込み動作時には冗長ビッ
ト(パリティ、CRC等を含む)を生成し、読出し動作
時には冗長ビットの比較を行なうものである。CPUイ
ンターフェイス制御回路5はC−PUと磁気ディスク制
御装置のインターフェイス信号の制御を行ない、磁気デ
ィスクインターフェイス制御回路6は磁気ディスク制御
装置と磁気ディスク装置のインターフェイス信号の制御
を行なう本のである。ところでこの磁気ディスク制御装
置は読出し動作時には冗長ビット制御回路4でエラー検
出を行なっているが、書込み動作時には冗長ビット制御
回路4では冗長ビットの生成を行なうためにエラー検出
ができなく前記のソフトウェア的方法によりエラー検出
を行なっている。したかってこの方法ではCPUの制御
時間を要し実時間内で処理しようとすると情報処理装置
の制御処理能力を低下させると云う欠点を有していた。
As shown in FIG. 1, in a conventional magnetic disk control device, a sequence control circuit 1 controls the transmission and reception of signals in each operating mode, and an index register 2 stores signals in each operating mode and records the operating status of the magnetic disk device. is stored, and the result is reported to a central processing unit (hereinafter referred to as CPU) under the control of this sequence control circuit 10. The data conversion circuit converts data depending on the recording format, and the redundant bit control circuit 4 generates redundant bits (including parity, CRC, etc.) during write operations, and compares redundant bits during read operations. . The CPU interface control circuit 5 controls the interface signals between the CPU and the magnetic disk controller, and the magnetic disk interface control circuit 6 controls the interface signals between the magnetic disk controller and the magnetic disk device. By the way, in this magnetic disk control device, during a read operation, the redundant bit control circuit 4 performs error detection, but during a write operation, the redundant bit control circuit 4 generates redundant bits, so error detection cannot be performed, and the above-mentioned software Error detection is performed using this method. Therefore, this method has the disadvantage that it requires a lot of CPU control time, and if processing is attempted in real time, the control processing capacity of the information processing apparatus is reduced.

本発明は磁気ディスク制御装置の制御下で磁気ディスク
装置の生処理時間にベリファイ動作を行なうことにより
上記欠点を解決し、ベリファイエラ一時にCPUに対し
て再書込み動作制御要求を2      行なうように
した磁気ディスク制御装置を提供す−1す るものである。
The present invention solves the above drawback by performing the verify operation during the raw processing time of the magnetic disk device under the control of the magnetic disk control device, and makes two rewrite operation control requests to the CPU at the time of a verify error. The present invention provides a magnetic disk control device.

本発明によれば、情報処理装置における磁気ディスク制
御装置忙おいて、中央演算処理装置からの書込み制御信
号を記憶するレジスタを有し、該レジスタにより前記書
込み制御信号を記憶し、中央演算処理装置からの動作指
示命令の有無を検出して、その生処理時間に前記レジス
タに記憶された書込み制御信号によシ磁気ディスク装置
に書込まれたデータのベリファイ動作を実行し、データ
に誤りが発見された場合には中央演算処理装置に再書込
みのための制御信号を送出するように制御することを特
徴とする磁気ディスク制御装置が得られる。
According to the present invention, a magnetic disk control device in an information processing device has a register that stores a write control signal from a central processing unit, and the register stores the write control signal, and the central processing unit detects the presence or absence of an operation instruction command from the controller, and executes a verify operation of the data written to the magnetic disk device using the write control signal stored in the register during the raw processing time, and detects an error in the data. A magnetic disk control device is obtained, which is characterized in that it controls the central processing unit to send a control signal for rewriting when the central processing unit does so.

次に本発明の実施例について図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.

第2図は本発明の一実施例の磁気ディスク制御装置の基
本的なブロックを示す。第2図において、第1図と同一
部分は同一符号が付されており、重複を避けるために同
一部分の説明を省略する。
FIG. 2 shows the basic blocks of a magnetic disk control device according to an embodiment of the present invention. In FIG. 2, the same parts as in FIG. 1 are designated by the same reference numerals, and explanations of the same parts will be omitted to avoid duplication.

ベリファイ制御回路7は磁気ディスク装置の生処理時間
にベリファイ動作を行なう時の制御回路でありCPUか
らの読出し動作命令と同じ機能を有する。指標レジスタ
8は書込み動作を行なりた時のCPUからの書込み制御
信号をベリファイ制御信号とし記憶する。空時間制御回
路9はCPUと磁気ディスク制御装置のイそターフェイ
ス信号の監視を行なう回路である。シーケンス制御回路
1はCPUから発生される書込み命令がCPUインター
フェイス制御回路5を通して受けると、この書込み命令
を指標レジスタ内に逐次記憶させるように制御する。た
だし、この指標レジスタ8は書込み命令以外の情報を記
憶しないようになっている。空時間制御回路9はCPU
から磁気ディスク制御装置に命令が伝達される時間間隔
を監視しある一定以上の間隔を検出すると、生処理時間
とみ表しシーケンス制御回路1ヘペリフアイ動作を指示
しベリファイ制御回路7とともに指標レジスタ8の内容
を逐次読出しながらベリファイ動作を制御し、冗長ビッ
ト制御回路4によシェラ−検出を行ないながらベリファ
イ動作を行なっていく。
The verify control circuit 7 is a control circuit for performing a verify operation during the raw processing time of the magnetic disk device, and has the same function as a read operation command from the CPU. The index register 8 stores a write control signal from the CPU when a write operation is performed as a verify control signal. The idle time control circuit 9 is a circuit that monitors the idle face signals of the CPU and the magnetic disk control device. When the sequence control circuit 1 receives a write command generated from the CPU through the CPU interface control circuit 5, it controls the write command so that the write command is sequentially stored in the index register. However, this index register 8 is designed not to store information other than write commands. The idle time control circuit 9 is a CPU
The time interval at which commands are transmitted from the magnetic disk controller to the magnetic disk controller is monitored, and when an interval longer than a certain level is detected, it is regarded as the raw processing time, and the sequence control circuit 1 is instructed to perform a peripheral operation, and together with the verify control circuit 7, the contents of the index register 8 are read. The verify operation is controlled while sequentially reading, and the verify operation is performed while the redundant bit control circuit 4 performs Scherrer detection.

一方1つのベリファイ動作が完了すると指標レジスタ8
の内容を逐次リセットしていく。このとき指鴫レジスタ
8の内容が全てリセットされるとベリファイ動作は完了
する。したがってシーケンス制御回路1はベリファイ動
作中に冗長ビット制御回路4によってエラーが検出され
るとCPUインターフェイス制御回路5t−通してCP
Uへ警報信号を発し指標レジスタ(2)8のベリファイ
制御信号を再書込み制御信号としてCPUへ送る。もし
シーケンス制御回路1はベリファイ動作中にCPUから
磁気ディスク制御装置へ命令が発生すると空時間制御回
路9から動作実行中の信号を出力し実行中のベリファイ
動作が完了するまで受付けないようになりており、また
ベリファイ制御信号の有無を示す信号をもちCPUから
の要求によりCPUへ送ることもできるようにし記憶媒
体の交換時および電源切断時の防止信号とすることも可
能となる。
On the other hand, when one verify operation is completed, the index register 8
The contents will be reset one by one. At this time, when the contents of the finger mark register 8 are all reset, the verify operation is completed. Therefore, when an error is detected by the redundant bit control circuit 4 during the verify operation, the sequence control circuit 1 transmits the CP through the CPU interface control circuit 5t.
It issues an alarm signal to U and sends the verify control signal of index register (2) 8 to the CPU as a rewrite control signal. If the sequence control circuit 1 issues a command from the CPU to the magnetic disk control device during the verify operation, the idle time control circuit 9 outputs a signal indicating that the operation is being executed and does not accept the command until the verify operation that is currently being executed is completed. In addition, it has a signal indicating the presence or absence of a verify control signal, which can be sent to the CPU upon request from the CPU, and can be used as a prevention signal when replacing the storage medium or turning off the power.

本発明d以上説明したように、ベリファイ−作制御回路
等を設けることにより書込み動作後のエラー検出を磁気
ディスク装置の生処理時間に行ないしかもCPUの制御
時間に与える影響を少なくし情報処理装置の制御能力を
ほぼ実時間で行なうことができる。
The present invention (d) As explained above, by providing a verify operation control circuit, etc., error detection after a write operation is performed during the raw processing time of the magnetic disk device, and the influence on the control time of the CPU is reduced, thereby reducing the impact on the information processing device. Control capabilities can be performed almost in real time.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の磁気ディスク制御装置の基本的な回路を
示すプロ12図、第2図は本発明の一実施例である磁気
ディスク制御装置を示すブロック図である。 1・・・・・・シーケンス制御回路、2・・・・・・指
標レジスタ、3・・・・・・データ変換回路、4・・・
・・・冗長ビット制御ML  5・・・・・・CPUイ
ンターフェイス制御回路、6・・・・・・磁気ディスク
インターフヱイス制御回路、7・・・・・・ベリファイ
制御回路、8・・・・・・指標レジスタ、9・・・・・
・空時間制御回路。なお、図中同一符号は同一部分ま九
は相当部分を示す。
FIG. 1 is a diagram showing a basic circuit of a conventional magnetic disk control device, and FIG. 2 is a block diagram showing a magnetic disk control device according to an embodiment of the present invention. 1... Sequence control circuit, 2... Index register, 3... Data conversion circuit, 4...
... Redundant bit control ML 5 ... CPU interface control circuit, 6 ... Magnetic disk interface control circuit, 7 ... Verification control circuit, 8 ... ...Indicator register, 9...
・Free time control circuit. In addition, the same reference numerals in the figures indicate the same parts and the corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 情報処理装置における磁気ディスク制御装置において、
中央演算処理装置からの書込み制御信号を記憶するレジ
スタを有し、該レジスタにより前記書込み制御信号を記
憶し、中央演算処理装置からの動作指示命令の有無を検
出して、その空処理時間に前記書込み制御信号によシ磁
気ディスク装置に書込まれたデータのベリファイ動作を
実行し、データに誤りが発見された場合には中央演算処
理装置に再書込みのための制御信号を送出するように制
御することを特徴とする磁気ディスク制御装置。
In a magnetic disk control device in an information processing device,
It has a register that stores a write control signal from a central processing unit, stores the write control signal using the register, detects the presence or absence of an operation instruction command from the central processing unit, and executes the above-mentioned data during the idle processing time. A write control signal is used to verify the data written to the magnetic disk drive, and if an error is found in the data, a control signal is sent to the central processing unit for rewriting. A magnetic disk control device characterized by:
JP57107406A 1982-06-22 1982-06-22 Magnetic disk controller Pending JPS58223860A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57107406A JPS58223860A (en) 1982-06-22 1982-06-22 Magnetic disk controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57107406A JPS58223860A (en) 1982-06-22 1982-06-22 Magnetic disk controller

Publications (1)

Publication Number Publication Date
JPS58223860A true JPS58223860A (en) 1983-12-26

Family

ID=14458333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57107406A Pending JPS58223860A (en) 1982-06-22 1982-06-22 Magnetic disk controller

Country Status (1)

Country Link
JP (1) JPS58223860A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62192976A (en) * 1986-02-20 1987-08-24 Sharp Corp Disk recording and inspecting system
JPH08297928A (en) * 1995-04-26 1996-11-12 Toshiba Corp Magnetic disk device with recording medium inspecting function
JPH0945013A (en) * 1995-07-31 1997-02-14 Matsushita Electric Ind Co Ltd Multimedia disc recorder

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62192976A (en) * 1986-02-20 1987-08-24 Sharp Corp Disk recording and inspecting system
JPH08297928A (en) * 1995-04-26 1996-11-12 Toshiba Corp Magnetic disk device with recording medium inspecting function
JPH0945013A (en) * 1995-07-31 1997-02-14 Matsushita Electric Ind Co Ltd Multimedia disc recorder

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