JP2000187621A - Scsi controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an SCSI controller for surely clarifying the cause of the generation of an error by tracing and holding the various kinds of data related with a SCSI(small computer system interface) system. SOLUTION: A trace control circuit 121 issues the instruction of trace to a trace memory 131 according to the states of a SCSI control bus 210 and a processor control bus 260, and a trace memory part 131 traces a SCSI data bus 200, SCSI control bus 210, processor data bus 250, and processor control bus 260 in response to the instruction. In this case, when any abnormality is generated in the SCSI data bus or the SCSI control bus, an abnormality detecting circuit 111 detects it, and instructs the stop of the trace to the trace control circuit. Thus, the states of the SCSI bus and the processor bus until the abnormality is generated can be left in a trace memory part without being overwritten.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a SCSI (Small Computer System Interface).
It is called CSI. 2.) An SC having a function of tracing the operation of the SCSI bus and the processor bus with respect to the control device.
It relates to an SI control device.

[0002]

2. Description of the Related Art Conventionally, in a computer having a SCSI interface, as a means of analyzing an error of a SCSI bus, a method of tracing the state of the SCSI bus to a memory device until an abnormality is detected has been used. I have. For example, JP-A-6-342406
According to the publication, the SCSI bus control circuit makes the SCSI
A technique is described in which data on a bus is written into a trace memory, and when an abnormality is detected, the trace data is transferred to a microprocessor or the like.

FIG. 7 shows a conventional SCS having a trace function.
It is a block diagram showing an example of an I control device. In the figure, a SCSI bus trace control circuit 120 includes a SCSI data bus 200 and a SCSI control bus 210.
Are sequentially written to the SCSI bus trace memory unit 130, and data in the SCSI bus trace memory unit 130 is updated. On the other hand, the SCSI controller 100
The SI bus is monitored, and when an abnormality is detected, an abnormality signal is sent to the abnormality detection circuit 110. When the abnormality detection circuit 110 receives the abnormality signal, the SCSI bus trace control circuit 1
Then, a stop signal is sent to 20. As a result, the trace data up to the occurrence of the error can be left in the trace memory without being overwritten.

Thereafter, the trace data is sent to the processor data bus 250 by the trace memory read control circuit 140 and analyzed by the microprocessor 160 and the like. As a result, the state of the SCSI bus up to the detection of an abnormality in the SCSI data bus 200 and the SCSI control bus 210 can be known, and the cause of the error can be analyzed. However, since the state of the parts other than the SCSI bus cannot be known, the resolution of errors is limited.

[0005]

SUMMARY OF THE INVENTION The above conventional S
The CSI control device has the following problems.

The first problem is that tracing of only the status of the SCSI bus does not always provide sufficient information for error analysis. An error in the SCSI bus may be caused by an abnormality such as a control signal of a microprocessor. The trace of the signal state of the SCSI bus may only indicate that the error has occurred.

The second problem is that errors may not be detected by the error detection by the SCSI controller. In that case, trace data required for error analysis is destroyed by overwriting, and error analysis cannot be performed reliably. It is. The reason is that the error on the SCSI bus is S
This is also due to the stall of the CSI controller.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and trace and retain various data related to the SCSI system so that the cause of the error can be clarified. Is to provide.

[0009]

A SCSI controller according to the present invention is a SCSI controller interposed between a SCSI bus and a processor bus. The SCSI controller traces the processor bus simultaneously with the SCSI bus to store trace data. When an abnormality occurs in the SCSI bus, tracing of the SCSI bus and the processor bus is stopped, and trace data until the occurrence of the abnormality is transmitted.

[0010] The SCSI control device of the present invention comprises:
SCSI interposed between CSI bus and processor bus
In the control device, a trace control circuit instructing to trace signals of the SCSI bus and the processor bus by using specific signals of the SCSI bus and the processor bus as a trigger, and the SCSI bus instructed by the trace control circuit A trace memory unit for storing a signal of the processor bus, and, when the SCSI bus is monitored and an abnormality is detected, a stop request signal for the trace being executed is sent to the trace control circuit and an interrupt signal is sent to a higher-level device. A trace memory read control circuit for reading the trace data stored in the trace memory unit instructed by the host device that has recognized the interrupt signal, and an error detection circuit that sends the SCSI bus instructed by the host device. Between the lower device and the higher device via In constituted by and a SCSI controller to pass data.

Further, in the SCSI controller according to the present invention, the trace control circuit includes a control signal edge detection circuit for detecting a rising / falling edge of a control signal of the SCSI bus, and a rising / falling edge of a write control signal to the SCSI controller. A write signal edge detection circuit for detecting a falling edge;
A read signal edge detection circuit for detecting a rising / falling edge of a read control signal to the CSI controller, an OR circuit for transmitting a logical sum signal of the signals transmitted by the edge detection circuits, and a latch request in accordance with the logical sum signal A latch request signal generation circuit for generating a signal, transmitting the signal to the trace memory unit, and suppressing transmission of the latch request signal when receiving a trace stop request signal transmitted by the abnormality detection circuit.

Further, in the SCSI control device according to the present invention, the trace memory section receives a plurality of data from a SCSI bus and a processor bus, respectively, and outputs a plurality of data latches according to the latch request signal. A memory for sequentially storing data as trace data; and a memory control circuit for reading trace data from the memory in accordance with a trace data read request signal sent by the trace memory read control circuit.

Further, in the SCSI control device according to the present invention, the trace memory read control circuit reads the trace data from the trace memory unit when instructed by an external processing device connected without passing through the processor bus. Also, the SCSI control circuit of the present invention is a differential type SCS.
It is connected to a differential SCSI bus via an I driver / receiver.

That is, according to the SCSI control apparatus of the present invention, the trace of the microprocessor data bus and the control bus at the time of accessing the SCSI bus and the SCSI controller is performed simultaneously, thereby achieving the SCSI control.
When a bus error occurs, analysis of the error content can be greatly facilitated.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. Referring to FIG.
The control device 151 includes a trace control circuit 121 that issues a trace instruction to the trace memory unit 131 using specific signals of the SCSI control bus 210 and the processor control bus 260 as a trigger. SC
SI control bus 210, processor data bus 2
All 50 signals and processor control bus 260
Has a trace memory unit 131 for storing the state of the signal for controlling the SCSI controller 100.

Further, the abnormality detection circuit 111 includes a SCSI data bus 200 and a SCSI control bus 210.
Is constantly monitored, and if an error occurs, the trace control circuit 1
A trace stop request signal is output to 21. At the same time, an interrupt signal is output to the microprocessor 160. The microprocessor 160 is connected to the abnormality detection circuit 11
Recognizing that an error has occurred in the SCSI interface based on the interrupt signal from No. 1, requests the trace memory read control circuit 140 to read the data in the trace memory unit 131, and analyzes the cause of the error based on the read data. The SCSI controller 100 controls the SCSI interface operation such as read / write using the SCSI interface in accordance with an instruction from the microprocessor 160.

FIG. 2 is a block diagram showing a main part of the trace control circuit 121. In the figure, a trace control circuit 121 detects a rising / falling edge of a control signal of a SCSI bus, or detects a rising / falling edge of a write control signal and a rising / falling control signal to the SCSI controller 100. It has a write signal edge detection circuit 123 and a read signal edge detection circuit 124 to detect.

Also, an OR for obtaining a logical sum of the edge detection circuit is provided.
From the output of the R circuit 128, the latch request signal generation circuit 12
5 generates a latch request signal for the trace memory unit 131. When the trace stop request from the abnormality detection circuit 111 becomes active, the latch request signal generation circuit 125 suppresses the latch request signal. The gates 126 and 127 select a write control signal and a read control signal by a SCSI controller chip select signal.

FIG. 3 is a block diagram showing a main part of the trace memory unit 131. In the figure, data latches 132 to 135 latch the states of the SCSI data bus, SCSI control bus, processor data bus, and processor control bus, respectively, according to the latch request signal. When the latch request signal becomes active, the memory control circuit 136 recognizes that the data has been latched in the data latches 132 to 135, and writes the latch data in order from the top of the memory 137. When the storage area of the memory 137 becomes full, New writing control is performed sequentially from the top. Further, the memory control circuit 136 performs control to read data stored in the memory 137 when a trace data read request is issued from the microprocessor.

FIG. 4 is a flow chart showing the operation of the above-mentioned SCSI controller. FIG. 5 shows a schematic flow of an example of the SCSI bus operation in which the SCSI controller of the present invention is a target and the target receives a write command from a higher-level device and performs processing.

First, in step 20, when a selection request is issued from the host device, the state of the BSY signal on the SCSI control bus 210 and the state of the REQ signal and ACK signal due to the transmission of the write command change. A latch request signal is output from the circuit 121 to the trace memory unit 131. As a result, the states of the signals on the SCSI data bus 200, SCSI control bus 210, processor data bus 250, and processor control bus 260 at this time are stored in the trace memory unit 131.

Further, in step 30, when the SCSI controller 100 notifies the microprocessor 160 of the selection, the microprocessor 160 reads the status of the SCSI controller 100. In this case, since the state of the SCSI controller read control signal changes, the trace control circuit 1
21 outputs a latch request signal to the trace memory unit 131. As a result, the states of the signals on the various buses are stored in the trace memory unit 131 in the same manner as described above.

In steps 40 to 80, similarly to the above, a change in the state of the signal on the SCSI control bus 210 or the access signal to the SCSI controller 100 on the processor control bus 260 is used as a trigger.
The signal states of the various buses are stored in the trace memory unit 131.

In this manner, the status is selected by the host device on the SCSI bus, and the status of the SCSI controller 100 is read from the microprocessor 160.
Issuing a command and receiving the command, the SCSI controller 10
0, SCSI bus and SCSI controller 10 for data transfer operation on SCSI bus
A series of zero access sequences can be stored sequentially.

When the storage area of the trace memory unit 131 is full, trace data is newly written (overwritten) from the beginning of the storage area, and the latest state is always stored in the trace memory unit. .

Next, a case where the occurrence of an abnormality on the SCSI bus is detected and the trace is stopped will be described.
As an example of the bus operation at the time of occurrence of an error, in step 70 of FIG. 4, a termination processing command from the microprocessor 160 to the SCSI controller 100 becomes partially invalid due to some kind of failure. It is assumed that an invalid message has been sent to the host device.

If an invalid message is sent in the message phase of step 80, the abnormality detection circuit 111 detects an abnormality of the SCSI bus and sends a message to the trace control circuit 121.
Output a trace stop request signal. At the same time, an interrupt signal is output to the microprocessor 160. The trace control circuit 121 receives the trace stop request signal, suppresses the generation of the latch request signal, and stops the data update processing of the trace memory unit 131.

The microprocessor 160, having received the interrupt signal from the abnormality detection circuit 111, recognizes that an error has occurred in the SCSI bus, and uses the trace memory read control circuit 140 to read the trace data for analyzing the cause of the error. I do.

In this way, the signal states of the SCSI bus and the processor bus are written and updated in the trace memory unit 131. When an abnormality of the SCSI bus is detected, the update process is stopped and the trace memory unit 131 is stopped.
The microprocessor reads and analyzes the data of the SCSI bus to detect the error of the SCSI bus.
SI data bus 200, SCSI control bus 21
0, the state of the processor data bus 250 and the processor control bus 260 can be known.

FIG. 5 is a block diagram showing a second embodiment of the present invention. In the figure, the SCSI controller 15
2 includes a trace memory read control circuit 141 connected to the serial interface control circuit 300. The serial interface control circuit 300 is connected to the PC for error analysis by the serial interface 320.
It is connected to the PC 310 and reads trace data from the trace memory read control circuit 141 in response to an instruction from the PC for error analysis 310, and sends the read trace data to the PC for error analysis 310 using the serial interface 320.

The cause of the SCSI bus abnormality is the processor data bus 250 or the processor control bus 26.
If the value is 0, reading the trace data from the microprocessor 160 will cause the read trace data to be incorrect and will not be the same as the data actually stored in the trace memory unit. There is a possibility that the address of the trace data to be read does not match the actually read address, and as a result, the data originally required for analysis may not be read.

This embodiment has an effect that by providing a dedicated serial interface as a means for reading out trace data, it is possible to more reliably perform an analysis when an abnormality of the SCSI bus is detected.

Although a serial interface is used in this embodiment, the serial interface control circuit 3
By replacing 00 and the PC 310 for error analysis with means capable of controlling another interface, another interface can be used.

FIG. 6 is a block diagram showing a third embodiment of the present invention. In the figure, the SCSI controller 15
Reference numeral 3 denotes a differential SCSI data bus 201 and a differential SCSI driver via a differential SCSI driver / receiver 400.
It is connected to the control bus 211. In this way, even when the SCSI bus is of a differential type, the S bus according to the present invention can be used.
The CSI control device can be utilized.

In this case, since each block in the SCSI controller 153 is not directly connected to the SCSI bus,
The load on the SI bus can be reduced.

Further, the SCSI control device 153 is configured as shown in FIG.
By using another interface as exemplified in (1), it is also possible to directly read the trace data.

[0038]

As described above, the SCSI controller according to the present invention has the following effects.

The first effect is that when an abnormality of the SCSI bus is detected, the analysis for the occurrence of the abnormality can be performed much easier and in a shorter time. The reason is not only the signal state of the SCSI data bus and SCSI control bus, but also
This is because the signal states of the processor data bus and the processor control bus are stored in the trace memory simultaneously with the signal states of the SCSI bus.

The second effect is that the possibility of overwriting the trace data necessary for the SCSI bus abnormality analysis with the latest trace data can be reduced because the abnormality of the SCSI bus cannot be detected. The reason is SCSI
This is because a circuit for detecting an abnormality of the SCSI bus is provided outside the controller.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a main part of a trace control circuit.

FIG. 3 is a block diagram showing a main part of a trace memory unit.

FIG. 4 is a flowchart showing the operation of the present invention.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a block diagram showing a third embodiment of the present invention.

FIG. 7 is a block diagram showing a conventional example of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 SCSI controller 111 abnormality detection circuit 121 trace control circuit 131 trace memory section 140 trace memory read control circuit 151 SCSI controller 160 microprocessor 200 SCSI data bus 210 SCSI control bus 250 processor data bus 260 processor control bus

Claims (6)

[Claims] 1. A SCSI control device interposed between a SCSI bus and a processor bus, wherein the trace is stored by tracing the processor bus at the same time as the SCSI bus and storing the trace data when an abnormality occurs in the SCSI bus. A SCSI control device which stops tracing of a bus and the processor bus and sends out trace data until the occurrence of the abnormality. 2. A SCSI control device interposed between a SCSI bus and a processor bus, wherein a specific signal of the SCSI bus and the processor bus is used as a trigger to instruct tracing of signals of the SCSI bus and the processor bus. A trace control circuit for storing the signals of the SCSI bus and the processor bus instructed by the trace control circuit; and a trace control circuit for monitoring the SCSI bus and detecting the abnormality when the abnormality is detected. An abnormality detection circuit that sends a stop request signal for the trace being executed and sends an interrupt signal to a higher-level device, and reads out trace data stored in the trace memory unit instructed by the higher-level device that has recognized the interrupt signal. A trace memory read control circuit; A SCSI controller, comprising: a SCSI controller that instructs a device to transfer data between a lower device and the higher device via the SCSI bus. 3. The SCSI controller according to claim 2, wherein said trace control circuit detects a rising / falling edge of a control signal of a SCSI bus and a control signal edge detection circuit for detecting a write control signal to said SCSI controller. A write signal edge detection circuit for detecting a rising / falling edge;
A read signal edge detection circuit for detecting a rising / falling edge of a read control signal to the CSI controller, an OR circuit for transmitting a logical sum signal of the signals transmitted by the edge detection circuits, and a latch request in accordance with the logical sum signal A latch request signal generation circuit for generating a signal, transmitting the signal to the trace memory unit, and suppressing transmission of the latch request signal when receiving a trace stop request signal transmitted by the abnormality detection circuit. SCSI controller. 4. A plurality of data latches according to claim 2, wherein said trace memory unit receives each data of a SCSI bus and a processor bus and sends said data in accordance with said latch request signal. And a memory for sequentially storing the data as trace data, and a memory control circuit for reading trace data from the memory in accordance with a trace data read request signal sent by the trace memory read control circuit. Control device. 5. The SCSI according to claim 2, 3 or 4,
In the control device, the trace memory read control circuit reads the trace data from the trace memory unit when instructed by an external processing device connected without passing through the processor bus. 6. The SCSI control device according to claim 1, wherein the SCSI control circuit is connected to a differential SCSI bus via a differential SCSI driver / receiver. .