JPH1116298A - Code error correcting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up the detecting and correcting processing of bit error of CD-ROM data. SOLUTION: An internal memory control circuit 15 and an external memory control circuit 16 are installed for an input interface 11, an error correcting circuit 12, an error detecting circuit 13 and an output interface to constitute a CD-ROM decoder together with an internal memory 17. The CD-ROM data are stored into the internal memory 17 and the external memory 20 respectively through the input interface and taken into an error correcting circuit 12 from the internal memory 17. Based on the positions and error of bit error calculated by an error correcting circuit 12, error portions are rewritten for the CD-ROM data stored in the internal memory 17 and the external memory 20. The CD- ROM data for which correcting processing is completed are taken into the output interface 14 from the external memory 20 to be transmitted to the host computer side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a CD (Compact Dis
The present invention relates to a code error correction detection device that performs processing in accordance with an error correction code and an error detection code included in data on digital data read from a recording medium such as c) or a DVD (Digital Video Disc).

[0002]

2. Description of the Related Art In a CD-ROM system in which a CD used for digital audio is utilized as a read-only memory (ROM) for digital data, in order to improve the reliability of data read from a disk, the read digital data is read. On the other hand, code error correction processing is performed twice. These correction processes are performed first by a digital signal processing unit common to the audio system, and the CD-
The CD-ROM decoder provided exclusively for the ROM system is configured to execute the second time.

FIG. 7 is a block diagram showing the structure of a CD-ROM system, and FIG. 8 is a diagram showing the structure of data handled by each part of the system. The pickup unit 1 receives the reflected light of the light applied to the disk 2 and extracts the intensity of the light as a change in the voltage value. Pickup controller 3
Controls the reading position of the CD pickup unit 1 with respect to the disk 2 so that the pickup unit 1 can read data stored in the disk 2 in a correct order. In reproducing the disk 2, the disk 2 is driven to rotate at a predetermined speed in accordance with the control of the position of the pickup unit 1 by the pickup control unit 3 in order to keep the linear velocity of the track read by the pickup unit 1 constant. Servo control is performed.

An analog signal processing unit 4 reads a change in the voltage value output from the pickup unit 1 and uses an EFM (Eight to Fourteen Modul) that uses 588 bits as one frame.
ation) signal. As shown in FIG. 8, in the EFM signal, the first 24 bits of each frame are allocated to a synchronization signal, and thereafter, 14 bits are repeatedly allocated to data bits with three connection bits interposed therebetween.
The digital signal processing unit 5 performs EFM demodulation on the EFM signal input from the analog signal processing unit 4 and converts 14 bits to 8 bits. In this EFM demodulation,
8-bit subcode data is generated from the first data bit following the synchronization signal, and 32-byte symbol data is generated from the remaining 32 data bits. Further, CIRC (C
Cross-Interleave Reed-Solomon Code) decoding is performed to generate CD-ROM data in which one frame is composed of 24 bytes. The first code error correction process is completed by this CIRC decoding.

[0005] This CD-ROM data is 24 bytes x
A total of 2352 bytes of 98 frames are treated as one block. Normally (in the case of mode 1), as shown in FIG. 9, the synchronization signal [12 bytes], the header [4 bytes], the user data [2048 bytes], and the error detection code EDC ( Error Detec
Option Code (4 bytes) and Error Correction Code ECC (Error
Correction Code) [276 bytes] is allocated. For this CD-ROM data,
Of the data of one block, 2340 bytes excluding the sync signal of 12 bytes have been scrambled, and are descrambled during reproduction to return to the original state.

[0006] The CD-ROM decoder 6 converts CD-ROM data input from the digital signal processing section 5 into data.
It performs code error correction processing and detection processing based on the error correction code ECC and the error detection code EDC, and outputs the processed CD-ROM data to the host computer.
In the processing in the CD-ROM decoder 6, usually,
After correcting a code error of data by the error correction code ECC, it is confirmed whether or not the code error is correctly corrected by the error detection code EDC. If a code error remains, the code error is corrected again by the error correction code ECC, or the CD-ROM data containing the code error is transferred to the host computer with the error flag added. It is configured to output to a computer.

[0007] The buffer RAM 7 is connected to the CD-ROM decoder 6 and receives a CD-RO signal from the digital signal processor 5.
The CD-ROM data input to the M decoder 6 is temporarily stored in units of one block. The error correction code ECC and the error detection code EDC are added to one block of CD-ROM data.
Requires at least one block of CD-ROM data. Therefore, the necessary 1
A buffer RAM 7 is provided to store CD-ROM data for blocks. The control microcomputer 8 is a so-called one-chip microcomputer having a built-in memory in which a control program is stored.
Control the operation of the ROM decoder 6; At the same time, the control microcomputer 8 temporarily stores command data input from the host computer or subcode data input from the digital signal processing unit 5 in a built-in memory. Thus, the control microcomputer 8 controls the operation of each unit in response to an instruction from the host computer, and causes the CD-ROM decoder 6 to output desired CD-ROM data to the host computer.

[0008]

In the CD-ROM decoder 6, in addition to the process of detecting the error correction of the code error in the CD-ROM data, the CD-ROM decoder 6 receives the CD-ROM data from the digital signal processing unit 5.
ROM data input and CD to host computer
The output of the ROM data is performed in parallel. Then, in accordance with each processing, the CD in the buffer RAM 7 is stored.
-Writing and reading of ROM data are repeated. At this time, the buffer R
Access to the AM 7 is allocated in a time-division manner in byte units or code units for each process.

In general, the CD-ROM decoder 6 completes a process for correcting and detecting a code error in one block of CD-ROM data within one block period. Here, if the predetermined processing cannot be completed within one block period due to the increase in the reproduction speed, the CD-RO continuously input
M data is successively written to the buffer RAM 7, so that the CD-ROM data is left unprocessed in the buffer RAM 7.
7 are left. If such a state continues, the buffer R
The AM 7 enters an overflow state, and the input of CD-ROM data to the CD-ROM decoder 6 must be temporarily interrupted.

In a CD-ROM system, if the reproduction speed of the disk 2 is increased without changing the frequency of the system clock as a reference for the operation of each unit (in the case of double-speed reproduction, etc.), the total number of clocks in one block period decreases. I do.
For this reason, the number of clocks for detecting and correcting a code error in the CD-ROM decoder 6 is insufficient, and the predetermined processing is performed by one.
It is more likely that the task cannot be completed within the block period.
Further, when the frequency of reading data from the buffer RAM 7 for transferring the CD-ROM data to the host computer is increased, the transfer speed of the CD-ROM data itself is increased. However, since reading and writing to and from the buffer RAM 7 for correcting and detecting a code error are time-limited, processing for correcting and detecting a code error in the CD-ROM decoder 6 is delayed.
The possibility that the predetermined processing cannot be completed within the block period is further increased.

[0011] These problems are caused by a double-speed reproduction CD-ROM.
Not only the system, but also DVD
This also occurs in a DVD-ROM system used as M. DVD with storage capacity about 7 times that of CD
In, it is desired that the reproduction speed be higher than that of a CD, and improving the speed of data transfer and decoding (correction detection of a code error) is one of the important issues.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an error correction detection device which is advantageous for increasing the data transfer speed while completing a predetermined process within a predetermined time.

[0013]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized in that digital data including an error correction code and an error detection code read from a recording medium are provided. In the code error correction detection device that performs processing based on the error correction code and the error detection code and transfers the processed digital data to the computer device side, the recording medium is transmitted from the recording medium in block units each including a predetermined number of bytes. An input interface that captures the read digital data, an internal memory that stores the digital data captured by the input interface circuit in block units, and an external memory that stores the digital data in block units together with the internal memory, The digital data stored in the internal memory is fetched and one block After performing a correction process based on the error correction code for each time, a correction circuit that rewrites an error portion of the digital data stored in the internal memory and the external memory, and an error portion that is rewritten by the correction circuit. A detection circuit that fetches the digital data stored in the internal memory, performs a detection process based on the error detection code for each block, and sets an error flag in accordance with a detection result; and a detection circuit stored in the external memory. An output interface for outputting the digital data to an external computer device.

According to the present invention, an operation for correcting a code error is performed based on the data stored in the internal memory, and an error portion of both the internal memory and the external memory is determined according to the result. Rewriting is performed. Since the access to the external memory is stopped while the data is read from the internal memory for the operation of the error correction processing, the data for which the correction processing has been completed can be read from the external memory to the output interface. Therefore, sufficient time for reading data from the external memory to the output interface can be secured.

[0015]

FIG. 1 is a block diagram showing an embodiment of a code error correction detection apparatus according to the present invention, and FIG.
FIG. 4 is a timing chart for explaining a data flow of each unit in the operation. In this embodiment, the CD-RO
The M-decoder 10 and the buffer RAM 20 constitute a code error correction detection device. This CD-ROM
The decoder 10 and the buffer RAM 20 correspond to C shown in FIG.
It corresponds to the CD-ROM decoder 6 and the buffer RAM 7 of the D-ROM system, respectively.

The CD-ROM decoder 10 includes an input interface 11, an error correction circuit 12, an error detection circuit 13,
It comprises an output interface 14, an internal memory control circuit 15, an external memory control circuit 16 and an internal memory 17, to which an external memory 20 is connected. Note that the components of the CD-ROM decoder 10 are integrated on a single semiconductor substrate.

The input interface 11 forms an interface with a digital signal processing section for generating CD-ROM data (FIG. 9) having one block of 2352 bytes, and receives the CD-ROM data to receive an internal memory control circuit 15. And to the external memory control circuit 16. In the input interface 11, the scrambling process is performed on the 2340-byte CD-ROM data excluding the 12-byte synchronization signal, so that the descrambling process is performed at the input stage. At the same time, a synchronization signal is extracted from the CD-ROM data, and a block synchronization signal indicating the start timing of each block is generated. This block synchronization signal is supplied to each section of the CD-ROM decoder 10 and is used for synchronizing the timing of each processing.

The error correction circuit 12 fetches the CD-ROM data in units of one block, and performs a correction process on a code error contained in the block based on an error correction code (ECC) of each block. In the error correction processing of CD-ROM data, one block (2352 bytes) of data is separated into two sets of planes (1176 bytes) of an upper byte and a lower byte, and two series of codes set for each plane. A syndrome operation based on the word (P, Q) is performed. As shown in FIG. 3, the P code word and the Q code word of the ECC are 1 except for the synchronization signal and the ECC.
For 1032 symbol data in the plane, P
According to the sequence and the Q sequence, every 24 pieces and 43
Two pieces are attached to each piece. Thereby, 86 P code words corresponding to 43 sets of symbol data, 26
52 corresponding to the set of symbol data (including the P code word)
And Q codewords are set. Therefore, by performing a syndrome operation on the symbol data including each codeword in the order according to the P sequence and the Q sequence, the position of the code error in the plane and the error caused by the error are calculated. The error correction circuit 12 is configured to correct a code error by adding an error to the symbol data corresponding to the error position based on the calculation result.

The error detection circuit 13 outputs the CD-ROM data (E) whose code error has been corrected by the error correction circuit 12.
(Excluding CC) are sequentially fetched for each block, and arithmetic processing based on an error detection code (EDC) is performed to detect the presence or absence of a code error. Since the EDC itself does not have a function of correcting an error, the error detection circuit 13 is configured to add an error flag to the CD-ROM data and output it when an error is detected. .

The output interface circuit 14 forms an interface with the host computer. In response to an instruction from the host computer, the output interface circuit 14 completes a predetermined process.
D-ROM data is output in block units. If necessary, control information is received from the host computer and supplied to a control microcomputer that controls the operation of each unit.

The internal memory control circuit 15 stores the internal memory 1
7 and controls writing of CD-ROM data from the input interface 11 to the internal memory 17 and reading of CD-ROM data from the internal memory 17 to the error correction circuit 12 or the error detection circuit 13. Further, the internal memory control circuit 15 is configured to rewrite a part of the CD-ROM data stored in the internal memory 17 according to the result of the correction processing in the error correction circuit 12. That is, when the position of the code error is calculated in the error correction circuit 12, the address of the internal memory 17 where the data corresponding to the error position is stored is read, and the data is read and supplied to the error correction circuit 12. I do. Further, after the correction process for the data is completed, the corrected data is written to the same address of the internal memory 17 to complete the rewriting of the data including the error in the internal memory 17.

The external memory control circuit 16 is a CD-ROM
It is connected to an external memory 20 externally connected to the decoder 10, and is connected to the external memory 20 from the input interface 11.
It controls writing of D-ROM data and reading of CD-ROM data from the external memory 20 to the output interface 14. Further, the external memory control circuit 16 is configured to rewrite a part of the CD-ROM data stored in the external memory 20 in accordance with the result of the correction processing in the error correction circuit 12, similarly to the internal memory control circuit 15. Is done. That is, the rewriting process of the error portion is performed on the CD-ROM data stored in the external memory 20 simultaneously with the rewriting process on the CD-ROM data stored in the internal memory 17.

The internal memory 17 is an SRAM (Static Rand).
om Access Memory) and a recording medium that can be freely read and written, and temporarily stores CD-ROM data taken into the input interface 11. The internal memory 17 has a capacity capable of storing at least two blocks of CD-ROM data. Since one block of CD-ROM data in a normal format is composed of 2352 bytes, the capacity of the internal memory 17 needs to be 4.8 Kbytes or more.

The external memory 20 is composed of a readable and writable recording medium similar to the internal memory 17, and temporarily stores CD-ROM data to be transferred to the host computer via the output interface 14. The external memory 20 has no problem in operation as long as it has a capacity capable of storing at least two blocks of CD-ROM data. However, in order to allow a margin for the transfer timing of the CD-ROM data to the host computer, Preferably, the capacity is larger than that of the internal memory 17. For the external memory 20, the CD-ROM decoder 1
Since it is integrated separately from 0, it is easy to increase the capacity as compared with the internal memory 10.

Next, the operation of the above-described code error correction detecting device will be described with reference to FIG. The data S (n) input from the DSP for each block is first input to the input interface 11, and the input interface 11
Are written to the internal memory 17 and the external memory 20, respectively. Data S written to internal memory 17
(n) is parallel to the input of the next data S (n + 1),
The data is read out to the error correction circuit 12 and undergoes a code error correction process. Then, as a result of the correction processing, if there is an error in the data S (n), only the erroneous portion is rewritten to correct data. This rewriting is performed simultaneously on the data S (n) stored in the internal memory 17 and the data S (n) stored in the external memory 20. The data S (n) for which the correction processing has been completed is read from the internal memory 17 to the error detection circuit 13. The operation of reading the data S (n) to the error correction circuit 12 and the error detection circuit 13 is performed during a period (one block period) in which the next data S (n + 1) is input from the preceding digital signal processing unit. To be completed.
The data S (n) stored in the external memory 20 is
The data is sequentially read out to the output interface in response to a request from the host computer.

In the above processing, the access from the internal memory control circuit 15 to the internal memory 17 includes writing of data from the input interface 11 and reading of data to the error correction circuit 12 or the error detection circuit 13. Are allocated in a time-sharing manner. The access from the external memory control circuit 16 to the external memory 20 is assigned to writing data from the input interface 11, writing corrected data from the error correction circuit 12, and reading data from the output interface 14. . While data is read from the internal memory 17 to the error correction circuit 12 or the error detection circuit 13, the external memory 2
Since the access to 0 is stopped, the transfer timing of the CD-ROM data to the host computer can be set in a wide range.

FIG. 4 is a block diagram showing a configuration of an address generating circuit for supplying a write address signal and a read address signal to the internal memory 17 or the external memory 20, and FIGS. 5 and 6 correspond to each address signal. FIG. 3 is a schematic diagram illustrating an example of a usage state of an internal memory 16 and an external memory 20. The address generation circuit includes a first address generator 21, a second address generator 22, a latch 23, and an adder 24. This address generation circuit includes an internal memory 17 and an external memory 20.
Are provided independently for each of the above.

The first address generator 21 is constituted by a counter, and is used for the internal memory 17 or the external memory 2.
In response to 0, as shown in FIGS. 5 and 6, a write address signal WA for designating all storage areas from address 0 to the last address in a predetermined order is generated. The write address signal WA is generated so that after the address position reaches the final address, the address returns to address 0 and the addresses are repeatedly specified in the same order. Therefore, in the internal memory 17 and the external memory 20, the CD-ROM data taken into the input interface 11 is sequentially written according to the input order.

As shown in FIGS. 5 and 6, the second address generator 22 determines a partial area of the internal memory 17 and the external memory 20 corresponding to one block of CD-ROM data for each processing. A cyclic address signal CA for designating in the specified unique order is generated. This cyclic address signal CA
Is generated by reading one block of CD-ROM data in the order according to each sequence of the error correction code when the internal memory 17 is used. For example, as shown in FIG. 3, in accordance with the P sequence of the P code word, data of one block is read out every 42 data and the Q code word is read.
It is generated so that data for one block can be read out every 43 data in accordance with the sequence. In the case of corresponding to the external memory 20, the cyclic address CA is 1
It is generated so that data for a block is read in the same order as the write address.

The latch 23 is connected to the first address generator 21
And latches address information WAh corresponding to the head of each block of data stored in the RAM among the write address signals WA. The latch 23 has a two-stage configuration, and each of the latched head address information WAh
Is shifted by one stage each time the processing for one block progresses.
Thus, in the first row, the head address information WAh in which the head data of the currently input block is stored.
(0) is retained. In the second row, the head address information W of the RAM in which the head data of the block which has been input one block ahead and subjected to the error correction processing is stored.
Ah (1) is held.

The adder 24 includes a second address generator 22
And the second address generator 22
By adding the start address information WAh to the cyclic address signal CA output from the CPU, an actual read address signal RA for the RAM is generated. That is, for the cyclic address signal CA, the top address is address 0, and the storage area of the RAM is specified in a range corresponding to one block. Therefore, the adder 24 adds the top address information WAh to the cyclic address signal CA. By doing, RA
The entire storage area of M can be accessed. For example, as shown in FIG. 5, the head address information WA of the internal memory 17 in which the CD-ROM data of the block n is stored.
By adding h (0) to the cyclic address signal CA, a read address signal RA (0) specifying the area of the block n where the CD-ROM data is stored is generated. As a result, one block of CD-ROM data is read from the internal memory 17 to the error correction circuit 12 or the error detection circuit 13 for correction processing or detection processing. Also, as shown in FIG. 6, the external memory 20 transmits the start address information WAh (0) of the external memory 20 storing the CD-ROM data of the block n to the cyclic address signal C.
By adding to A, a read address signal RA (0) that specifies the area of the block n where the CD-ROM data is stored is generated. As a result, in order to transfer the data to the host computer, the external memory 20 sends the output data to the output interface 14 for one block of the completed CD-ROM.
ROM data is read.

One of the write address signal WA and the read address signal RA generated as described above is selected and supplied to the internal memory 17 and the external memory 20. Normally, input interface 1
1. The error correction circuit 12 and the error detection circuit 13 operate in parallel, and access from each unit to the internal memory 17 or the external memory 20 is allocated in a time division manner in units of one word. At this time, since the operation timing of the external memory control circuit 16 is not directly related to the timing of the read operation of the error correction circuit 12 or the error detection circuit 13,
ROM data can be input / output at any time. Therefore, without waiting for the gap between the operations of the error correction circuit 12 and the error detection circuit 13, the C
D-ROM data can be transferred.

In the above embodiment, a CD-ROM system using a CD as a recording medium has been exemplified.
As a recording medium, a system using other media such as a DVD can be adopted.

[0034]

According to the present invention, a CD-R for error correction processing is stored in an internal memory built in a CD-ROM decoder.
By temporarily storing the OM data, the frequency of input / output of CD-ROM data between the external memory and the CD-ROM decoder can be reduced. Therefore, when transferring the CD-ROM data to the host computer side, the degree of freedom of the read timing from the external memory is expanded, and as a result, the transfer speed of the CD-ROM data can be increased. Further, since the internal memory is integrated on the same substrate as the error correction circuit, the speed of input / output of CD-ROM data between the internal memory and the error correction circuit can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a code error correction detection device according to the present invention.

FIG. 2 is a timing chart for explaining the flow of CD-ROM data.

FIG. 3 is a diagram illustrating an access order of CD-ROM data in an error correction process.

FIG. 4 is a block diagram illustrating a configuration example of an address generation circuit.

FIG. 5 is a schematic diagram illustrating an example of an access state of an internal memory.

FIG. 6 is a schematic diagram illustrating an example of an access state of an external memory.

FIG. 7 is a block diagram illustrating a configuration of a CD-ROM system.

FIG. 8 is a format diagram of data read from a disk.

FIG. 9 is a format diagram of CD-ROM data.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pickup part 2 Disk 3 Pickup control part 4 Analog signal processing part 5 Digital signal processing part 6 CD-ROM decoder 7 Buffer RAM 8 Control microcomputer 10 CD-ROM decoder 11 Input interface 12 Error correction circuit 13 Error detection circuit 14 Output interface 15 Internal memory control circuit 16 External memory control circuit 17 Internal memory 20 External memory

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI G11B 20/18 572 G11B 20/18 572F 574 574E

Claims (3)

[Claims] A digital data including an error correction code and an error detection code read from a recording medium is subjected to processing based on the error correction code and the error detection code, and the processed digital data is transferred to a computer device. In the code error correction detection device, an input interface for taking in digital data read from a recording medium in a block unit composed of a predetermined number of bytes, and an internal unit for storing the digital data taken in by the input interface circuit in a block unit A memory, an external memory for storing the digital data in block units together with the internal memory, and after taking the digital data stored in the internal memory and performing a correction process based on the error correction code for each block. Stored in the internal memory and the external memory A correction circuit for rewriting each error portion of the digital data, and a detection process based on the error detection code for each block in which the error data is rewritten by the correction circuit and the digital data stored in the internal memory is fetched. Code error correction, comprising: a detection circuit for setting an error flag in accordance with a detection result after performing the detection; and an output interface for outputting the digital data stored in the external memory to an external computer device. Detection device. 2. The method according to claim 1, further comprising the steps of: writing the digital data from the input interface or the correction circuit to the internal memory; and reading the digital data from the internal memory to the correction circuit or the detection circuit. An internal memory control circuit for controlling;
An external memory control circuit connected to the external memory and controlling writing of the digital data from the input interface or the error correction circuit to the external memory and reading of the digital data from the external memory to the output interface; The code error correction detection device according to claim 1, further comprising: 3. The code error correction detection device according to claim 2, wherein the internal memory has a capacity capable of storing at least two blocks of the digital data.