JP3995693B2 - Code error correction detection device - Google Patents

Description

  The present invention relates to a code error correction detection apparatus that performs processing according to an error correction code and an error detection code included in data on digital data read from a recording medium such as a CD (Compact Disc) or a DVD (Digital Video Disc).

  In a CD-ROM system that utilizes a CD used for digital audio as a read-only memory (ROM) for digital data, in order to increase the reliability of the data read from the disk, a code error is detected with respect to the read digital data. Correction processing is performed twice. These correction processes are configured to be executed for the first time by a digital signal processing unit common to the audio system and for the second time by a CD-ROM decoder provided exclusively for the CD-ROM system.

  FIG. 7 is a block diagram showing the configuration of the CD-ROM system, and FIG. 8 is a configuration diagram of data handled by each part of the system.

  The pickup unit 1 receives the reflected light of the light irradiated on the disk 2 and extracts the intensity of the light as a change in voltage value. The pickup control unit 3 controls the reading position of the CD pickup unit 1 with respect to the disc 2 so that the pickup unit 1 can read the data stored on the disc 2 in the correct order. During reproduction of the disc 2, the disc 2 is rotated at a predetermined speed in accordance with the control of the position of the pickup unit 1 by the pickup control unit 3 in order to keep the linear velocity of the track read by the pickup unit 1 constant. Servo control is performed as follows.

  The analog signal processing unit 4 reads the change in the voltage value output from the pickup unit 1 and generates an EFM (Eight to Fourteen Modulation) signal with 588 bits as one frame. In the EFM signal, as shown in FIG. 8, the 24 bits at the beginning of each frame are assigned to the synchronization signal, and then 14 bits are repeatedly assigned to the data bits with 3 connection bits interposed therebetween. The digital signal processing unit 5 performs EFM demodulation on the EFM signal input from the analog signal processing unit 4 and converts 14 bits into 8 bits. In this EFM demodulation, 8-bit subcode data is generated from the first data bit following the synchronization signal, and 32-byte symbol data is generated from the remaining 32 data bits. Further, CIRC (Cross-Interleave Reed-Solomon Code) decoding is performed on the 32-byte symbol data to generate CD-ROM data in which one frame is 24 bytes. The first code error correction process is completed by this CIRC decoding.

  In this CD-ROM data, a total of 2352 bytes of 24 bytes × 98 frames is handled as one block. For this one block of data, normally (in the case of mode 1), as shown in FIG. 9, the synchronization signal [12 bytes], header [4 bytes], user data [2048 bytes], error detection code EDC ( An Error Detection Code (4 bytes) and an Error Correction Code (ECC) (276 bytes) are respectively allocated. Further, the CD-ROM data is scrambled to 2340 bytes of the data of one block excluding the synchronization signal 12 bytes, and is descrambled at the time of reproduction to be returned to the original state.

The CD-ROM decoder 6 performs code error correction processing and detection processing based on the error correction code ECC and the error detection code EDC on the CD-ROM data input from the digital signal processing unit 5, and the processing is completed. CD-ROM data is output to the host computer. In the processing in the CD-ROM decoder 6, normally, after a data code error is corrected by the error correction code ECC, it is confirmed whether or not the code error is correctly corrected by the error detection code EDC. If a code error remains, the code error correction process using the error correction code ECC is performed again, or the CD-ROM data containing the code error is stored in the host with the error flag added. Configured to output to a computer.

  The buffer RAM 7 is connected to the CD-ROM decoder 6 and temporarily stores the CD-ROM data input from the digital signal processing unit 5 to the CD-ROM decoder 6 in units of one block. Since the error correction code ECC and the error detection code EDC are added to the CD-ROM data for one block, the CD-ROM decoder 6 requires at least one block of CD-ROM data. . Therefore, a buffer RAM 7 is provided to store one block of CD-ROM data necessary for each process. The control microcomputer 8 is constituted by a so-called one-chip microcomputer having a memory in which a control program is stored, and controls the operation of the CD-ROM decoder 6 according to the control program. At the same time, the control microcomputer 8 temporarily stores the command data input from the host computer or the subcode data input from the digital signal processing unit 5 in the built-in memory. Thus, the control microcomputer 8 controls the operation of each unit in response to an instruction from the host computer, and causes the CD-ROM decoder 6 to output desired CD-ROM data to the host computer.

  In the CD-ROM decoder 6, in addition to the process of correcting and detecting the code error for the CD-ROM data, the input of the CD-ROM data from the digital signal processing unit 5 and the output of the CD-ROM data to the host computer are performed in parallel. Done. In accordance with each process, writing and reading of CD-ROM data to and from the buffer RAM 7 are repeated. At this time, access from the CD-ROM decoder 6 to the buffer RAM 7 is allocated in a time division manner in units of bytes or codes for each processing.

  In general, the CD-ROM decoder 6 completes the processing for correcting and detecting a code error for one block of CD-ROM data within one block period. Here, if the predetermined processing cannot be completed within one block period as the reproduction speed increases, CD-ROM data continuously input is written to the buffer RAM 7 one after another. The ROM data remains in the buffer RAM 7 unprocessed. If such a state continues, the buffer RAM 7 becomes an overflow state, and the input of CD-ROM data to the CD-ROM decoder 6 must be temporarily interrupted.

  In the CD-ROM system, if the reproduction speed of the disk 2 is increased without changing the frequency of the system clock serving as a reference for the operation of each unit (in the case of double speed reproduction or the like), the total number of clocks in one block period decreases. For this reason, there is a high possibility that the number of clocks for detecting and correcting a code error in the CD-ROM decoder 6 will be insufficient, and a predetermined process cannot be completed within one block period. Further, if the reading frequency with respect to the buffer RAM 7 for transferring the CD-ROM data to the host computer is increased, the transfer speed of the CD-ROM data itself is increased. However, since reading and writing to the buffer RAM 7 for correcting and detecting the code error are limited in time, the processing for correcting and detecting the code error in the CD-ROM decoder 6 is delayed. The possibility that the predetermined processing cannot be completed within the block period is further increased.

These problems are not limited to double-speed playback CD-ROM systems,
This also occurs in a DVD-ROM system that uses VD as a ROM. For DVDs with about 7 times the storage capacity of CDs, it is desirable to increase the playback speed over CDs, and it is important to improve the speed of data transfer and decoding (code error correction detection). This is one of the major issues.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an error correction detection apparatus that is advantageous in increasing the data transfer rate while completing predetermined processing within a predetermined time.

  The present invention has been made to solve the above-described problems, and is characterized in that an error correction code and an error are detected with respect to digital data including an error correction code and an error detection code read from a recording medium. In a code error correction detection apparatus that performs processing based on a detection code and outputs processed digital data, an input interface that captures digital data read from a recording medium, and a digital that is connected to an external memory and captured by an input interface circuit An external memory control circuit for controlling the writing of data to the external memory and the reading of the digital data stored in the external memory, an internal memory for storing the digital data taken into the input interface circuit, a write address signal for the internal memory, and Internal supply of read address signal A memory address generating circuit, a correction circuit that takes in digital data stored in the internal memory, performs a correction process based on an error correction code, and then rewrites the error location of the digital data stored in the internal memory and the external memory, respectively , A detection circuit that takes in digital data stored in the internal memory after the error portion has been rewritten by the correction circuit, performs detection processing based on the error detection code, and an output interface that outputs the digital data stored in the external memory to an external device The internal memory address generation circuit includes a first address generator that generates an address signal that specifies all storage areas in a predetermined order, and an address that specifies a part of the storage areas in a specific order. And a second address generator for generating a signal.

  According to the present invention, an operation for correcting a code error is performed based on the data stored in the internal memory, and the error part is rewritten in both the internal memory and the external memory according to the result. Is called. While data is read from the internal memory for error correction processing, access to the external memory is stopped, so that data for which correction processing has been completed can be read from the external memory to the output interface. Accordingly, a sufficient time for reading data from the external memory to the output interface can be secured.

  FIG. 1 is a block diagram showing an embodiment of a code error correction detection apparatus of the present invention, and FIG. 2 is a timing diagram for explaining the flow of data in each part in the operation. In this embodiment, the CD-ROM decoder 10 and the buffer RAM 20 constitute a code error correction detection device. The CD-ROM decoder 10 and the buffer RAM 20 correspond to the CD-ROM decoder 6 and the buffer RAM 7 of the CD-ROM system shown in FIG.

  The CD-ROM decoder 10 includes an input interface 11, an error correction circuit 12, an error detection circuit 13, an output interface 14, an internal memory control circuit 15, an external memory control circuit 16, and an internal memory 17, to which an external memory 20 is connected. The Note that each part of the CD-ROM decoder 10 is integrated on a single semiconductor substrate.

The input interface 11 forms an interface with a digital signal processing unit that generates CD-ROM data (FIG. 9) in which one block is 2352 bytes, and receives the CD-ROM data to receive the internal memory control circuit 15 and the external memory. This is supplied to the control circuit 16. In this input interface 11, the 2340-byte CD-ROM data excluding the 12-byte synchronization signal is scrambled, so that the descrambling process is performed at the input stage. At the same time, a synchronization signal is extracted from the CD-ROM data, and a block synchronization signal indicating the start timing of each block is generated. This block synchronization signal is supplied to each part of the CD-ROM decoder 10 and used for synchronizing the timing of each process.

  The error correction circuit 12 takes in the CD-ROM data in units of blocks, and performs correction processing on code errors included in the blocks based on the error correction code (ECC) for each block. In error correction processing of CD-ROM data, one block (2352 bytes) of data is separated into two sets of planes (1176 bytes) of upper bytes and lower bytes, and two series of codes set for each plane A syndrome operation based on the word (P, Q) is performed. As shown in FIG. 3, ECC P codewords and Q codewords are generated every 24 and 43 according to the P sequence and Q sequence for 1032 symbol data in one plane excluding the synchronization signal and ECC. Two pieces are attached to each piece. Thereby, 86 P code words corresponding to 43 sets of symbol data and 52 Q code words corresponding to 26 sets of symbol data (including P code words) are set. Therefore, by performing a syndrome operation on the symbol data including each code word in the order according to the P sequence and the Q sequence, the position of the code error in the plane and the error caused by the error are calculated. The error correction circuit 12 is configured to correct a code error by adding an error to symbol data corresponding to the error position based on the calculation result.

  The error detection circuit 13 sequentially takes in the CD-ROM data (excluding ECC) in which the code error has been corrected by the error correction circuit 12 for each block, and performs arithmetic processing based on the error detection code (EDC). Detect the presence of errors. Since the EDC itself does not have an error correcting function, the error detection circuit 13 is configured to output an error flag attached to the CD-ROM data when an error is detected. .

  The output interface circuit 14 forms an interface with the host computer, and outputs CD-ROM data for which predetermined processing is completed in units of blocks in response to an instruction from the host computer. If necessary, control information from the host computer is received and supplied to a control microcomputer that controls the operation of each unit.

  The internal memory control circuit 15 is connected to the internal memory 17, writes CD-ROM data from the input interface 11 to the internal memory 17, and CD-ROM data from the internal memory 17 to the error correction circuit 12 or the error detection circuit 13. Is controlled. Further, the internal memory control circuit 15 is configured to rewrite a part of the CD-ROM data stored in the internal memory 17 in accordance with the result of the correction process in the error correction circuit 12. That is, when the position of the code error is calculated in the error correction circuit 12, the address of the internal memory 17 where the data corresponding to the error position is stored is accessed, and the data is read and supplied to the error correction circuit 12. To do. Further, after the correction process for the data is completed, the correction data is written to the same address in the internal memory 17 to complete the rewriting of data including an error in the internal memory 17.

The external memory control circuit 16 is connected to an external memory 20 externally attached to the CD-ROM decoder 10, writes CD-ROM data from the input interface 11 to the external memory 20, and sends data from the external memory 20 to the output interface 14. Controls reading of CD-ROM data. Further, like the internal memory control circuit 15, the external memory control circuit 16 is configured to rewrite a part of the CD-ROM data stored in the external memory 20 in accordance with the correction processing result in the error correction circuit 12. Is done. That is, the rewriting process of the error part is performed simultaneously with the rewriting process for the CD-ROM data stored in the internal memory 17 for the CD-ROM data stored in the external memory 20.

  The internal memory 17 is composed of a recording medium such as SRAM (Static Random Access Memory) that can be freely read and written, and temporarily stores CD-ROM data taken into the input interface 11. The internal memory 17 is formed with a capacity capable of storing at least two blocks of CD-ROM data. Since normal format CD-ROM data is composed of 2352 bytes in one block, the capacity of the internal memory 17 is required to be 4.8 Kbytes or more.

  The external memory 20 is composed of a readable / writable recording medium similar to the internal memory 17 and temporarily stores CD-ROM data to be transferred to the host computer side via the output interface 14. The external memory 20 has no problem in operation as long as it has a capacity capable of storing at least two blocks of CD-ROM data. However, in order to provide a margin for the timing of transferring the CD-ROM data to the host computer side. The capacity is preferably larger than that of the internal memory 17. Since the external memory 20 is integrated separately from the CD-ROM decoder 10, it is easy to increase the capacity compared to the internal memory 10.

  Next, the operation of the above-described code error correction detection apparatus will be described with reference to FIG.

  Data S (n) input for each block from the DSP side is first input to the input interface 11, and is written from the input interface 11 to the internal memory 17 and the external memory 20, respectively. The data S (n) written in the internal memory 17 is read out to the error correction circuit 12 in parallel with the next data S (n + 1) being input, and is subjected to a code error correction process. If there is an error in the data S (n) as a result of the correction process, only the erroneous part is rewritten with correct data. This rewriting is performed simultaneously on each of the data S (n) stored in the internal memory 17 and the data S (n) stored in the external memory 20. The data S (n) for which the correction process has been completed is read from the internal memory 17 to the error detection circuit 13. The read operation of the data S (n) to the error correction circuit 12 and the error detection circuit 13 is performed within a period (one block period) in which the next data S (n + 1) is input from the preceding digital signal processing unit. To complete. The data S (n) stored in the external memory 20 is sequentially read out to the output interface in response to a request from the host computer.

  In the processing as described above, access from the internal memory control circuit 15 to the internal memory 17 is time-divided into writing data from the input interface 11 and reading data from the error correction circuit 12 or the error detection circuit 13. Assigned by Access from the external memory control circuit 16 to the external memory 20 is assigned to writing data from the input interface 11, writing correction data from the error correction circuit 12, and reading data to the output interface 14. . While data is read from the internal memory 17 to the error correction circuit 12 or the error detection circuit 13, access to the external memory 20 is stopped, so that the timing for transferring CD-ROM data to the host computer can be set in a wide range. become.

  FIG. 4 is a block diagram showing a configuration of an address generation circuit for supplying a write address signal and a read address signal to the internal memory 17 or the external memory 20, and FIGS. 5 and 6 show the internal memory 16 corresponding to each address signal. 4 is a schematic diagram illustrating an example of a usage state of an external memory 20.

  The address generation circuit includes a first address generator 21, a second address generator 22, a latch 23 and an adder 24. This address generation circuit is provided independently for each of the internal memory 17 and the external memory 20.

  The first address generator 21 is constituted by a counter, and with respect to the internal memory 17 or the external memory 20, as shown in FIGS. 5 and 6, all storage areas are assigned in a predetermined order from address 0 to the final address. A designated write address signal WA is generated. The write address signal WA is generated so that after the address position reaches the final address, the address is returned to address 0 and the addresses are repeatedly specified in the same order. Therefore, in the internal memory 17 and the external memory 20, the CD-ROM data taken into the input interface 11 is sequentially written according to the input order.

  As shown in FIGS. 5 and 6, the second address generator 22 has a specific area determined for each process in a partial area of the internal memory 17 and the external memory 20 corresponding to one block of CD-ROM data. The cyclic address signal CA specified in the order of is generated. When the cyclic address signal CA corresponds to the internal memory 17, the cyclic address signal CA is generated by reading CD-ROM data for one block in the order according to each sequence of error correction codes. For example, as shown in FIG. 3, data for one block is read every 42 blocks according to the P sequence of the P code word, and data for one block is read every 43 blocks according to the Q sequence of the Q code word. Generated as you can. When the external memory 20 is supported, the cyclic address CA is generated so that one block of data is read in the same order as the write address.

  The latch 23 is connected to the first address generator 21 and latches address information WAh corresponding to the head of each block of data stored in the RAM in the write address signal WA. The latch 23 has a two-stage configuration, and the latched leading address information WAh is shifted by one stage each time processing for one block proceeds. As a result, the first stage holds the head address information WAh (0) in which the head data of the block currently being input is stored. In the second row, RAM leading address information WAh (1) in which the leading data of the block which has been input one block ahead and subjected to error correction processing is stored is held.

  The adder 24 is connected to the second address generator 22 and the latch 23, and adds the head address information WAh to the cyclic address signal CA output from the second address generator 22, so that the actual address for the RAM is increased. A read address signal RA is generated. That is, for the cyclic address signal CA, the top address is 0, and the RAM storage area is specified in a range corresponding to one block. Therefore, the adder 24 adds the top address information WAh to the cyclic address signal CA. This makes it possible to access the entire storage area of the RAM. For example, as shown in FIG. 5, by adding the head address information WAh (0) of the internal memory 17 in which the CD-ROM data of the block n is stored to the cyclic address signal CA, the CD-ROM data of the block n can be obtained. A read address signal RA (0) designating the stored area is generated. Thereby, one block of CD-ROM data is read from the internal memory 17 to the error correction circuit 12 or the error detection circuit 13 for correction processing or detection processing. As for the external memory 20, as shown in FIG. 6, by adding the head address information WAh (0) of the external memory 20 storing the CD-ROM data of the block n to the cyclic address signal CA, the block n A read address signal RA (0) designating an area in which the CD-ROM data is stored is generated. As a result, for transfer to the host computer side, one block of CD-ROM data for which correction processing has been completed is read from the external memory 20 to the output interface 14.

The write address signal WA and the read address signal RA generated as described above.
Is selected and supplied to the internal memory 17 and the external memory 20. Normally, the input interface 11, the error correction circuit 12, and the error detection circuit 13 operate in parallel, and access from each unit to the internal memory 17 or the external memory 20 is assigned by time division in units of one word. At this time, since the operation timing of the external memory control circuit 16 is not directly related to the read operation timing of the error correction circuit 12 or the error detection circuit 13, the CD-ROM data can be transferred to the external memory 20 at any timing. I / O is possible. Therefore, it is possible to transfer the CD-ROM data to the host computer without waiting for a gap between the operations of the error correction circuit 12 and the error detection circuit 13.

  In the above embodiment, a CD-ROM system using a CD as a recording medium has been exemplified. However, the recording medium can also be adopted in a system using another medium such as a DVD.

  According to the present invention, the CD-ROM data between the external memory and the CD-ROM decoder is temporarily stored in the internal memory built in the CD-ROM decoder for error correction processing. -The frequency of input / output of ROM data can be reduced. For this reason, when transferring CD-ROM data to the host computer side, the degree of freedom in reading timing from the external memory is expanded, and as a result, the transfer speed of CD-ROM data can be increased. Further, since the internal memory is integrated on the same substrate as the error correction circuit, the CD-ROM data input / output speed between the internal memory and the error correction circuit can be increased.

It is a block diagram which shows the structure of the code error correction detection apparatus of this invention. It is a timing diagram explaining the flow of CD-ROM data. It is a figure explaining the access order of CD-ROM data in error correction processing. It is a block diagram which shows the structural example of an address generation circuit. It is a schematic diagram explaining an example of the state of access of an internal memory. It is a schematic diagram explaining an example of the state of access of an external memory. It is a block diagram which shows the structure of a CD-ROM system. It is a format figure of the data read from a disk. It is a format diagram of CD-ROM data.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pickup part 2 Disc 3 Pickup control part 4 Analog signal processing part 5 Digital signal processing part 6 CD-ROM decoder 7 Buffer RAM
8 control microcomputer 10 CD-ROM decoder 11 input interface 12 error correction circuit 13 error detection circuit 14 output interface 15 internal memory control circuit 16 external memory control circuit 17 internal memory 20 external memory

Claims (3)

In a code error correction detection apparatus that performs processing based on an error correction code and an error detection code on digital data including an error correction code and an error detection code read from a recording medium, and outputs processed digital data.
An input interface for capturing digital data read from a recording medium;
An external memory control circuit for controlling writing of the digital data to the external memory connected to the external memory and taking in the external interface and reading of the digital data stored in the external memory;
An internal memory for storing the digital data captured by the input interface circuit;
An internal memory address generation circuit for supplying a write address signal and a read address signal to the internal memory;
A correction circuit that captures the digital data stored in the internal memory, performs a correction process based on the error correction code, and then rewrites the error location of the digital data stored in the internal memory and the external memory, respectively.
A detection circuit that takes in the digital data stored in the internal memory after rewriting the error location in the correction circuit, and performs detection processing based on the error detection code;
An output interface for outputting the digital data stored in the external memory to an external device,
The internal memory address generation circuit stores a first address generator for generating an address signal for storing the digital data fetched by the input interface circuit in the internal memory, and stores the digital data in the internal memory for correction processing. A second address generator for generating an address signal for capturing the digital data generated;
A code error correction detection apparatus comprising: 2. The code error correction detection apparatus according to claim 1, wherein the digital data is written to the internal memory from the input interface or the correction circuit, and the correction circuit or the detection circuit is connected to the internal memory. A code error correction detection apparatus, further comprising an internal memory control circuit for controlling reading of the digital data to the memory. 2. The code error correction detection apparatus according to claim 1, further comprising an external memory address generation circuit for supplying a write address signal and a read address signal to an external memory, wherein the external memory address generation circuit is connected to the input interface circuit. A first address generator for generating an address signal for storing the captured digital data in the external memory, and an external device for storing a part of the storage area in a specific order are stored in the external memory. And a second address generator for generating an address signal for taking in the digital data .

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