TW425545B - Coding error correction detection device - Google Patents

Abstract

The present invention provides a coding error correction detection device that speeds up data coding error correction and detection processes. The data is taken into the first error detection circuit 12 at the same time when the input interface 11 writes the input data into buffer RAM 20 in blocks. Data determined to have no coding error in the first error detection circuit 12 may be output from buffer RAM 20 via input interface 15 by omitting coding error correction process in the error correction circuit 13 and coding error detection process in the second error detection circuit 14.

Description

V. Description of the invention (1) '— [Technical field to which the invention belongs] The present invention relates to a digital data read by a large-capacity memory medium such as a CD (compact disc) or DVD (Digital Video Disc). Implement error correction code detection device for data error correction code and error detection code. [Known technology] As a read-only memory for digital data of digital audio CDs ^ 活 In the CD-ROM system in use, in order to improve the reliability of reading the data of the disc, the read digital data is implemented with double codes Error correction processing. This type of correction processing is performed for the first time 'in a digital signal processing section common to the audio system, and for the second time in a dedicated CD-ROM decoder provided in the CD-ROM system. Fig. 4 is a block diagram showing the structure of the CD-ROM system, and Fig. 5 is a diagram showing the structure of data processed by each part of the system. / The pick-up unit 1 receives the reflected light of the light irradiated to the optical disc 2 and takes out the intensity of the light as a change in the voltage value. The pick-up control unit 3 is used to control the The reading position of the optical disc 2 enables the pickup unit 1 to read the data stored in the optical disc 2 in the correct order. The reproduction of the optical disc 2 is to maintain a constant linear speed of the reading track of the pickup unit 1. In conjunction with the control of the position of the pickup unit 1 by the pickup control unit 3, the servo control of the optical disc 2 is driven at a predetermined speed (CLV control). . Or, servo control (cAV control) is performed so that the rotational angular velocity of the disc 2 is kept constant. The analog signal processing unit 4 reads the value of the voltage change output by the pickup unit 1 and generates an EFM (Eigh1; to

C: \ Program Files \ Patent \ 3l〇562.ptd page 4 Δ255 in 5 V. Description of the invention (2)

Fourteen Modulation) signal. The EF MU signal is shown in FIG. 5. The first 24 bits of each frame are allocated as synchronization signals, and the connection bits of every 3 bits thereafter are repeatedly allocated as data bits with 14 bits. The digital signal processing section 5 applies EFM demodulation to the EFM signal input from the analog signal processing section 4 to convert 14 bits into 8 bits. In this EFM demodulation, 8-bit subcode data is generated from the first data bit connected to the synchronization signal, and 32-bit symbol data is generated from the remaining 32 data bits ( Symbol data). Furthermore, the 32-byte symbol data is subjected to CIRC (Cross-Inter leave Reed-So 100m code) decoding to generate 1 frame of CD-ROM data composed of 24 bytes. This circ decoding completes the initial Mar error correction processing. This CD-ROM data is based on a total of 2352 bytes of 24 bytes x 98 frames as one block. For this block of data, usually (in mode 1), as shown in Fig. 6, they are respectively allocated as a synchronization signal [12 bytes], a header [4 bytes] (header), and user data [ 2048 bytes], error detection code EDC (Eri: or Detection Code) [4 bytes] and error correction code ECC (Error Correction Code) [276 bytes]. In addition, this CD-ROM data is "in block 1", except that the 2340 bytes of the synchronization signal are subjected to Scramble processing, and the decryption processing is performed during reproduction. And return to the original state. The CD-ROM decoder 6 performs error code correction processing and detection processing on the CD-ROM data input by the digital signal processing unit 5 according to the error correction code (ECC) and error detection code (EDC). CD-ROM data is input to the host computer. In the processing of such a CD-ROM decoder 6,

—III C: \ ProgramFiles \ Patent \ 310562.ptd Page 5 425545 V. Description of the invention (3) After the error of the data is usually corrected according to ECC, confirm with edc whether the error code has been corrected. If an error code is left, the error code is corrected again by ECC, or the CD-ROM data containing the error code status is rounded to the host computer by adding an error flag (K). The buffer RAM 7 is connected to the CD-ROM decoder 6, and temporarily stores the CD-ROM data from the digital signal processing unit 5 to the CD-ROM decoder 6 in a unit of one frame. ≫ ECC and EDC are added to one frame CD-ROM data, so there must be at least one frame of CD-ROM data in the processing of the CD-ROM decoder 6. Therefore, a buffer RAM 7 is provided so that one frame of CD-ROM data necessary for each process can be stored. The control microcomputer 8 is a so-called single-chip microcomputer having a memory with a memory control program incorporated therein. The operation of the CD-ROM decoder 6 can be controlled by the control program. At the same time, the 'control micro-electric Teng 8' also temporarily stores the command (commmanc [) data input from the host computer or the sub-code data input from the digital signal processing section 5 into the built-in memory. Based on this, the control microcomputer 8 can control the operation of each unit in response to the instruction from the host computer, and output the expected CD-ROM data from the CD-ROM decoder 6 to the host computer. [Problems to be Solved by the Present Invention] In addition to the process of detecting the error code correction of the CD-ROM data, the CD-ROM decoder 6 also inputs the CD-ROM data of the digital signal processing unit 5 and the CD to the host computer. -ROM data output is processed simultaneously. Therefore, in accordance with each process, the operation of writing and reading the CD-ROM data in the buffer RAM 7 is repeated. Each operation of the CD-ROM decoder 6 is controlled according to the instructions of the control microcomputer 8. Therefore, when the CD-ROM system is multifunctional, the control of the microcomputer 8 is controlled.

C: \ ProgramFiles \ Patent \ 310562.ptd Page 6 V. Explanation of the invention (4) Increased burden 'ie' With multifunctionalization, the subcode data of the digital signal processing unit 5 or the instruction of the host computer are taken in When the data is equal to controlling the microcomputer 8, in addition to controlling the operations of each part, the controlling microcomputer 8 must also perform processing such as sub-code data or command data. Therefore, the lack of a spare portion in the control operation of the control microcomputer 8 hinders an increase in the reproduction speed. Therefore, the present invention aims to reduce the burden of controlling the microcomputer and to increase the speed corresponding to the reproduction speed. [Means for Solving the Problem] The present invention was created to solve the above-mentioned problems, and is characterized by performing error correction code correction processing and error detection on digital data including error correction codes and error detection codes read from a recording medium. Code detection processing 'error code correction detection device for computer equipment that has transmitted processed digital data', among which 'equipped with digital data input in a frame unit composed of predetermined bytes is stored in an input interface of the buffer memory (interface ); A first error detection circuit that performs a first detection process on the digital data input to the input interface body according to the error detection code; and corrects the digital data stored in the buffer memory according to the error correction code Process 'and rewrite the above-mentioned digital data error error correction circuit; for the above-mentioned digital data stored in the buffer memory by the above-mentioned error correction circuit rewriting error', a second detection process is performed according to the above-mentioned error detection code, and corresponding to the detection result A second error detection circuit that sets an error flag (error f lag) and The external computer outputs the digital data output interface and the like stored in the buffer memory, and the digital data that cannot be detected by the first error detection circuit cannot be detected.

Mil li ^ w C: \ Program Files \ Patent \ 310562.ptd Page 7 '一 "-4-25545; V. Description of the invention (5) The process of the second error detection circuit is described. According to the present invention, when a code error cannot be detected in the first error detection circuit, since the processing of the error correction circuit and the second error detection circuit is omitted, the data that does not contain a code error is stored in the buffer RAM by the turn-in interface. It is read in the interface as it is and output to the outside. Therefore, the control microcomputer that controls the operation of each part does not need to control the operation of the error correction circuit and the second error detection circuit. [Embodiment of the invention] Fig. 1 is a block diagram showing the first embodiment of the error code correction detection device of the present invention, and Fig. 2 is a timing chart illustrating the data flow of each part in this operation. The error code correction detection device 10 is equivalent to the CD-ROM decoder 6 ′ shown in FIG. 4 and is connected to the buffer RAM 20 and the control microcomputer 30. The error code correction detection device 1 of the present invention is provided by the input interface 11, the first The error detection circuit 12, the error correction circuit 13, the second error detection circuit 14, the output interface 15, the instruction register 16 and the memory control circuit ι7 are configured. Generally, each part of the error correction detection device 10 is formed by being integrated on a single semiconductor substrate. The input interface 11 constitutes an interface between a CD-ROM (Figure 6) formed by a block of 235 2-bytes and a digital signal processing unit, and the CD-ROM data is supplied to the first error detection circuit 11 and memory.体 控制 电路 17。 Body control circuit 17. This input interface 11 is a cryptographic process performed on the 2340-byte CD-ROM data other than the 12-byte sync signal, and a decryption process is performed during the input stage. At the same time, the synchronization signal is taken from the CD-ROM data, and the display is generated. Mm mail C: \ Program Files \ Patent \ 310562.ptd Page 8 4255 45.

A block synchronization signal shown at the front of each block to indicate timing. This block synchronization signal is supplied to each part of the error code correction detection device 10, and is used to synchronize the timing of each operation. The first error detection circuit 12 sequentially takes in the CD-ROM data inputted from the input interface η in each block ', and performs calculation by an error detection code (EDC) to detect the presence or absence of an error in the code. The code error detection result is supplied to the control microcomputer 30. The error correction circuit 13 fetches the CD-ROM data stored in the buffer RAM 20 in units of one block, and corrects the detected code errors according to the error correction code (ECC) detection code error of each block. For example, for two types of code words, the position of the code error and the error due to the error are calculated by performing a 'syndrome' calculation corresponding to each code sequence. Then, the calculation result according to s' is added to the data corresponding to the error position to correct the ma error. The second error detection circuit 14 sequentially takes in the CD-ROM data (except ECC) for which the blocks have been corrected by the error correction circuit 13 in order, and performs arithmetic processing with the error detection code (EDC) to detect the error Yes or no. This second error detection circuit 14 has the same function as the first error detection circuit 12. At this time, 'because EDC does not have the function of correcting the code error, if a code error is detected in the error detection circuit 13', an error flag is added to the cd-ROM data. The output interface circuit 15 constitutes an interface with the host computer, and outputs the CD_ROM data which completes the predetermined processing in block units in response to an instruction from the host computer side. If necessary, the control information on the host computer side can be supplied to the control microcomputer that controls the operation of each part.

The command register 16 is connected to the input interface 11, the first error detection circuit 12, the error correction circuit 13, the second error correction circuit 14, and the output interface 1 5 'to set the operating conditions of each circuit in accordance with the instructions of the control microcomputer 30. That is, the first error detection circuit 12, the error correction circuit 13, and the second error detection 2 circuit 14 constitute a machine that can select individual processing accuracy or whether to execute processing, and the control register 16 is received and stored in the instruction register 16 〇 Provide control instructions for determining conditions. In addition, the input interface body 丨 丨 and the output interface 15 are provided with control instructions for determining the format or rate of data input and output. These control instructions are also supplied by the control microcomputer 30. The memory control circuit 17 is connected between the input interface π, the error correction circuit 13, the second error correction circuit 14 and the output interface 15 and the buffer RAM 20 ′ corresponding to the instructions for controlling the microcomputer in a time division manner to control the sections and the buffer RAM 20 Data input and output. That is, the buffer 1 ^ old0 cannot read and write plural data at the same timing, so the memory control circuit 17 allocates the access of the buffer RAM2 in accordance with the operation timing of each part. The buffer RAM 20 is formed of a representative readable and writable recording medium such as dRAm, SRSM, and the like. The data input by the input interface body 11 is memorized by the memory control circuit 17. The buffer RAM 20 has a capacity capable of storing at least two blocks of CD-ROM data, and temporarily holds the CD-ROM data inputted from the input interface n during the correction processing by the error correction circuit 13 and the detection processing by the second error detection circuit 14. Then, after completing the transfer of the stored CD-ROM data to the host computer side, the CD_ROM data that is input next can be written into this memory area. In addition, if the storage range of the buffer memory 20 is sufficient,

C: \ Program Files \ Patent \ 310562.ptd

Storing CD-ROM data ’can also be transmitted to the main computer side by repeating the same CI> _R0M data. The selection of these operating conditions is determined by the setting of the control register 16 by the control microcomputer. The control microcomputer 30 corresponds to a predetermined control program, and simultaneously performs the operation of the error code correction detection device 10 and the operation of the device connected to the previous stage. For control, the control instruction is set in the instruction register 16. That is, the control microcomputer 30 sets the instructions for setting the respective operating conditions in the instruction register 16 'so that the error code correction detection device 10 need not continue to supply control instructions. Accordingly, various devices' other than the error code correction detection device 10 can be operated in a time division manner. In addition, the computer 30 sets a control flag for stopping the operation of the error correction circuit 13 and the second error detection circuit 14 in accordance with the detection result of the first error detection circuit 12 under this tilt control. That is, when the first error detection circuit 12 determines that the data taken into the input interface 11 is error-free, the error correction processing in all the error correction circuits 13 and the error detection processing in the second error detection circuit 14 can be omitted. The control microcomputer 30 sets a control flag to the instruction register 16. The operation of the above-mentioned error code correction detection device will be described with reference to FIG. 2. The figure shows the situation where the buffer RAM 20 stores 2 blocks of data S (η). The data S (n) in block 1 is input from the device in the previous section. The input interface 11 is input first, and then the input interface 11 is written into the buffer RAM 20 through the memory control circuit 17, and the first error detection circuit is also taken. 12. Then, the first error detection circuit 12 performs a code error detection process in each block > sends a message whether the block data S (η) contains a code error to the control microelectronics 膘

A: V3ia562, ptd Page ^ 425545 V. Description of the invention (9) 30 ° If the data S (n) contains a code error (for example, n = i), first, the data S (η) is fetched by the buffer RAM20. The input error correction circuit 13 performs a predetermined correction process and rewrites a code error portion of the data s (n) stored in the buffer RAM 20. Then, the data s (n) whose code error has been rewritten (corrected) is fetched from the buffer RAM 20 into the second error detection circuit 14 to perform the second error detection process. Then, in response to the instruction from the host computer side, the data S (n) stored in the buffer Mm20 is output from the output interface 15 to the host computer side. On the other hand, if the data S (n) does not contain a ma error (for example, when n = 2), the data g (n) is not taken into the error correction circuit 13 and the second error detection circuit 14 and the data S (n) It is output from the buffer RAM 20 to the host computer side via the output interface 15 as it is. The above-mentioned processing should be performed on the data S (n) which is determined to be a codeless error by the first error correction circuit 12, that is, the operation control of the error correction circuit 13 and the second error detection circuit 14 is not required. Therefore, it is possible to reduce the burden on the control microcomputer 30 during this period, and it is possible to easily cope with the high-speed or multifunctional reproduction speed. Further, since the access operation of the buffer RAM 20 by the error correction circuit 13 and the second error detection circuit 14 is reduced, the time allocated to transfer the CD-ROM data from the buffer RAM 20 to the host computer becomes longer. Therefore, CD-ROM and data transfer speed can be improved. It is particularly effective when buffering the wide-ranging CD-ROM data of RAM 10 or more and storing the CD-ROM data of multiple blocks, and transferring it to the host computer. Fig. 3 is a block diagram showing a second embodiment of the error code correction detection device according to the present invention.

5. Description of the invention (10) In this embodiment, the control flag of the instruction register 6 is set directly according to the detection result of the first error detection circuit 12. That is, the error code correction detection device 10 is different from the error register correction detection device 10 shown in Fig. 1 only in the instruction register 16. The detection results of the first error detection circuit 12 are directly taken in, and the control flags for stopping the operation of the error correction circuit 13 and the second error detection circuit 14 are set. Therefore, the control microcomputer 30 need not correspond to the detection result of the first error detection circuit 12, and the burden of setting the control flag 'in the instruction register 16 is further reduced. " In the above embodiment, although the CD ^ ⑽ system using a CD as a recording medium is taken as an example ', the recording medium may be other media systems such as a DVD or a muscle. ^ [Effect of the invention] According to the present invention, correction processing and correction processing are performed for input data code errors. Therefore, it is possible to reduce the control load, which is beneficial to speeding up the operation, or it is possible to transfer the free time to the computer side when the processing is omitted. Therefore, the data transmission speed can be increased. If a code error is not included, it may be possible to omit the detection of the code error for the ^ confirmation. The microcomputer that controls the processing operations is now multifunctional. In addition, since the transmission efficiency of the CD-ROM data allocated to the host can be saved between provinces, the result can be fascinated. [Simplified description of the drawing] The i-th implementation of the correction detection device. Illustration. Fig. 2 is a timing chart for explaining the data flow. Fig. 3 is a diagram showing an error code of the present invention. Second implementation of correction detection device

d 2 55 4 5 V. Description of the invention (π) Form block diagram. Fig. 4 is a block diagram showing the structure of a CD-ROM system. Fig. 5 is a data format diagram read from an optical disc. Fig. 6 is a format diagram of CD-ROM data. [Explanation of symbols] 1 pickup unit 2 optical disc 3 pickup control unit 4 analog signal processing unit 5 digital signal processing unit 6 CD-ROM decoder 7 buffer RAM 8 control microcomputer 10 '1 0' error code correction detection device 11 input Interface 12 First error detection circuit 13 Error correction circuit 14 Second error detection circuit 15 Output interface 16, 16 'instruction register 17 Memory control circuit 20 Buffer RAM 30, 30' control microcomputer

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Claims (1)

-425545 6. Scope of patent application 1. An error code correction detection device for correcting the error correction code and error detection code digital data that is read from a recording medium, and performing correction processing according to the error correction code and error detection code. Detection processing, and transmitting the processed digital data to the code error correction detection device on the computer side, including: storing digital data input in a block unit composed of a predetermined number of bytes in an input interface of a buffer memory; A first error detection circuit that performs first detection processing on the digital data input to the input interface according to the error detection code; and performs correction processing on the digital data stored in the buffer memory according to the error correction code. To rewrite the error correction circuit of the above-mentioned digital data error part; to perform the second detection processing according to the above-mentioned error detection code on the above-mentioned digital data that is stored in the buffer memory by the above-mentioned error correction circuit overwriting the wrong place, and corresponding to the detection result A second error detection circuit for setting an error flag; and The digital data of the buffer memory is output to an output interface of an external computer, etc .; if the digital data of the first error detection circuit does not detect an error, the digital data in the error correction circuit and the second error detection circuit are omitted. Processor. 2. For example, the error code correction detection device described in item 1 of the scope of patent application, the device is provided with a detection result corresponding to the above-mentioned second error detection circuit ′, and the setting instruction indicates the above-mentioned error correction circuit and the above-mentioned second error detection circuit C: \ Programnies \ Patem \ 310562.ptd Page 15 4 255 4 5 VI. Patent register Register register of the stop flag of action C: \ Program Files \ Patent \ 310562.ptd page 16