JP3628532B2 - Digital playback device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital playback device that includes a buffer memory such as an MD (mini disk) device and that decompresses and plays back compressed data.
[0002]
[Prior art]
In a conventional MD device, when a music signal is reproduced, a signal read from a mini-disc is subjected to C1 correction, C2 correction, and descrambling processing in this order by a signal processing circuit based on an error correction code. Finally, after sequentially becoming 1 byte (8 bits) data and 1 bit byte flag corresponding to the data, it is written in a dynamic RAM (hereinafter referred to as DRAM). This byte flag indicates the possibility that an error remains in the data after correction. When the binary logic is 1, the possibility is high. When the binary logic is 0, the possibility is high. Is small.
[0003]
Note that the C1 code and the C2 code are both Reed-Solomon codes, and C2 encoding, interleaving, and C1 encoding are performed during recording, and the reverse is performed during reproduction. The C1 correction and the C2 correction are related to the C1 encoding and the C2 encoding, respectively. The DRAM is a buffer memory (seismic memory) provided to absorb shocks.
[0004]
After the data and the byte flag written in the DRAM as described above are read at regular intervals, the audio decompression unit performs the first error processing and the second error processing, and after the decompression processing is performed. The music signal is output to the outside of the digital device via the D / A converter.
[0005]
Here, for convenience of explanation, in the first error process described above, when it is determined that an error cannot be repaired in the subsequent decompression process based on the data format detection and the presence / absence of a byte flag error. In the meantime, a rough error process is performed in which the same correct previous half sound group data (hereinafter referred to as the last correct half sound group data) is sent to the next stage, while the second error process is as follows. It is assumed that detailed error processing for correcting data so as to reduce the original sound is performed based on the information in the half sound group data.
[0006]
By the way, the capacity of the work RAM of the audio processing unit may be much smaller during the decompression process than during the data compression process, and thus corresponds to the difference between the compression process and the decompression process during the decompression process. A part of the capacity to be used is used for storing one half sound group data for the first error processing.
[0007]
[Problems to be solved by the invention]
In recent years, reproduction-only MD reproduction apparatuses have become widespread, and the entire system is dedicated to reproduction, and cost reduction has become an indispensable matter by simplifying the hardware configuration.
[0008]
However, in the above conventional technique, the work RAM area (capacity) for the previous correct half sound group data is secured on the voice decompression unit side in order to always hold the previous correct half sound group data at the time of the first error processing. For this reason, there is a problem that the cost increases as a whole.
[0009]
The present invention has been made in view of the above-mentioned problems, and its object is to reduce the cost as a whole by eliminating the need for providing a work RAM area for each channel on the voice decompression unit corresponding to the immediately preceding correct half sound group data. An object of the present invention is to provide a digital playback device that can be reduced.
[0010]
[Means for Solving the Problems]
Book In order to solve the above problems, the digital playback device of the invention provides Error correction processing based on error correction code is performed From signal processing system , Half sound group data Error processing and decompression processing are performed based on information in the half sound group data. The digital playback apparatus that transfers to the decompression processing system and plays back is characterized by the following measures.
[0011]
That is, in the digital playback device, the signal processing system is configured to determine whether the half sound group data can be restored during the decompression process, and the determination result of the half sound group data and the determination means. And store And function as an earthquake-resistant memory And a register means for recording only the address corresponding to the previous half sound group data without error among the half sound group data read from the buffer memory, and the determination result is stored in the buffer memory. When the determination result indicates that the half sound group data to be read and decompressed cannot be restored during the decompression process, the half sound group data stored at the address recorded in the register means is It is characterized in that it is read from the buffer memory and transferred to the decompression processing system instead.
[0012]
According to the above invention, the half sound group data is transferred from the signal processing system to the expansion processing system, and is subjected to the predetermined expansion processing and reproduced. The transfer of the half sound group data to the decompression processing system is performed as follows.
[0013]
It is judged by the judging means whether or not each half sound group data can be restored during the decompression process. The half sound group data and the determination result by the determining means related to the half sound group data are stored in the buffer memory.
[0014]
Of the half sound group data read from the buffer memory, only the address corresponding to the previous half sound group data without error is recorded in the register means. That is, not the half sound group data immediately before an error is recorded, but only the address corresponding to the half sound group data is recorded in the register means.
[0015]
When each half sound group data is transferred from the signal processing system to the decompression processing system, the determination result is read from the buffer memory. When the read result indicates that the half sound group data to be decompressed cannot be restored during the decompression process, the address recorded in the register means is accessed to the buffer memory, and the The half sound group data stored in the address is read from the buffer memory and transferred to the decompression processing system instead. As a result, error-free half sound group data is always transferred to the decompression processing system.
[0016]
As described above, the register means is provided not in the decompression processing system but in the signal processing system. Among the half sound group data read from the buffer memory, the correct half sound group data immediately before there is no error. Only the address corresponding to is recorded in the register means. Therefore, unlike the prior art, it is not necessary to always hold the previous correct half-sound group data itself in the work RAM of the decompression processing system. Therefore, a work RAM area for one sound group data can be provided in the speech decompression system. It becomes unnecessary, and the cost of the entire apparatus can be reduced.
[0017]
Book In order to solve the above problems, the digital playback device of the invention provides The present invention In the digital reproduction apparatus according to the above, the determination means creates a 1-bit flag based on whether or not the corresponding data in the half sound group data match each other and the presence or absence of an error in the byte flag. Based on the above, it is determined whether or not the half sound group data can be restored during the decompression process.
[0018]
According to the above invention, the above In addition to the above action, the 1-bit flag is created by the judging means based on whether or not the corresponding data in the half sound group data match each other and the presence or absence of an error in the byte flag. Based on the flag created in this way, it is judged by the judging means whether or not the half sound group data can be restored during the decompression process.
[0019]
As a result, whether half sound group data consisting of a large number of bits can be restored during the decompression process can be determined based on the flag of only one bit, and therefore the determination can be simplified. Moreover, since the determination criterion is a 1-bit flag, the buffer memory is not burdened with capacity when storing it.
[0020]
Also book In order to solve the above problems, the digital playback device of the invention provides Error correction processing based on error correction code is performed From signal processing system , Half sound group data Error processing and decompression processing are performed based on information in the half sound group data. The digital playback apparatus that transfers to the decompression processing system and plays back is characterized by the following measures.
[0021]
That is, in the digital playback device, the signal processing system is configured to determine whether the half sound group data can be restored during the decompression process, and the determination result of the half sound group data and the determination means. And store And function as an earthquake-resistant memory A buffer memory, a first address corresponding to the half sound group data immediately before no error among the half sound group data read from the buffer memory, In a position other than the previous half sound group data with no error Register means for recording a second address corresponding to the half sound group data, reading the judgment result from the buffer memory, and restoring the half sound group data to be decompressed by the judgment result during the decompression process If it is not possible, the half sound group data stored in the first address or the second address recorded in the register means is read from the buffer memory and transferred to the decompression processing system instead. It is characterized by.
[0022]
According to the above invention, the half sound group data is transferred from the signal processing system to the decompression processing system, and is subjected to a predetermined decompression process and reproduced. The transfer of the half sound group data to the decompression processing system is performed as follows.
[0023]
It is judged by the judging means whether or not each half sound group data can be restored during the decompression process. The half sound group data and the determination result by the determining means related to the half sound group data are stored in the buffer memory.
[0024]
Register means for recording the first address corresponding to the previous half sound group data without error among the half sound group data read from the buffer memory and the second address corresponding to the predetermined half sound group data. To be recorded. That is, the half sound group data immediately before an error and the predetermined half sound group data itself are not recorded, but only their corresponding addresses are recorded in the register means.
[0025]
When each half sound group data is transferred from the signal processing system to the decompression processing system, the determination result is read from the buffer memory. If the read result indicates that the half sound group data to be decompressed cannot be restored during the decompression process, the first or second address recorded in the register means for the buffer memory Is accessed, and the half sound group data stored at the address is read from the buffer memory and transferred to the decompression processing system instead. As a result, half sound group data without error or predetermined half sound group data is always transferred to the decompression processing system.
[0026]
As described above, the register means is provided not in the decompression processing system but in the signal processing system. Among the half sound group data read from the buffer memory, the correct half sound group data immediately before there is no error. And a second address corresponding to predetermined half sound group data are recorded in the register means. Therefore, as in the prior art, it is not necessary to always hold the previous correct half sound group data itself or the predetermined half sound group data itself in the work RAM of the decompression processing system. It is not necessary to provide a region in the voice decompression system, and the cost of the entire apparatus can be reduced.
[0027]
In addition, when it is determined that the half sound group data to be decompressed cannot be repaired during the decompression process, the decompression process is performed based on the listener's audibility, and thus the degree of participation in the listener's playback process. Becomes larger, and the listener's audibility can be reflected.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below with reference to FIGS.
[0029]
An MD apparatus is illustrated as a digital playback apparatus according to the present invention, and the present invention will be described below through playback of the MD apparatus.
[0030]
The MD device has a configuration as shown in FIG. According to this MD apparatus, during reproduction, the optical pickup 2 irradiates the mini-disc 1 with laser light (not shown), and the RF signal (modulation) recorded on the mini-disc 1 based on the reflected light from the mini-disc 1. Audio data) is detected.
[0031]
This RF signal is sent to the RF amplifier 3, amplified there, and then sent to the signal processing circuit 4. The signal processing circuit 4 performs frame synchronization and demodulation, and C1 error correction and C2 error correction based on an error correction code. After a 1-bit byte flag is created for 1 byte of data, sector synchronization and descrambling are performed. The process is performed and sent to the error determination circuit 5.
[0032]
The error determination circuit 5 detects the HSG flag indicating whether or not the half sound group data can be repaired, and then writes it in the DRAM 6 together with the byte flag in real time.
[0033]
In FIG. 1, the spin motor 10 is provided for rotating the mini disk 1. The feed motor 11 is provided to move the optical pickup 2 in a direction perpendicular to the track of the mini disk 1. The driver circuit 13 is provided to supply power to the spin motor 10, the feed motor 11, and a drive device (not shown) that drives the objective lens (not shown) of the optical pickup 2. It has been. The servo circuit 12 feedback-controls each device driven by the driver circuit 13 so that the operation of causing the light emitted from the optical pickup 2 to follow the target track of the mini disk 1 is accurately performed.
[0034]
At the time of reading from the DRAM 6, only the address of the DRAM where the previous correct half sound group data is written is always held in a register (not shown) in the error processing circuit 7. If the HSG flag corresponding to the data and byte flag to be transferred to the voice decompression circuit 8 is correct (if not an error), the data and byte flag are transferred as they are, but if the answer is incorrect (error) The data in the DRAM written in the address held in the register in the error processing circuit 7 (that is, the correct half sound group data immediately before the HSG flag is always correct) is the next stage voice decompression circuit. 8 is sent.
[0035]
The audio decompression circuit 8 first performs detailed error processing for correcting data so as to reduce the original sound based on information in the half sound group data, and then performs decompression processing to perform D / A converter 9. Here, after being converted from a digital signal to an analog signal, it is output as sound.
[0036]
All the above processing is centrally managed by the system microcomputer 15. In addition, operating power is appropriately supplied to the optical pickup 2, the servo circuit 12, the driver circuit 13, and the system microcomputer 15 via a power ON / OFF circuit. The audio decompression circuit 8 performs detailed error processing and decompression processing, but is not a main part of the present invention, and thus detailed description thereof is omitted.
[0037]
The details of the present invention will be described below with reference to FIGS.
[0038]
First, a format example of sound group data input to the error determination circuit 5 (see FIG. 1) will be described with reference to FIG. The sound group data (consisting of 424 bytes) is the minimum unit of a digital signal input to the audio decompression circuit 8 in FIG. 1, and one half sound is provided for each of the L channel (left channel) and the R channel (right channel). It consists of group data (consisting of 212 bytes).
[0039]
In the format example shown in FIG. 2, the first BSM (Block Size Mode) at the 0th byte, the first SIA (Sub Information Amount) at the first byte, the first WL (Word Length) at the second byte, 3 The first SF (Scale Factor) in the byte, the first ASD (Audio Spectrum Data) in the fourth byte, the second SF in the 208th byte, the second WL in the 209th byte, the 210th byte The second SIA and the second BSM of the 211th byte are stored in order from the head for each channel.
[0040]
Here, the BSM indicates data related to a block size when performing IMDCT (Inverse Modified Discrete Cosine Transform), WL indicates data indicating the data length of the ASD, and SF indicates the data The data showing the scale factor of ASD is shown, and the SIA shows the data of the number of WLs and SFs. The first data and the second data are basically the same, but the second WL and the second SF may not exist. The byte group obtained by the signal processing circuit 4 is added to the sound group data shown in FIG.
[0041]
The error determination of the sound group data for each half sound group data and writing of the HSG flag to the DRAM 6 will be described below. Note that the error determination performed for the L channel and the R channel is the same, and therefore, the description for each channel is omitted.
[0042]
First, in step 1, in the 0th byte data (first BSM) and the 211th byte data (second BSM), a comparison is made as to whether both data match each other, and both byte flags An error is detected. As a result, the intermediate flag is set to 1 of binary logic only when both data are different from each other or both byte flags have an error, otherwise the intermediate flag is set to 0 of binary logic. Is done.
[0043]
Next, in step 2, as in step 1 above, whether the first byte data (first SIA) and the second byte data (second SIA) match each other. A comparison is made and whether or not there is an error in both byte flags is detected. As a result, if both data are different from each other, or if both byte flags have an error, the intermediate flag is set to 1 of binary logic, otherwise the intermediate flag is set to 0 of binary logic. Is done.
[0044]
Then, in step 3, bits 3 and 4 (the least significant bit is set to bit 0 and the lowest bit is set in each of the data (first SIA) of the first byte and the data (second SIA) of the 210th byte). It is determined whether or not both upper bits are bit 7). Here, bits 3 and 4 indicate whether or not the data at the 209th byte is WL. When both the bits 3 and 4 are 0, it is determined that the data at the 209th byte is not WL. In other cases, it is determined that the data of the 209th byte is WL.
[0045]
In step 4, when it is determined in step 3 above that the data at the 209th byte is not WL, if the byte flag is 0 in binary logic, the intermediate flag is set to 0 in binary logic, while When the flag is 1 in binary logic, the intermediate flag is set to 1 in binary logic.
[0046]
On the other hand, if it is determined in step 3 that the 209th byte data is WL, the second byte data (first WL) and the 209th byte data (first WL) are the same as in step 1 above. In the second WL), a comparison is made as to whether or not both data match, and the presence or absence of an error in both byte flags is detected. As a result, if both data are different from each other, or if both byte flags have an error, the intermediate flag is set to 1 of binary logic, otherwise the intermediate flag is set to 0 of binary logic. Is done.
[0047]
As described above, a total of four types of intermediate flags are generated for each half sound group data based on Steps 1 to 4. Of these, when one of the binary logic is 1, the binary logic is 1, and when all the intermediate flags are 0, the binary logic is 0. The HSG flag of the sound group data is written in the HSG flag area in the DRAM 6 together with the corresponding data and byte flag. At this time, the addressing for the byte flag and the HSG flag is simplified so as to be obtained simply by decoding the address of the data.
[0048]
A map of the DRAM 6 in such a case is shown in FIG. As shown in FIG. 3, the byte flag corresponds to 1 bit for 1 byte of data (8 bits), and the HSG flag corresponds to 212 bytes of data (1696 bits: one half sound group data length). Corresponds to 1 bit. Therefore, when the data area is set to A bytes, at least a capacity of (A / 8) bytes is required as the byte flag area, and a capacity of (A / 1696) bytes is required as the HSG flag area.
[0049]
Here, the process from reading the half sound group data from the DRAM 6 to sending it to a voice decompression unit (not shown) in the voice decompression circuit 8 will be described below with reference to FIG.
[0050]
In FIG. 4, SGRQT which is a transfer reference clock is a clock having a predetermined cycle and a duty ratio of 50%. Conventionally, when SGRQT is 1 in binary logic, 212 bytes of data for the L channel and the corresponding byte flag are read from the DRAM 6, while when SGRQT is 0 in binary logic, 212 bytes of data for the R channel are read. And the corresponding byte flag are read from the DRAM 6 and transferred to the voice decompression unit as they are.
[0051]
On the other hand, according to the present embodiment, the HSG flag is read from the HSG area in the DRAM 6 immediately before transfer to the audio decompression unit (decompression processing system) of each channel, and an error result signal is output in the HSG flag register 4. Once held as HFG. When this error result signal HFG is 0 in binary logic (corresponding to the case where data is correct), the same address CAO as in the prior art is selected, while in the case where HFG is 1 in binary logic (data is incorrect) The address of the last correct half sound group data (hereinafter referred to as the last correct half sound group data) with the shortest time (LAO for the L channel, RAO for the R channel). Is selected.
[0052]
Therefore, not only the start address is loaded into the address counter 21 of the DRAM 6 by the system microcomputer 15 but also the L channel address holding register 22 and the R channel address register 23 are correctly started corresponding to each channel. The address is loaded.
[0053]
In FIG. 4, the master clock is a clock having a frequency sufficiently higher than the SGRQT, and the selection circuit 25 selects and outputs the LAO when the SGRQT is binary logic 1, while the binary logic In the case of 0, the selector selects and outputs RAO. The selection circuit 26 selects and outputs the CAO when the HFG (HSG flag to be transferred at present) is 0 of binary logic, and outputs 1 when the binary logic is 1 (when there is an HSG error). Is a selector that selects and outputs the output of the selection circuit 25 described above. The selection circuit 27 selects and outputs the output of the DECA 30 (described later) when the HFA (described later) is 0 of binary logic, while the selection circuit 27 of the above-described selection circuit 26 when the binary logic is 1. A selector that selects and outputs an output.
[0054]
In FIG. 4, ACK 28 is a circuit that generates a clock pulse in synchronization with the edge of SGRQT. In addition, the correct latch pulse generation circuit 29 is based on the input master clock, HFG, and SGRQT, and the clock pulse only when each channel is correct (when the correct answer is L channel, the correct latch pulse LCK and R channel is correct). In the case of a correct answer, the circuit generates a correct answer latch pulse RCK). Further, the DECA 30 is a circuit that decodes the HSG address (the address of the HSG flag area) from the data address based on the input SGRQT. The CNT 31 generates a clock based on the input SGRQT and generates the HSG flag. This is a circuit for sending to the register 24 and generating the HFA and sending it to the selection circuit 27.
[0055]
In FIG. 4, an AND gate 32 is a circuit that uses the read data RAD from the DRAM 6 as data to be sent to the voice decompression unit only when the HFA is 1 in binary logic, and the DECB 33 This circuit generates 212 clocks only when the value logic is 1.
[0056]
A specific example of reading from the DRAM 6 will be described below with reference to the timing chart of FIG. 5 corresponding to FIG.
[0057]
First, L0ad and R0ad are loaded from the system microcomputer 15 to the L channel address holding register 22 and the R channel address holding register 23 as correct answer addresses, respectively. The DRAM address counter 21 counts up in synchronization with the clock input to the clock terminal, and sequentially outputs L1, R1, L2, R2, L3, R3, L4, R4... As CAO. ing.
[0058]
In synchronization with the rise of SGRQT from 0 to 1 of the binary logic, an address corresponding to L1 data (hereinafter referred to as L1ad) from the DRAM address counter 21 is set as CAO and the L channel address holding register 22 and the R channel address holding Each is output to the register 23.
[0059]
At point A in the HFA in FIG. 5, the address corresponding to the HSG flag area related to the L1 data is set as the read address RAA for the DRAM 6, and then the DRAM 6 is accessed. The HSG flag of the L1 data is read from the DRAM 6 as read data RAD and input to the HSG flag register 24. At this time, HFG is output from the HSG flag register 24, but it is 0 in binary logic (that is, corresponding to the correct answer) (see HFG in FIG. 5), so the correct answer from the correct latch pulse generation circuit 29 is correct. A latch pulse LCK is generated and output to the clock terminal of the L channel address holding register 22.
[0060]
As a result, the input L1ad is output from the L channel address holding register 22 as LAO. The selection circuit 25 outputs L1ad (LAO) to the selection circuit 26 because SGRQT is 1 in binary logic. The selection circuit 26 outputs the output CAO (L1ad) of the DRAM address counter 21 to the selection circuit 27 because HFG is 0 of binary logic. Since the HFA is 1 of binary logic, the selection circuit 27 outputs CAO (L1ad), which is the output of the selection circuit 26, as the read address RAA of the DRAM 6. Therefore, the read data RAD from the DRAM 6 is L1 data. Since HFA is 1 of binary logic, data ATDT sent to the voice decompression unit is L1 data which is read data RAD.
[0061]
Next, in synchronization with the fall of SGRQT from 1 to 0 of the binary logic, the address corresponding to the R1 data (hereinafter referred to as R1ad) from the DRAM address counter 21 is designated as CAO and the L channel address holding register 22 and Each is output to the R channel address holding register 23.
[0062]
At point B in the HFA in FIG. 5, the address corresponding to the HSG flag area related to the R1 data is set as the read address RAA for the DRAM 6 as the read address RAA for the DRAM 6, and then the DRAM 6 is accessed.
[0063]
The HSG flag of R1 data is read from the DRAM 6 as read data RAD and input to the HSG flag register 24. At this time, HFG is output from the HSG flag register 24, but it is 1 in binary logic (that is, corresponding to the case of incorrect answer) (see HFG in FIG. 5). The correct latch pulse RCK is not generated.
[0064]
Therefore, the correct start address R0ad is output from the R channel address holding register 23 as the address RAO. The selection circuit 25 outputs the correct start address R0ad (RAO) to the selection circuit 26 because SGRQT is 0 in binary logic. The selection circuit 26 outputs the correct start address R0ad (RAO) to the selection circuit 27 because HFG is 1 of binary logic. The selection circuit 27 outputs the RAO (correct answer start address R0ad) output from the selection circuit 26 as the read address RAA of the DRAM 6 because the HFA is 1 of binary logic. Therefore, the read data RAD from the DRAM 6 is R0 data written to the correct start address R0ad. Since HFA is 1 of binary logic, data ATDT sent to the voice decompression unit is R0 data which is read data RAD, not R1 data corresponding to CAO which is the output of DRAM address counter 21, R0 data (immediately correct half sound group data).
[0065]
Then, in synchronization with the rising of SGRQT from 0 to 1 of the binary logic, the address corresponding to the L2 data from the DRAM address counter 21 (hereinafter referred to as L2ad) is set as CAO and the L channel address holding register 22 and R Each is output to the channel address holding register 23.
[0066]
At point C in the HFA in FIG. 5, the address corresponding to the HSG flag area related to the L2 data is set as the read address RAA for the DRAM 6, and then the DRAM 6 is accessed. The HSG flag of the L2 data is read from the DRAM 6 as read data RAD and input to the HSG flag register 24. At this time, HFG is output from the HSG flag register 24, but it is 0 in binary logic (that is, corresponding to the correct answer) (see HFG in FIG. 5), so the correct answer from the correct latch pulse generation circuit 29 is correct. A latch pulse LCK is generated and output to the clock terminal of the L channel address holding register 22.
[0067]
As a result, the input L2ad is output from the L channel address holding register 22 as LAO. The selection circuit 25 outputs L2ad (LAO) to the selection circuit 26 because SGRQT is 1 in the binary logic. The selection circuit 26 outputs the output CAO (L2ad) of the DRAM address counter 21 to the selection circuit 27 because HFG is 0 of binary logic. The selection circuit 27 outputs the CAO (L2ad) output from the selection circuit 26 as the read address RAA of the DRAM 6 because the HFA is 1 of binary logic. Therefore, the read data RAD from the DRAM 6 is L2 data. Further, since HFA is 1 of binary logic, data ATDT sent to the voice decompression unit is L2 data which is read data RAD.
[0068]
Then, in synchronization with the fall of SGRQT from 1 to 0 of the binary logic, the address corresponding to the R2 data (hereinafter referred to as R2ad) from the DRAM address counter 21 is called CAO as the L channel address holding register 22 and Each is output to the R channel address holding register 23.
[0069]
At point D in the HFA in FIG. 5, the address corresponding to the HSG flag area related to the R2 data is set as the read address RAA for the DRAM 6, and then the DRAM 6 is accessed. The HSG flag of the R2 data is read from the DRAM 6 as read data RAD and input to the HSG flag register 24. At this time, HFG is output from the HSG flag register 24, but it is 0 in binary logic (that is, corresponding to the correct answer) (see HFG in FIG. 5), so the correct answer from the correct latch pulse generation circuit 29 is correct. A latch pulse RCK is generated and output to the clock terminal of the R channel address holding register 23.
[0070]
As a result, the input R2ad is output from the R channel address holding register 23 as RAO. The selection circuit 25 outputs R2ad (RAO) to the selection circuit 26 because SGRQT is 0 in binary logic. The selection circuit 26 outputs the output CAO (R2ad) of the DRAM address counter 21 to the selection circuit 27 because HFG is 0 of binary logic. The selection circuit 27 outputs CAO (R2ad) as the output of the selection circuit 26 as the read address RAA of the DRAM 6 because the HFA is 1 of binary logic. Therefore, the read data RAD from the DRAM 6 becomes R2 data. Further, since HFA is 1 of binary logic, data ATDT sent to the voice decompression unit is R2 data which is read data RAD.
[0071]
Next, in synchronization with the fall of SGRQT from 0 to 1 of the binary logic, the address corresponding to the L3 data (hereinafter referred to as L3ad) from the DRAM address counter 21 is set as CAO as the L channel address holding register 22 and Each is output to the R channel address holding register 23.
[0072]
At point E in the HFA in FIG. 5, the address corresponding to the HSG flag area related to the L3 data is set as the read address RAA for the DRAM 6 as the read address RAA for the DRAM 6, and then the DRAM 6 is accessed. The HSG flag of L3 data is read from the DRAM 6 as read data RAD and input to the HSG flag register 24. At this time, HFG is output from the HSG flag register 24, but it is 1 in binary logic (that is, corresponding to the case of incorrect answer) (see HFG in FIG. 5). The correct latch pulse LCK is not generated.
[0073]
Therefore, L2ad is output from the L channel address holding register 23 as the address LAO. The selection circuit 25 outputs L2ad (LAO) to the selection circuit 26 because SGRQT is 1 in the binary logic. The selection circuit 26 outputs L2ad (LAO) to the selection circuit 27 because HFG is 1 of binary logic. The selection circuit 27 outputs LAO (L2ad) as the output of the selection circuit 26 as the read address RAA of the DRAM 6 because the HFA is 1 of binary logic. Therefore, the read data RAD from the DRAM 6 becomes L2 data written in L2ad. Further, since HFA is 1 of binary logic, the data ATDT sent to the voice decompression unit is L2 data which is read data RAD, not L3 data corresponding to CAO which is the output of the DRAM address counter 21, L2 data (preceding correct half sound group data).
[0074]
Then, in synchronization with the fall of SGRQT from 1 to 0 of the binary logic, the address corresponding to the R3 data (hereinafter referred to as R3ad) from the DRAM address counter 21 is referred to as CAO as the L channel address holding register 22 and Each is output to the R channel address holding register 23.
[0075]
At point F in the HFA in FIG. 5, the address corresponding to the HSG flag area related to the R3 data is set as the read address RAA for the DRAM 6, and then the DRAM 6 is accessed. The HSG flag of the R3 data is read from the DRAM 6 as read data RAD and input to the HSG flag register 24. At this time, HFG is output from the HSG flag register 24, but it is 0 in binary logic (that is, corresponding to the correct answer) (see HFG in FIG. 5), so the correct answer from the correct latch pulse generation circuit 29 is correct. A latch pulse RCK is generated and output to the clock terminal of the R channel address holding register 23.
[0076]
As a result, the inputted R3ad is outputted from the R channel address holding register 23 as RAO. The selection circuit 25 outputs R3ad (RAO) to the selection circuit 26 because SGRQT is 0 in binary logic. The selection circuit 26 outputs the output CAO (R3ad) of the DRAM address counter 21 to the selection circuit 27 because HFG is 0 of binary logic. The selection circuit 27 outputs CAO (R3ad) as the output of the selection circuit 26 as the read address RAA of the DRAM 6 because the HFA is 1 of binary logic. Therefore, the read data RAD from the DRAM 6 becomes R3 data. Since HFA is 1 of binary logic, the data ATDT sent to the voice decompression unit is R3 data which is read data RAD.
[0077]
As described above, when compared with the conventional case where a work RAM area for one sound group data and a byte flag (at least 3816 bits (= 424 × 9)) is required on the audio decompression side, the signal processing circuit As a whole, the cost can be greatly reduced by adding the address register on the side and its control circuit, and using the unused area of the DRAM 6 which has not been used conventionally.
[0078]
As described above, when the HFG from the HSG flag register 24 is 1 in binary logic (that is, corresponding to an incorrect answer), the correct latch pulse is not generated from the correct latch pulse generation circuit 29, and the voice decompression unit As an example of the data ATDT to be sent to the above, an example in which the previous correct read data RAD is output has been described, but the present invention is not limited to this. For example, in FIG. 4, by selecting the selection circuit 26 and the selection circuit 27 as appropriate by the system microcomputer 15, the read address RAA of the DRAM 6 is set to the same CAO as before, and immediately before the transfer of the half sound group data to the audio decompression unit. Set the start address.
[0079]
That is, the system microcomputer 15 reads the HSG flag area of the DRAM map of FIG. 3, and if the HSG flag that is currently being transferred is incorrect, as described above, the previous correct half sound group data is transferred to the voice decompression unit. In addition to this, it is possible to transfer arbitrary data, for example, half sound group data to be transferred next, and to switch the error processing method according to the audibility of the sound signal outside the uncorrectable signal. .
[0080]
In this case, the L channel address holding register 22 (or the R channel address holding register 23) has a first address corresponding to the half sound group data immediately before no error among the half sound group data read from the DRAM 6, and a desired address. And a second address corresponding to the next half-sound group data (for example, the half-sound group data to be transferred next, as described above), and the first address or The half sound group data in the buffer memory stored at the second address can be read from the DRAM 6 and decompressed instead.
[0081]
As a result, when it is determined that the half sound group data to be decompressed cannot be restored during the decompression process, the decompression process is performed based on the listener's audibility. Becomes larger, and the listener's audibility can be reflected.
[0082]
As described above, the register means is provided not in the decompression processing system but in the signal processing system. Among the half sound group data read from the buffer memory, the correct half sound group data immediately before there is no error. And a second address corresponding to predetermined half sound group data are recorded in the register means. Therefore, as in the prior art, it is not necessary to always hold the previous correct half sound group data itself or the predetermined half sound group data itself in the work RAM of the decompression processing system. It is not necessary to provide a region in the voice decompression system, and the cost of the entire apparatus can be reduced.
[0083]
In addition, when it is determined that the half sound group data to be decompressed cannot be restored during the decompression process, the decompression process is performed based on the listener's audibility. This increases the effect of reflecting the listener's audibility.
[0084]
As described above, the digital playback device according to the present invention is a digital playback device such as an MD device that decompresses compressed data, and the data input to the earthquake-resistant memory that absorbs disturbance can be corrected by the decompression processing in the next stage. Flag creating means for creating a half sound group flag (HSG flag) indicating whether or not, flag storage means for holding the HSG flag in the earthquake resistant memory corresponding to the data in the same manner as the byte flag after C2 correction, and earthquake resistant Data and byte flags are read from the memory at regular intervals, the corresponding HSG flag is read before being transferred to the decompression processing unit, and if it is correct, the storage means for holding the data address and the data address by the HSG flag Selection means for switching whether to use the current address or the address storage means output as described above, Previous correctable half sound group data and the byte flags are characterized by forwarding to the voice decompression section.
[0085]
The flag creating means creates the HSG flag in real time with the corresponding data before storing it in the seismic memory. The HSG flag is a byte flag indicating whether the corresponding data in the half sound group data matches. Preferably, it is created based on the determination of whether the answer is correct.
[0086]
The addressing for writing to and reading from the flag storage means is preferably performed by the decoding means from the corresponding data address.
[0087]
The storage means preferably holds only the address of the L channel and the R channel independently, not the data itself.
[0088]
It is preferable that the selection means can separately read out the HSG flag area by a system microcomputer and transfer an arbitrary data area to the voice decompression unit according to the value.
[0089]
According to the above invention, the first error processing is not performed by the voice decompression unit as in the prior art, but is performed on the signal processing circuit side using the fact that there is an empty area in the earthquake-resistant memory (DRAM 6). Is called. In other words, not only the data and byte flags are written to the seismic memory, but also the signal processing circuit detects in advance the HSG flag indicating whether or not the current half sound group data can be restored. If the current HSG flag is an error, only the closest correct seismic memory address is stored in the register. If the current HSG flag is an error, the register is accessed, and the data whose HSG flag is always correct is sent to the next audio decompression unit. Detailed error handling is performed. As a result, the number of registers and the like on the signal processing circuit side increases, but the work RAM for storing correct data on the voice decompression unit side is not necessary, and as a whole, a significant cost reduction can be realized.
[0090]
【The invention's effect】
As described above, in the digital playback device of the present invention, the signal processing system is configured to determine whether the half sound group data can be restored during the decompression process, the half sound group data, and the determination means. Stores judgment results And function as an earthquake-resistant memory And a register means for recording only the address corresponding to the previous half sound group data without error among the half sound group data read from the buffer memory, and the determination result is stored in the buffer memory. When the determination result indicates that the half sound group data to be read and decompressed cannot be restored during the decompression process, the half sound group data stored at the address recorded in the register means is The data is read from the buffer memory and transferred to the decompression processing system instead.
[0091]
Therefore, the immediately preceding half sound group data without error is not recorded, but only the address corresponding to the half sound group data is recorded in the register means. Therefore, when each half sound group data is transferred from the signal processing system to the decompression processing system, the determination result is read from the buffer memory. When the read result indicates that the half sound group data to be decompressed cannot be restored during the decompression process, the address recorded in the register means is accessed to the buffer memory, and the The half sound group data stored in the address is read from the buffer memory and transferred to the decompression processing system instead. As a result, it is possible to always transfer error-free half sound group data to the decompression processing system.
[0092]
As described above, the register means is provided not in the decompression processing system but in the signal processing system. Among the half sound group data read from the buffer memory, the correct half sound group data immediately before there is no error. Only the address corresponding to is recorded in the register means. Therefore, unlike the prior art, it is not necessary to always hold the previous correct half-sound group data itself in the work RAM of the decompression processing system. Therefore, a work RAM area for one sound group data can be provided in the speech decompression system. This eliminates the need for the device, and the overall cost can be greatly reduced.
[0093]
Book The digital playback device of the invention is as described above. The present invention In the digital playback apparatus according to the above, the judging means creates a 1-bit flag based on whether or not the corresponding data in the half sound group data match each other and the presence or absence of an error in the byte flag. Based on this, it is determined whether or not the half sound group data can be restored during the decompression process.
[0094]
therefore, the above In addition to the above effect, whether or not half sound group data consisting of a large number of bits can be restored during the decompression process can be determined based on only a 1-bit flag, so that the determination can be simplified. In addition, since the determination criterion is a 1-bit flag, there is an effect that the buffer memory is not burdened in terms of capacity when storing it.
[0095]
As described above, in the digital playback device of the present invention, the signal processing system is configured to determine whether the half sound group data can be restored during the decompression process, the half sound group data, and the determination means. Stores judgment results And function as an earthquake-resistant memory A buffer memory, a first address corresponding to the half sound group data immediately before no error among the half sound group data read from the buffer memory, In a position other than the previous half sound group data with no error Register means for recording a second address corresponding to the half sound group data, reading the judgment result from the buffer memory, and restoring the half sound group data to be decompressed by the judgment result during the decompression process When it is impossible, half sound group data stored in the first address or second address recorded in the register means is read from the buffer memory and transferred to the decompression processing system instead. It is.
[0096]
Therefore, the half sound group data immediately before an error and the predetermined half sound group data itself are not recorded, but only their corresponding addresses are recorded in the register means.
[0097]
Therefore, if the read determination result indicates that the half sound group data to be decompressed cannot be restored during the decompression process, the first or second recorded in the register means with respect to the buffer memory. Two addresses are accessed, and the half sound group data stored at the address is read from the buffer memory, and is transferred to the decompression processing system instead. As a result, half sound group data without error or predetermined half sound group data can always be transferred to the decompression processing system.
[0098]
As described above, the register means is provided not in the decompression processing system but in the signal processing system. Among the half sound group data read from the buffer memory, the correct half sound group data immediately before there is no error. And a second address corresponding to predetermined half sound group data are recorded in the register means. Therefore, as in the prior art, it is not necessary to always hold the previous correct half sound group data itself or the predetermined half sound group data itself in the work RAM of the decompression processing system. It becomes unnecessary to provide the area in the voice decompression system, and the cost of the entire apparatus can be greatly reduced.
[0099]
In addition, when it is determined that the half sound group data to be decompressed cannot be repaired during the decompression process, the decompression process is performed based on the listener's audibility, and thus the degree of participation in the listener's playback process. This increases the effect of reflecting the listener's audibility.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of an MD apparatus which is an example of a digital playback apparatus according to the present invention.
FIG. 2 is an explanatory diagram showing a format example of sound group data input to the error determination circuit of FIG. 1;
FIG. 3 is an explanatory diagram showing a map of the DRAM of FIG. 1;
FIG. 4 is a block diagram showing a configuration example of reading half sound group data from the DRAM and sending it to a sound decompression unit in a sound decompression circuit.
FIG. 5 is a timing chart of FIG. 5 corresponding to FIG. 4;
[Explanation of symbols]
4 signal processing circuit
5 Error judgment circuit
7 Error processing circuit
8 Voice expansion circuit
15 System microcomputer
21 DRAM address counter
22 L channel address holding register
23 R channel address holding register
24 HSG flag register
25 Selection circuit
26 selection circuit
27 Selection circuit
29 Correct Latch Pulse Generation Circuit

Claims (3)

Half sound group data is transferred from a signal processing system in which error correction processing based on an error correction code is performed to a decompression processing system in which error processing and decompression processing is performed based on information in the half sound group data and reproduced. A digital playback device,
The signal processing system is
A determination means for determining whether or not the half sound group data can be restored during the decompression process;
A buffer memory that stores the half sound group data and the determination result of the determination means, and functions as an earthquake-resistant memory ;
Register means for recording only the address corresponding to the previous half sound group data without error among the half sound group data read from the buffer memory;
When the determination result is read from the buffer memory and the determination result indicates that the half sound group data to be decompressed cannot be restored during the decompression process, it is stored at the address recorded in the register means. A half reproduction group data is read from the buffer memory and transferred to the decompression processing system instead. The determination means creates a 1-bit flag based on whether or not corresponding data in the half sound group data match and the presence or absence of an error of a byte flag, and based on the flag, the half sound group 2. The digital reproduction apparatus according to claim 1, wherein it is determined whether or not the data can be restored in the decompression process. Half sound group data is transferred from a signal processing system in which error correction processing based on an error correction code is performed to a decompression processing system in which error processing and decompression processing is performed based on information in the half sound group data and reproduced. A digital playback device,
The signal processing system is
A determination means for determining whether or not the half sound group data can be restored during the decompression process;
A buffer memory that stores the half sound group data and the determination result of the determination means, and functions as an earthquake-resistant memory ;
A first sound address corresponding to the previous half sound group data without error in the half sound group data read from the buffer memory, and a half sound group at a predetermined position other than the previous half sound group data without error Register means for recording a second address corresponding to the data;
When the determination result is read from the buffer memory and the determination result indicates that the half sound group data to be decompressed cannot be restored during the decompression process, the first address recorded in the register means or A digital reproduction apparatus characterized in that half sound group data stored at a second address is read from the buffer memory and transferred to the decompression processing system instead.

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