JPH06275032A - Digital data reproducing device - Google Patents

Abstract

PURPOSE:To interpolate an address destination signal when this signal is wrong in the case of reproducing a digital information signal. CONSTITUTION:This device is provided with an error detecting means 55, evaluation means 58 and 60, 61, address interpolating circuit 62, and extracting means 59 or 57 for extracting an absolute destination signal contained in a disk or a sub address destination signal in additional information added to the digital information signal reproduced from the disk. When the error detecting means 55 decides the address destination signal in the digital information signal is wrong, the absolute destination signal or sub address destination signal extracted by the extracting means 59 or 57 is evaluated by the evaluating means 58, 60 and 61 and corresponding to the evaluated result, the address destination signal is interpolated by the address interpolating means 62. Thus, the digital information signal is prevented from being omitted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disc reproducing apparatus for reproducing an information signal such as a digital audio signal from a disc recording medium.

[0002]

2. Description of the Related Art In recent years, a magneto-optical type optical disc has been developed which can record data many times. Among them, the mini disk (hereinafter referred to as "MD") system is as compact as the conventional Walkman (trademark) type cassette recorder,
It is possible to reduce the weight, and its spread in the future is drawing attention. The MD is for recording and reproducing an audio signal in which data is compressed on a disk by a magneto-optical method, and a guide groove for tracking control is formed on the disk, and the guide groove is continuous over the entire circumference of the disk. Address information is recorded in advance. Therefore, it is possible to search regardless of the presence or absence of the recording signal.

FIG. 3 is a block circuit diagram of the MD system. In the figure, 1 is a 2-channel audio input terminal, 2 is an analog / digital conversion circuit (A / D), 3
Is a data compression circuit, 4 is a data processing circuit, 5 is an error correction coding encoder, 6 is a modulation circuit, 7 is a magnetic head drive circuit, 8 is a magnetic recording head, 9 is a disk, 10 is an optical pickup, and 11 is a reproduction. An amplifier, 12 is a demodulation circuit,
13 is a decoder for error correction, 14 is a microcomputer, 15 is a data expansion circuit, 16 is a digital / analog conversion circuit (D / A), 17 is a 2-channel audio output terminal, 18 is an address decoder, 19 is a motor, 20 Is a servo control circuit.

FIG. 4 is a timing chart of signal processing during recording and reproduction. The operation will be described with reference to FIGS. 3 and 4. The analog audio signal supplied to the audio input terminal 1 is sampled by the A / D conversion circuit 2 and converted into a digital signal. This digital signal is subjected to voice compression coding processing in the data compression circuit 3,
It is reduced to about 1/5 of the original signal information amount.

The compressed digital signal is temporarily stored in the data processing circuit 4 and is intermittently read out at the same signal rate as before compression, as shown in FIG. The encoder 5 performs interleave processing for distributing data and rearranging signals, and added value of error correction code. Further, in the next modulation circuit 6, 1 byte (= 8 bit) data is converted into 14-bit data. EFM modulation is performed. This signal is magneto-optically recorded on the disk 9 by the magnetic recording head 8 via the magnetic head drive circuit 7. The recording operation is performed in response to the modulation signal supplied intermittently, and the recording state and the recording pause state are alternately repeated as shown in FIG. 4D, and the end of the recorded portion before the recording is performed. Search for the address of and record continuously.

At the time of reproduction, the signal written on the disk 9 is read by the reflected light of the light emitted from the optical pickup 10 to the disk 9. The optical information is converted into an electric signal by the optical pickup 10 and supplied to the reproduction amplifier 11. The signal amplified by the reproduction amplifier 11 is given to the demodulation circuit 12 and converted into the original 1-byte data.

On the other hand, the output of the reproducing amplifier 11 is also supplied to the address decoder 18. This address decoder 18
Aims to take out the information contained in the light spot guide groove previously engraved on the disc 9, and reproduces the continuous address signal of the entire circumference of the disc and detects the wobbling of the guide groove to obtain the tracking information. It has gained.

This tracking information is sent to the servo control circuit 2
0, a tracking servo is applied so that the optical pickup 10 scans a predetermined guide groove, and a servo that keeps the rotation of the disk 9 at a constant linear velocity is applied so that the waviness of the guide groove has a constant cycle. Motor 19
To control.

The signal reading from the disk 9 is performed intermittently like the writing at the time of recording, and as shown in FIG. 4 (e), the reproducing operation and the reproducing pause state are alternately repeated. The signal demodulated by the demodulation circuit 12 is subjected to error detection and correction processing by the decoder 13 and deinterleave processing for restoring the order of the signals is performed, and then the data processing circuit 4
The signal written in the data processing circuit 4 and read from the data processing circuit 4 is applied to the data decompression circuit 15. Normally, the input of the data processing circuit 4 is controlled so that the signal is retained by a predetermined amount or more. That is, as shown in FIG. 4 (h), when the amount of data in the reproduction area of the data processing circuit 4 becomes full, the input is stopped and the reproduction is suspended,
When the remaining data amount of the data processing circuit 4 falls below the point indicated by a, the subsequent portion of the signal already read on the disk 9 is searched and reproduced, and data is supplied to the data processing circuit 4.

Therefore, even if the optical pickup 10 jumps due to disturbance, for example, the data processing circuit 4
Since at least the data amount a is held in, the signal is read out, and by searching the portion immediately before jumping during that, continuous reproduction without sound break can be performed. The audio signal restored to the amount of information before compression by the data expansion circuit 15 is converted into an analog signal by the D / A conversion circuit 16 and then output from the audio output terminal 17. The microcomputer 14 controls the motor 19 using the address signal engraved in the disc guide groove from the address decoder 18 and the address signal recorded corresponding to the audio signal, and at the same time, the series of operations described above. Control.

By the way, regarding the data format of MD, JAS Journal vol 33 No1
(1993) or as disclosed in Radio Technology Vol. 47, No. 3, it has a structure similar to CD-ROM mode 2 and is recorded for each data unit called a cluster.
The cluster is subdivided into 36 sectors. In addition, 32 sectors of one cluster are used for audio data. Further, each sector has a hierarchical structure of a cluster sector at a portion called a sector header and a data address on the disk is added.

The above address is decoded by the data processing circuit 4 and used as an address when data is stored or read in the data processing circuit 4. Further, the above address is recorded in an additional information area called a subcode Q in the reproduction-only MD, and the recording / reproduction M is used.
In D, ADIP (Address In Pregroo
It is also recorded in a guide groove called ve) and is used as data for controlling the rotation of the disc.

By the way, regarding the processing of the sector data, JAS Journal Vol 33, No.
1 (1993), one sector is 23
It is composed of 52 bytes (of which 2332 bytes are audio data), and is divided into data units called 11 sound groups in 2 sectors (1 sound group is 424 bytes), and a data expansion circuit 15 is provided for each sound group.
The decompression process and the data compression circuit 3 compression process are performed.

[0014]

Since the conventional MD system is constructed as described above, a measure is taken so that the sound is not interrupted even when the needle jumps due to an impact during reproduction. Suitable for portable systems and in-vehicle systems. However, the address information is 1 sector 235.
It is added every 2 bytes, and blocks such as DAT (3
Compared to the address information added every 6 bytes), it is given to a larger number of data groups. Therefore, if the address information is erroneous, the reliability of the data for one sector is reduced.

For this reason, sound skips, sound breaks, etc. occur for about 11.6 msec (for one sector), so that the address information is erroneous, or the data in the sector is 1
Even if one is wrong, the optical pickup 10
Is reproduced by reproducing the same sector by moving the same to obtain correct address information or data to prevent skipping. However, in the above method, there is at least one uncorrectable error in the sector due to a defect such as a scratch on the disk, the reproducing operation is repeated many times, and not only the desired correct data is not obtained in the end,
During that time, all the data in the data processing circuit 4 is read out. Therefore, if the erroneous sector is unavoidably skipped and the next sector is reproduced, the sound skip for one sector occurs during this period.

In the conventional system, in the above case, an error flag or the like is added to all the data of the sector that could not be reproduced, and the data decompression circuit 15 interpolates the preceding and following sector data. Due to the large number, the sound quality is significantly degraded.

Therefore, if the address information does not have a flag indicating uncorrectable at a certain position, it is used as a valid sector, and only the data with the uncorrectable flag is interpolated from other data and used. A method for reducing the number of interpolated data has also been proposed.

However, even in this case, if the address information is incorrect, there is a problem that all the data in the sector is interpolated as described above.

The present invention has been made for the purpose of solving the above-mentioned problems, and it is possible to reduce the number of data to be interpolated when data is erroneous by interpolating or protecting the address information in the sector. It is an object of the present invention to obtain a device that improves the reliability of the address information.

[0020]

In a digital data reproducing apparatus according to the present invention, a track guide groove on a disk is formed in a wobbling shape, and an absolute address of the disk is recorded in the wobbling signal together with a plurality of digital information. Recording medium or additional information added to a plurality of digital information, and the same location of the recording medium in which a sub-address address signal corresponding to the address address of the digital information is recorded in the additional information, a plurality of times. A reproducible device, an error detecting means for detecting an error of digital information including an address address signal in the digital information, an evaluating means for evaluating continuity of the absolute address or the sub address address signal, and the evaluation. The address determined as an error by the error detection means based on the evaluation result of the means Is obtained and an address interpolation means for interpolating the earth signal.

Further, when the same portion is reproduced a plurality of times, first and second storage means for storing an interpolation signal indicating that the address has been interpolated and the detection result of the error detecting means, and the digital information are stored. Third storage means for
A control means for determining whether to rewrite the contents of the third storage means from the interpolation signal, the error detection result, and the contents of the first and second storage means is provided.

[0022]

The digital data reproducing apparatus according to the present invention is
When the error detecting means determines that the address address signal is in error, the address interpolating means interpolates the address address signal when the evaluating means continues the absolute address or sub-address address signal.

Further, when the same portion is reproduced a plurality of times, the control means determines the third value according to the interpolation signal output by the address interpolation means, the error detection result of the error detection means, and the contents of the first and second storage means. The entire system is controlled so that the contents of the storage means can be rewritten.

[0024]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a block circuit diagram showing the inside of a data processing circuit 4 that performs processing of detecting address information in each sector header and performing interpolation or protection.

In the figure, 21 is an input / output terminal to the encoder 5 and the decoder 13, 22 is an encode / decode data interface, 23 is a sector sync detection circuit,
24 is a descrambler, 25 is a reproduction header register,
26 is a decode flag register, 27 is a sector sync generation circuit, 28 is a scrambler, 29 is a data selector A, 30 is a microcomputer interface, 31 is a write data buffer, 32 is a read data buffer, 33 is a data selector B, and 34 is a RAM. Interface, 35 is R
AM, 36 is an address generator, 37 is a recording header register, 38 is a companding data interface, 39 is an input / output terminal for the data compressing circuit 3 and the data expanding circuit 15, 40 is a data input terminal from the microcomputer 14, and 41 Is a data output terminal to the microcomputer 14, and 42 is a terminal for inputting a data output request signal from the data expansion circuit 15.

First, the operation of the data processing circuit 4 during reproduction will be described with reference to FIG. RAM35 first
When the reset operation of is completed, the data subjected to the error detection and correction processing by the decoder 13 is input from the input / output terminal 21 together with the error detection result and encoded / encoded.
It is input to the decode data interface 22. Of the input data, the error detection result is input to the decode flag register 26, the corrected data is input to the descrambler 24, and the order of the data is changed. Of these, the sync signal in the sector header of each sector is detected by the sector sync detection circuit 23, and the address information in the sector header is extracted by the signal generated based on the detection timing for reproduction. It is input to the header register 25.

Next, the data output from the descrambler 24 is temporarily stored in the write data buffer 31 via the data selector A29. The error detection result of the data input to the write data buffer 31 is output from the decode flag register 26 and input to the RAM interface 34 via the microcomputer interface 30. Further, the address information is output from the reproduction header register 25 and input to the RAM interface 34 via the microcomputer interface 30.

Here, the RAM interface 34 outputs a detection signal from the output terminal 41 to the microcomputer 14 via the microcomputer interface 30 to indicate that the data capacity of the RAM 35 is below a certain value.
Then, the microcomputer 1 is input through the input terminal 40.
Data 4 designating the first data address written in the RAM 35 is input to the microcomputer interface 30. This designated data is compared with the address information output from the reproduction header register 25, and if they match, the result is instructed to the RAM interface 34, and at the same time,
The data selector B33 is switched to the write data buffer 31 side.

In the above case, the RAM interface 34 sends the input address information to the address generator 36, generates an address for accessing the RAM 35, and outputs a signal for putting the RAM 35 in the write mode. Also, the data output of the write data buffer 31 is enabled. Therefore, the data of the addresses designated by the microcomputer 14 are sequentially written in the RAM 35.

Next, the RAM interface 34 checks the input address information, and when it detects that the write address of the RAM 35 has reached a predetermined value and the empty area is full, it outputs the output of the write data buffer 31. At the same time, the writing of data to the RAM 35 is stopped. The address information at the end of writing is output to the output terminal 4 via the microcomputer interface 30.
1 is output to the microcomputer 14. The first data write operation is completed as described above.

Next, the data read operation from the RAM 35 will be described. Data expansion circuit 1 via input terminal 42
When the data output request signal from 5 is input to the companding data interface 38, the output of the read data buffer 32 is connected to the companding data interface 38 via the data selector A29, and the data bus of the RAM 35 is connected to the data selector. Read data buffer 3 via B33
The RAM interface 34 is instructed to connect to the RAM 2.

From the input terminal 40, a read start address is designated by the microcomputer 15 to the microcomputer interface 30, and address information is sent to the RAM interface 34. At this time, the RAM interface 34 is configured to perform data writing and reading in a time-division manner. The read data buffer 32 is disabled during the data writing operation, and the read data buffer 32 is read during the data writing operation. , The read data buffer 32 is enabled. In the RAM interface 34, the data bus of the RAM 35 is connected to the read data buffer 32 in the read state, and the data selector B33 and the data selector A2 are connected so that the read data buffer output is connected to the companding data interface.
9 and control.

In the read state, the RAM interface 34 outputs the address information input from the microcomputer 14 to the address generator 36 to access the RAM 35. Therefore, predetermined data is read from the RAM 35 through the data selector B33, the read data buffer 32, and the data selector A29 to the data decompression circuit 15 from the input / output terminal 39 via the companding data interface 38. However, the read operation is continued while the data output request signal is input to the companding data interface 38 from the input terminal 42.
When the input is stopped, the companding data interface 38 instructs the RAM interface 34 to stop the read operation.

When the read operation is stopped, the RAM interface 34 informs the microcomputer 14 from the output terminal 41 via the microcomputer interface 30 that the read operation has been stopped. As a result, the microcomputer 14 sets the next read address information from the input terminal 40 again in the microcomputer interface. Thereafter, when the next data output request signal is input from the input terminal 42, the reading is restarted again.

As described above, the data reading is repeated intermittently, but when the data capacity in the RAM 35 becomes a certain value or less, the RAM interface 34 outputs a detection signal to the microcomputer 14, so that the above procedure is performed. Then, the write operation is restarted.

The above write operation is repeated at predetermined intervals according to the data capacity in the RAM 35. When an error detection signal is input from the decode flag register 26 to the RAM interface 34 via the microcomputer interface 30, The address information is interpolated as described above.

FIG. 2 shows the RAM interface 3 of the first embodiment.
4 is a block circuit diagram showing FIG. In the figure, 50,5
1, 52 and 53 are input terminals, 54 is a reproduction address latch, 55 is a decode flag latch, 56 is a microcomputer data latch, 57 is a subcode address latch, 58 is an address check circuit A, 59 is an ADIP address latch, and 60 is an address. The check circuits B and 61 are selectors,
62 is an address interpolation circuit, 63 is a control circuit, and 64 is RA
M read / write circuit, 65 is a clock control circuit, 66
Is a buffer selector control circuit, 67 is an address latch,
68, 69, 70 and 71 are output terminals, 72 is an input / output terminal, 73 is an input terminal, and 74 and 75 are output terminals.

Next, the operation will be described. First, a signal for initializing the RAM 35 is input from the input terminal 53 to the control circuit 63 from the microcomputer 14 via the microcomputer interface 30. The control circuit 63 uses the address latch 67 to initialize the output terminal 74 of the RAM 3
The address corresponding to the area 5 is output and RA
Data is output from the input / output terminal 72 via the M read / write circuit 64 to initialize the RAM 35. Next, after the initialization is completed, the control circuit 63 outputs a signal indicating that the data capacity of the RAM 35 has become equal to or less than a predetermined value to the microcomputer 14 through the output terminal 75 and the microcomputer interface 30.

The data output from the microcomputer 14 by the above operation is input to the control circuit 63 from the input terminal 53 and is in a data write state. At this time, a selection signal is output from the control circuit 63 to the selector 61 so that the address check circuit A is selected in the case of the reproduction-only disc and the address check circuit B is selected in the case of the recording / reproduction disc. It

Next, while the descrambler 24 rearranges the order of the sector data, the input terminal 5
The sector address in the sector header is input to 0 via the microcomputer interface 30 and stored in the reproduction address latch 54. The error detection result of the sector address is input to the input terminal 51 via the microcomputer interface 30, and the decode flag latch 55 is input.
Stored in. Thereafter, every time the sector address is input from the microcomputer interface 30, the contents of the reproduction address latch 54 and the decode flag latch 55 are updated.

During the above operation, the microcomputer interface 30
As described above, when the sector address and the address of the write start sector input from the microcomputer 14 match, the result is input to the control circuit 63 from the input terminal 53 and data writing is started.

First, in the address interpolation circuit, the error detection result of the decode flag latch 55 is input to check whether there is an error. When there is no error, the reproduction address latch 5
The contents of 4 are output to the control circuit 63. If there is an error, the check result of the address input from the selector 61 is input, and if it is correct, the sector address (1
The previous sector address) is added with +1 or a predetermined value to create an interpolation address, which is output to the control circuit 63.

In the above operation, from the input terminal 52 to the microcomputer interface 30 to the microcomputer 14
The address information read by the microcomputer data latch 56
Entered in. For a read-only disc, the subcode address latch 59 stores the sector address included in the subcode Q, and for a read / write disc, the ADIP address latch 57 stores the sector address included in ADIP. At this time, the fact that the addresses of the subcode address latch 59 or the ADIP address latch 57 are continuous indicates that the address check circuit A58 and the address check circuit B6, respectively.
It is checked with 0 and output to the selector 61. The selector 61 outputs the contents of the address check circuit A58 or B60 as described above.

By the above operation, the address information is generated by the sector address input to the control circuit 63,
After being temporarily stored in the address latch 67, the output terminal 74
And is input to the address generator 36.
The error detection result of the sector data is input from the decode flag register 26 to the control circuit 63 via the microcomputer interface 30 and the input terminal 53. The control circuit 63 outputs the error detection result to the RAM read / write circuit 64, and outputs it from the input / output terminal 72 to the RAM 35 at the write timing of the RAM 35 according to the control clock output from the clock control circuit 65. At this time, a control signal for causing the RAM 35 to perform a write operation is output from the output terminal 71. Further, the address information for writing the error detection result is the control circuit 6
3 is output from the output terminal 74 via the address latch 67.

Further, as described above, when writing the data in the sector, the RAM read / write circuit 6 according to the control clock output from the clock control circuit 65.
4 outputs a write signal to the buffer selector control circuit 66. Then, the buffer / selector control circuit 66 outputs a selection signal from the output terminal 68 to the data selector A 29, which causes the data selector A 29 to connect the output of the descrambler 24 to the write data buffer 31, and writes the data selector B 33. Buffer 31 is RA
Output terminal 69 for selecting signal to be connected to M35
Output to the data selector B33. A signal for enabling the write buffer 31 is output from the control circuit 63 via the buffer / selector control circuit 66 to the output terminal 7.
It is output from 0.

The above sector data write operation is continued until the final address of the address input from the microcomputer 14 by the control circuit 63 and the sector address input by the address interpolation circuit 62 match or reach a predetermined value. To be Then, when they match or reach a predetermined value, the control circuit 63 sends a signal to the RAM read / write circuit 64 and the buffer selector control circuit 66 to stop the write operation.

In addition to the above operation, the following operation is performed when reading data from the RAM 35. First, after a certain period of time during the write operation, the read start address is input from the microcomputer 14 to the control circuit 63. At this time, a read signal is input from the companding data interface 38 to the RAM read / write circuit 64 from the input terminal 73. From the above, at the read timing of the error detection result, the error detection result is input from the RAM 35 to the read data buffer 32 via the data selector B33, and at the next data read timing, RA
The data is input to the read data buffer 32 from M35. Therefore, the RAM read / write circuit 64 is
At the timing of reading the error detection result, the RAM 3
A control signal for reading 5 is sent, and a signal for generating an address is sent to the control circuit 63. In the control circuit 63, within the area in which the error detection result is included, the address information including the error detection result in a portion corresponding to the read start address is generated and output from the address latch 67 to the output terminal 74.

At the data read timing, the control circuit 63 outputs the read start address to the output terminal 74 via the address latch 67 according to the signal input from the RAM read / write circuit 64.

Further, the RAM read / write circuit 64
A read signal is sent to the buffer selector control circuit 66 at the error detection result and the data read timing. Accordingly, the selection signal from the output terminal 68 causes the read data buffer 32 to pass through the data selector A29.
Is a signal to be connected to the companding data interface 38 via. The selection signal from the output terminal 69 is sent to the RAM
The signal connects the data bus 35 to the read data buffer 32 via the data selector B33. further,
A signal for enabling the read data buffer 32 is output from the output terminal 70.

When the read signal is not input from the input terminal 73 during the above read operation, the RAM read / write circuit 64 stops outputting the read signal to the control circuit 63 and the buffer / selector control circuit 66. Read operation stops. At this time, the control circuit 63 outputs to the output terminal 75 a signal indicating that the read operation has been completed.

The control circuit 63 indicates that the data capacity in the RAM 35 has become a certain value or less by the above reading.
When it detects from the write start and end addresses and the read start and end addresses, the output terminal 75 outputs a detection signal to the microcomputer. Therefore, the write start sector address is input again from the input terminal 53, and the write operation is restarted.

As described above, writing and reading are controlled in the RAM interface 34, and even if the sector address is incorrect, the address interpolation circuit 62 interpolates and writes.

Example 2. In the above-described first embodiment, the method of interpolating when the sector address is incorrect is described.
The same sector can be reproduced more than once until the capacity of M35 becomes less than a certain value. A method for improving the reliability of the sector address when reproducing the same sector a plurality of times will be described below.

In the second embodiment, the first embodiment is used for the address interpolation circuit 62, or when the sector address is incorrect as a result of error detection of the decode flag latch 55, interpolation is performed from the correct sector address before and after. Is configured. However, when the address is interpolated, an interpolation signal is input from the address interpolation circuit 62 to the control circuit 63 together with the sector address.

The operation will be described below with reference to FIGS. 1 and 2. Similar to the first embodiment, when writing data after initializing the RAM 35, address information is generated from the sector address input to the control circuit 63, and the address latch 67 is generated.
Is output to the output terminal 74 via. At this time, the interpolation signal is sent to the RAM read / write circuit 64 at the same time as the sector address, the writing timing of the interpolation signal is generated according to the clock from the clock control circuit 65, and the interpolation signal is input from the input / output terminal 72 accordingly. Is output and RA
Written to M35. The write timing signal is also input to the control circuit 63 to generate address information for the interpolation signal and output from the output terminal 74 via the address latch 67. When the address is interpolated as described above, the interpolation signal is written.

In the above, the interpolation signal is output to the output terminal 7
5 is also output to the microcomputer 14, and the control circuit 63 informs that the sector address is interpolated and data is written in the RAM 35.

When the capacity of the RAM 35 is full, or when a sector in which at least one interpolation signal is output is generated, the microcomputer 14 operates the input terminal 5
A signal for stopping the writing is input to the control circuit 63 through 3. Therefore, the control circuit 63 outputs a signal for stopping the writing to the RAM read / write control circuit 64 and the buffer / selector control circuit 66, and outputs the address information at the time of the stop to the output terminal 75.

Next, the microcomputer 14 gives an instruction to the servo control circuit 20 to move the optical pickup 10, and as a result, the same area on the disc is reproduced again. Next, the microcomputer 14 sends the write start sector address to the input terminal 53. The sector address value at this time is at least a value before the sector where the interpolation signal is output for the first time, and when the microcomputer 14 determines that the error detection result from the decoder 13 has an error of a certain value or more. Outputs the same value as last time.

Therefore, as described above, the writing is repeated at least from the data having the sector address from which the interpolation signal is output for the first time. Here, the data read error detection result and the interpolation signal are read at the RAM read / write circuit 64 before the clock of the clock control circuit 65 before the write timing of the interpolation signal, the write timing of the data, and the write timing of the error detection result. Timing is generated, and the data error detection result and the interpolation signal are read from the RAM 35 in response to the timing, and input from the input / output terminal 72 to the control circuit 63 via the RAM read / write circuit 64. Also, each address is
The timing signal is input to the control circuit 63, address data for the interpolation signal and an address for the error detection result are generated, and output to the output terminal 74 via the address latch 67.

As described above, the control circuit 63 uses the read interpolation signal and error detection result, the error detection result input from the input terminal 53 when writing for the second time, and the interpolation signal input from the address interpolation circuit 62. RAM
A signal for controlling writing is output to the read / write circuit 64 and the buffer / selector control circuit 66.

The judgment contents of the control circuit 63 are as follows. (1) When the interpolation signal of the sector address to be rewritten is read from the RAM 35, and when the interpolation signal is input from the address interpolation circuit 62 to the control circuit, the writing of the sector is stopped and the signal is passed through the output terminal 75. And inform the microcomputer 14 of the cancellation,
Unless there is an instruction from the input terminal 53, writing of the next sector is executed. Also, when the interpolation signal is not input,
The RAM read / write circuit 6 outputs a signal for erasing the interpolation signal.
At the same time as writing to the RAM 35 via 4, a signal for executing data writing is output from the sector address. In this case, the RAM designated by the sector address
The data area in 35 is rewritten with the reproduced data for the second time.

(2) The interpolation signal of the sector address to be rewritten is not read from the RAM 35, and when the error detection result for the sector data is read, the control circuit 63 determines that the data is erroneous when the error detection result is read.
At the time of writing from the write data buffer 31, a signal for executing writing is output. At this time, the data in the sector in which an error has occurred is rewritten, and the error detection result input from the input terminal 53 is also stored in the RAM.
It is output to the RAM 35 via the read / write control circuit 64.

(3) In (2), rewriting is not performed on the error-free data, and the error detection result is not output.

By the control circuit 63 operating as described above, at the time of rewriting, address information is generated based on the sector address having no interpolation signal, and only incorrect data is rewritten, so that the reliability of data is improved. .

Example 3. The operation of the control circuit 63 in the second embodiment is such that the interpolation signal read from the control circuit 63, the error detection result, and the interpolation signal from the address interpolation circuit 62 are output from the output terminal 75, and an error from the decode flag register 26 occurs. The detection results may be sent to the microcomputer 14 via the microcomputer interface 30, and the microcomputer 14 may output a signal to the control circuit 63 as to whether or not to rewrite. In this case, when a rewrite signal is sent from the input terminal 53, the control circuit 63 outputs a signal for executing writing to the RAM read / write circuit 64 and the buffer / selector control circuit 66.

[0066]

As described above, according to the present invention,
An optical digital information reproducing apparatus in which a track guide groove is formed in a wobbling shape on a disc-shaped recording medium, wherein absolute address extracting means for extracting an absolute address signal on the recording medium from the wobbling signal, and a plurality of reproduced plural Error detection is performed based on the address address signal extraction means for extracting the address address signal added to each piece of digital information and the error detection code added to the plurality of digital information including the address address signal. Error detecting means, evaluating means for checking that the absolute address signals extracted by the absolute address extracting means are continuous, and the result of detection by the error detecting means, it is determined that the address address signal is erroneous. If the absolute address signal is continuous as a result of the check by the evaluation means, In place of an erroneous address address signal, an address interpolating means for generating an interpolated address address signal by adding a predetermined value to the address address signal immediately before or after the error is not detected by the error detecting means is provided. Therefore, even if the address address signal is erroneous, the entire digital information to which the erroneous address address signal is added can be used by interpolating the address address signal by the address interpolating means, thus preventing loss of digital information. it can.

Further, when reproducing a recording medium in which a sub address address signal corresponding to the address address signal is recorded in the additional information added to the plurality of digital information, the sub address address signal is extracted. A sub-address address signal extracting means and an evaluating means for checking that the sub-address signal is continuous are provided, and when the address interpolating means is erroneous in the address address signal, the sub-address In the case where the wobbling signal does not exist, the error detecting means is configured to generate the interpolation address address signal by adding a predetermined value to the address address signal immediately before or after the error is not detected. It is possible to prevent the loss of digital information even on a recording medium.

Further, in the above, a discriminating means for discriminating whether the recording medium is a recording medium in which the sub address address signal is recorded in the additional information or a recording medium in which an absolute address signal is recorded in the wobbling signal, and the discriminating means. According to the determination result of, the selector for switching between the absolute address signal and the sub-address address signal, which is the evaluation content of the evaluation means, is provided in the evaluation means, so that the continuity of the absolute address signal or the sub-address address signal is used. The address address signal can be interpolated.

In the apparatus for reproducing the plurality of digital information a plurality of times, the first storage means for storing the interpolation signal indicating that the address address signal is interpolated and the error detection result error of the error detection means are erroneous. Second storage means for storing an error flag for the data determined to be present;
From the third storage means for storing the digital information, the interpolation signal, the error detection result, the content of the first storage means and the content of the second storage means, the same location as the digital information in the storage means is found. When reproduced, the interpolation signal is stored in the first storage means, and when the reproduced address address signal is not interpolated, the third signal is output.
If the interpolation signal is not stored in the first storage means, the data stored in the storage means is controlled so that the data indicated by the address address signal is restored by the reproduced digital information. If the above-mentioned error flag is present in the storage means of the above, and the data in the third storage means corresponding to the error flag is erroneous, the result of error detection of the data at the same location as the reproduced erroneous data is erroneous. When there is no data, the control means for controlling to rewrite the data in the third storage means by the reproduced data is provided. Therefore, the third storage means is reproduced by reproducing the digital information at the same location a plurality of times. There is an effect that the error data in the inside can be reduced and a device with high reliability of digital information can be obtained.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of data processing detection in a first embodiment and a second embodiment of the present invention.

FIG. 2 is a block circuit diagram of a RAM interface in the first, second and third embodiments of the present invention.

FIG. 3 is a block circuit diagram of a digital data reproducing device according to the present invention and a conventional example.

FIG. 4 is a timing diagram illustrating a recording / reproducing operation.

[Explanation of symbols]

 4 Data Processing 13 Decoder 14 Microcomputer 34 RAM Interface 35 RAM 54 Playback Address Latch 55 Decode Flag Latch 56 Microcomputer Data Latch 57 Subcode Address Latch 58 Address Check Circuit A 59 ADIP Address Latch 60 Address Check Circuit B 61 Selector 62 Address Interpolation Circuit 63 Control circuit 64 RAM read / write circuit 65 Clock control circuit 66 Buffer selector control circuit

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Claims (6)

[Claims] 1. A reproducing apparatus for reproducing a plurality of digital information signals such as digital audio signals from a disk-shaped recording medium, the recording medium being obtained from a wobbling signal obtained from a guide groove formed in the recording medium. Extraction means for extracting the absolute address signal of, the evaluation means for evaluating the continuity of the absolute address signal obtained by the extraction means, and the error of the digital information signal including the address address signal reproduced from the recording medium is detected. And an address interpolating means for interpolating the address address signal according to the evaluation result of the evaluating means when the error detecting means determines that the address address signal is erroneous. Characteristic digital data reproducing device. 2. An apparatus for reproducing a plurality of digital information signals such as digital audio signals from a disc-shaped recording medium, wherein the digital information signals include an address address signal, and the digital information signals correspond to the digital information signals. The additional information added by the subaddress address signal corresponding to the address address signal is included in the recording medium for extracting the subaddress address signal from the recorded recording medium, and the subaddress address signal obtained by the extracting means. Means for evaluating the continuity of the address information, an error detecting means for detecting an error in the digital information signal including the address address signal reproduced from the recording medium, and the address detecting means for detecting an error in the address address signal. If judged, the address address signal is interpolated according to the evaluation result of the evaluation means. A digital data reproducing device comprising an address interpolating means. 3. The address interpolating means is provided with a selecting means for selecting an evaluation result of the absolute address signal evaluating means and an evaluation result of the sub-address address signal evaluating means, and is the recording medium on which the absolute address signal is recorded. 2. A discriminating means for discriminating whether or not the sub-address address signal is recorded on the recording medium is provided, and the selecting means is made to select in accordance with the discrimination result of the discriminating means.
Alternatively, the digital data reproducing apparatus according to claim 2. 4. The address interpolating means comprises a generating means for generating an interpolation address by adding a predetermined value to an address address signal immediately before or immediately after the error when interpolating an erroneous address address signal. The digital data reproducing device according to claim 1 or 2. 5. An apparatus for reproducing a digital information signal including a plurality of address address signals such as a digital audio signal from a disc-shaped recording medium a plurality of times, and detecting an error in the digital information signal including the address address signals. Error detecting means, an address interpolating means for interpolating the address address signal determined to be erroneous by the error detecting means, and an interpolation signal indicating that the address address signal is interpolated by the address interpolating means. No. 1 storage means, second storage means for storing an error flag corresponding to the digital information signal determined to be an error by the error detection of the error detection means, and third storage means for storing the digital information signal. From the interpolation signal, the error flag, and the contents of the first and second storage means. A digital data reproducing apparatus comprising: a control unit that rewrites the contents of a storage unit. 6. The control means reproduces the same address address signal by a plurality of reproducing operations when an address address signal in the first storage means has an interpolation signal, and the reproduced address address signal is an error detecting means. When it is determined that there is no error by the first rewriting means, the predetermined rewriting means for rewriting the predetermined address in the third storage means indicated by the regenerated address address signal with the regenerated digital information signal; If there is no interpolation signal in the first storage means, the same location as the digital information signal stored in the third storage means is reproduced by the error detection means in the plurality of reproduction operations, When the reproduced digital information signal is determined by the error detection means to be error-free, the third information corresponding to the contents of the second storage means
6. The digital data reproducing apparatus according to claim 5, further comprising a second rewriting unit that controls to replace the digital information signal in the storage unit with the reproduced digital information signal.