JPS63197122A - Error correcting and checking device - Google Patents

Abstract

PURPOSE:To reduce the data processing time by devising the device such that error correction and error check are finished at the same time to data of matrix arrangement so as to reduce the number of times of data reading from a buffer memory. CONSTITUTION:The titled device consists of a RAM 1 as a memory storing data of the state including an error check parity generated as to one block data, a read means reading the data from the memory, a syndrome generating circuit 7 receiving the read data, a check syndrome generating circuit 13, an error location and error value detection circuit 8 calculating the error location and error from the result of production of the syndrome generating circuit 13 and an adder circuit 15 adding the error information to the output of the circuit 13 from the calculated error location and the error. Thus, in applying error correction, error check is attained at the same time. Thus, the number of times of data read from the memory is decreased by one for the check to improve the data processing speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error correction and checking device suitable for application to a digital data reproducing system from a disk recording medium such as a magneto-optical disk.

[Summary of the invention]

This invention enables error correction and error checking to be completed at the same time when the direction of the generation series of error correction codes and the direction of the generation series of error checking codes are in the same direction for data arranged in a matrix. As a result, the number of times data is read from the buffer memory can be reduced, and data processing time can be shortened.

[Conventional technology]

2. Description of the Related Art Devices for recording and reproducing digital data on disk-shaped recording media such as optical disks and hard disks are known.

In this case, digital data is generally recorded and reproduced by constructing an error correction code that can detect and correct data errors that occur during recording on and reproduction from a disk.

Usually, a block-contained type is often used that forms an error correction code for a predetermined number of information sample data.

When the information data is computer data, even if errors are corrected in units of information data blocks, if the information data is not truly correct, it cannot be used as data, so errors occur in units of information data blocks. A check code is also added to check for errors.

FIG. 4 shows an example of such an information data block. For example, digital data is expressed in bytes as l fil
(However, one information sample is not necessarily one byte) as shown in Figure 4.
Digital data is m bytes in the row direction on the memory.
Arranged in a matrix as n bytes in the column direction, and m bytes (m pieces) of data in each row in the row direction (
k, m) code is generated and -mlIli check data C1 for error detection and correction is added to it, and (1, n) code is generated for n bytes (n pieces) of data in each column in the column direction. Generate l−n error detection and correction test data C2
is added to form a product code.

In this case, an error check code EDC is inserted in the last line of the information data to ultimately check whether or not there is an error in this information data block. This code EDC is generated by sequentially reading data in the row direction from the top row to the bottom row.

In such a product code, first, error correction is performed for each row using test data C1, and then error correction is performed for each column using test data C2. In principle, all errors can be corrected by repeating the process repeatedly. However, if error correction is carried out to the limit in this way, data reliability will be lost. Therefore, after an appropriate number of repetitions, error correction is stopped and the error check code ED is
A data check of the corrected information data block is performed by C.

[Problem that the invention seeks to solve]

By the way, such error correction and checking processing is
The reproduced data is temporarily written in the buffer memory as matrix data as shown in Fig. 4, and the inspection data C
When performing error correction using test data C2, data is read out sequentially in the row direction, and when this is completed, data is read out sequentially in the column direction and error correction is performed using check data C2.

After the error correction is completed, the data is sequentially read out from the buffer memory in the row direction again and an error check is performed using the error check code EDC. Therefore, for this error check, after the error correction is completed,
It is necessary to read the data from memory again. This has the disadvantage that the processing time becomes longer in the case of an error correction code that requires a large number of times to read data from the memory as described above.

[Means for solving problems]

In this invention, a plurality of pieces of data are arranged in a matrix as one block, and an error correction code is generated in at least one of the row direction and the column direction, and the error correction code is generated in the same direction as the generation direction of the error correction code. a memory for storing data including an error check code generated for the data in the l block, a reading means for reading data from the memory in the generation direction, and a syndrome generating means and check to which the read data is supplied. It consists of a code generating means, a means for calculating an error position and an error value from the generation result of the syndrome generating means, and a means for adding error information from the calculated error position and error value to the output of the check code generating means.

[Effect]

When performing error correction in the row direction, the read data is supplied to the check code generation means.

Therefore, when all error correction in the row direction is completed, a check code is also generated while all data is read. However, in this case, the check code was generated using data that still contained errors, so the check code is not correct as it is.

Therefore, information on the error value at the error position obtained during error correction is added to the generated check code. This is exactly equivalent to generating a check code from the error correction result data. In other words, there is no need to read data from memory specifically for generating check codes, and when error correction is completed, checking can be performed at the same time.
Processing time is short.

〔Example〕

An example of the present invention will be described using a case where data is reproduced from a magneto-optical disk.

First, the formant of a magneto-optical disk will be explained.

In this magneto-optical disk, data is recorded as one track per revolution, forming a trunk in a circular or spiral pattern, and is reproduced from this trunk.

One track of this magneto-optical disk consists of a plurality of sectors equally divided in the circumferential direction, and each sector contains a predetermined number of data with an error correction code and an error check code generated and added. recorded.

For example, one track is made up of 32 sectors.

One sector consists of a header section, a data section, and a gap section GAP provided after the header section and after the data section.
It consists of

In the header section, a preamble signal is recorded at the beginning, as well as trunk address TA and sector address S.
An address synchronization signal ASYN is added to the address signal ADD consisting of A and an error correction code ECC.
The one with C added is recorded twice.

Further, in the data section, a preamble signal is recorded at the beginning, and after that, data and an error correction code ECC and the like added to the data are recorded.

In this case, the standard unit data amount to be recorded in the data section of one sector is 512 bytes, considering the use as a computer storage device.

The structure of the data section is as shown in FIG.

In other words, in the case of Fig. 2, the number of data is 512 bytes from Do to D511, and the actual data is 16 bytes of additional information added after the 512 bytes of data Do'''Dstx in the row direction. 44 bytes in the column direction and 12 bytes in the column direction, resulting in a matrix array of 44×12=528 bytes.

That is, the 12 bytes after the 512-byte data DoNDs1x are used as a reserve area, and track numbers, sector numbers, data identification information, etc. are inserted into this area. Then, a 4-byte error check code EDC (for example, using a Reed-Solomon code) is generated for the 524-byte data including this reserved area, with the row direction as the generation direction, and is inserted into the last 4-byte area of additional information. be done. A total of 528 bytes are arranged in a 44×12 matrix as shown in FIG.

4-byte data P of this error check code EDC
, Q, R, and S are generated as . Here, in this example, N=523.

Then, for 528 bytes including 4 bytes of this error check code EDC, 4 bytes are written for each row in the row direction.
Check data C1 of the first error correction code (this is a (48, 44) Reed-Solomon code, for example) is added as one byte, and similarly, a 2-byte second error correction code (this is the For example, (14, 12
) Reed-Solomon code) test data C2 is added.

From the above, in this case, the 512 bytes of data is
Add 16 bytes of additional information related to this data,
A block consisting of 528 bytes is formed, and this is arranged in 12 rows and 44 columns to generate and add parity C1 in the row direction and parity C2 in the column direction to form a product code, which is recorded and reproduced as one sector of the disk. It is something.

Error correction and checking processing for this data block will be explained.

FIG. 1 is a functional block diagram of this processing, and (1) is a RAM for data buffer. Timing control of writing and reading for this RAM (1) is performed by a microcomputer, and the functions of this microcomputer are shown in block form as a timing controller (3).

(2) is an address controller for RAM (11).

Switches (4) and (5) are provided on the data input side and data output side of the RAM (1), and their switching is controlled by a switching control signal from a timing controller (3).

When writing playback data from the magneto-optical disk, the switch (4) is switched to the input end A side, and the playback data that has been played back from the magneto-optical disk and restored to a digital signal passes through the input end (6) and is transferred to this switch. (4) Through R
A M (11) is supplied to the data input terminal. In this case, data from the disk is reproduced sector by sector, and the data is block data with the structure shown in Figure 2. Then, the address controller ( The write/read control signal from the controller (2) puts the RAM (1) into the write state, and the write address from the controller (2) causes the playback data to be sequentially written to the RAM (1), as shown in Figure 2. Matrix-like block data is reproduced on memory.

When writing is completed in this way, error correction and checking are performed, but in this example, error correction is performed in the order of ■ Correction using test data C1 - ■ Correction using test data C2 → ■ Correction using test data C1. Correction using the data C1 is performed twice, and in this example, a data change operation is also performed at the same time as the second correction using the test data C1.

That is, first, switches (4) and (5) are connected to terminals B and B', respectively. And RAM (1
), data is read out in the row direction in FIG. 2, and a syndrome is generated for each row in the first syndrome generation circuit (7). When there is an error, the error position and error value are detected by the detection circuit (8).
) is calculated. Information on the error position and error value is then supplied to the error correction circuit (9), and the error data is corrected. Further, data on the error position is supplied to the address controller (2). Then, by the address signal from this address controller (2), the RA
The detected error data in each row of M (11) is rewritten with correct correct data from the error correction circuit (9).

When the correction based on this first inspection data C1 is completed,
The remaining errors are corrected using the test data C2. That is, switches (4) and (5) are connected to terminals C and C'. Then, data is read from the RAM (1) in the column direction in FIG. 2, and a syndrome is generated for each column in the second syndrome generation circuit (10).

If there is an error, the error position and error value are calculated by the detection circuit (11). At this time, the error flag for the row that could not be corrected during correction using the inspection data C1 may be referred to.

Information on the error position and error value is sent to the error correction circuit (12
) to correct the error data. Information on the error position is also supplied to the address controller (2), and under the control of this address controller (2), the detected error data in each column of RAM (11) is corrected by the error correction circuit (12). The data will be rewritten to the correct data.

When the correction using the test data C2 is completed, the remaining errors are further corrected again using the test data C1. That is, switches (4) and (5) are connected to terminals B and B', and data is read out from RAM (1) in the row direction in FIG. 2 and sent to the first syndrome generation circuit (7). Supplied. At this time, RAM (1
) The data read from the check code generation circuit (
13). Then, when performing the error correction operation for each row described above, calculations for generating check codes are gradually performed. And RAM (
1) Check code generation ends when all byte data is read out, but since this check code is data before the second correction using the test data C1, it may contain errors. In other words, when the correct check code is WI (generated from the i-th byte data), the actual one is Wl'
= aj61 + α'ek + ” ” ” +W(
It is expressed as However, j, k... are error positions,
eJ, 1B5, . . . indicate error values, respectively.

By finding αJeJ and αke w included in Wi' and adding these to Wl', a'ej to cx'ej = 0 (m
od, 2), so w,'=w, and a correct check code can be obtained.In this case, a correct check code can be obtained as follows.

That is, at the time of correction using this second inspection data C1,
Information on the error data position and error value detected by the detection circuit (8) is supplied to the error position and error value change circuit (14), and this circuit (14) changes the error position and error value suitable for generating a check code. Converted to value information. That is, error position information for one line in the row direction is converted to position information using serial numbers from D1 to D521+, and from this position information and error value, the above-mentioned error information α'eJsαke k... is calculated. be done. This error information is then supplied to the addition circuit (15) and added to the check code from the check code generation circuit (13). In this addition circuit (15), w
By adding +od, 2, the error contained in the above-mentioned error has been corrected, and a correct check code is obtained. This check code is supplied to a check circuit (16) to check whether the error has disappeared. Then, the check result signal is a buffer amplifier (so-called three-state buffer) (
17), and if there is no error, this amplifier (17) is enabled, and if an error remains, this amplifier (17) is disabled.

After error correction and checking are thus completed, the switch (5) is connected to the terminal A', and the corrected data is read out from the RAM (1). However, as mentioned above, if an error remains as a result of the check, the data cannot pass through the buffer amplifier (17) and is not obtained at the output terminal (18), resulting in a block of error-free data. only that which is available at the output (18).

Furthermore, based on the output of the check circuit (16), RAM
(The data corrected from 11 may not be read.

FIG. 3 is a flowchart of the above error correction and checking operation.

In the above example, when correcting errors using the first inspection data C1, a check code is generated at the same time, the error value obtained at that time is added to the check code, and then the second inspection At the time of error correction using the data C1, the check code may not be generated, and the error value obtained at that time may be further added.

Of course, error information obtained from the error position and error value obtained during error correction using the test data C2 is also added to the check code.

In addition, in the above example, the test data C2 is added not only to the test data C1 in the row direction but also to the column direction, so when these are repeated, the test data C1
When making the last correction, a check is made at the same time. However, in this invention, the inspection data C1 in the row direction
Of course, it can also be used for error correction codes in which there is only one error correction code, and in this case, reading data from the memory only needs to be done once for error correction and checking.

Note that the error checking code is not limited to the above code, and for example, a CRC code or other error detection code can be used.

〔Effect of the invention〕

According to this invention, when error correction is performed, error checking can be performed at the same time, and the number of times data is read from memory can be reduced by one time for the checking operation, thereby increasing data processing speed. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram for explaining an example of the structure of a data block, FIG. 3 is a flowchart of error correction and checking operations, and FIG.
The figure is a diagram for explaining a product code as an example of a data block structure. (1) is a RAM as a buffer memory, (7) is a syndrome generation circuit, (8) is an error position and error value detection circuit, (13) is a check code generation circuit, -(15)
) is an adder circuit.

Claims (1)

[Claims] A plurality of pieces of data are arranged in a matrix as one block, and an error correction code is generated in at least one of the row direction and the column direction, and the error correction code is generated in the same direction as the generation direction of the error correction code. a memory for storing data including an error check code generated for the one block of data in the above-mentioned direction; a reading means for reading data from the memory in the above-mentioned generation direction; a syndrome generating means to which the read data is supplied; It consists of a check code generation means, a means for calculating an error position and an error value from the generation result of the syndrome generation means, and a means for adding error information from the calculated error position and error value to the output of the check code generation means. , An error correction and checking device that can perform error checking at the same time as error correction decoding processing.