JPS6096030A - Decoding system - Google Patents

Abstract

PURPOSE:To correct residual errors by switching the mode of error correction into two modes; the filtering decoding mode and the residual erasure correcting mode to correct the errors thereby providing the detecting ability and the correcting ability to an R parity. CONSTITUTION:One segment's share of data is stored in an RAM32. A mode switch 35 is changed over to the position A, an error is detected by an error detection circuit 28 of the R parity code by the command of a decoding control circuit 18 and an R flag is formed. The formed R flag is stored in an R flag register 31. Then a P decoder D1 reads data from a terminal 34 by using erasure information from the register 31 and decodes it. The result is inputted again to the RAM32 and the flag is cleared. Then a Q decoder D2 is actuated similarly. The error not corrected is left after the repetition. The switch 35 is changed over to the position B by the command of the control circuit 18. Thus, the mode is switched from the filtering mode into the residual erasure correction mode. An R decoder 21 corrects the remaining errors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a decoding system for correcting errors in digital information.

[Prior art]

C cassette rotating head DAT (Digital
Error control codes are used in audio tape systems and the like. In the rotating head DAT system, data for one scan can be stored in RAM memory, so
It is possible to decode the s9 return. First, the conventional method will be explained.

FIG. 1 shows the block format of the 1dl block t bit.

In the figure (11 is an 8-bit synchronization signal part, (2) is an a-pit address part, 13) 141 U Q, parity symbol Q1 of the parity code. Q2 part, +50
61 is the parity symbol P1.61 of the P parity code. The P2 part, (7) is the m-bit data part, and (8) is the δ-bit R parity code parity symbol part, Pl,
P2. Ql and Q2 are respectively bit numbers P1. P2.
q1. If q2, then z=a+q1+q2+p1+p2
+m+δ.

Figure 2 shows data for one scan in one segment format, with one segment uL block or tXL
Consists of bits. On the encoding side, data is triple encoded. (8,6,3) Re(R
eed -Solomon) code 'fQ parity code with (10,8,5)Re code on G F (28)
O of G(Z) = χ 1 χ 1 χ + 1 in the parity code
Assuming that an RC (Cross Reed-Solomon) code is used, 0 where (n, ni, cl) is the code length n
, number of information symbols k.

is the linear sign of the minimum distance d. Each parity check symbol of the RE code is encoded based on □(l). α is the primitive polynomial χ8+χ4+χ
It is the root of 6+χ”10i=o.R8 with minimum distance a=3
The code encoder and decoder are a VTR (video tape recorder) type E-AJ (Japanese Industrial Standard) PCM recording adapter 1 or each 61 pcM recorder, and since they are publicly known technology, they will not be described in detail here.

FIG. 3 is a diagram showing the interleaving structure of the buffer RAM memory on the receiving side. Accumulate L blocks of data for one scan. In the figure, (9) is the encoding direction of R parity, a. is the encoding direction of P parity, and αυ is the encoding direction of Q parity.

Dp, Dq? The parity symbol p of the P parity code is the delay amount of the P sequence and Q sequence with respect to the R sequence, respectively.
1. p2 is Pl(su=WO(i+2Dp)+W1 (i+!+Dp
)+W2(i+4Dp)-1-w5(i+5Dp)
+W4 (i+6Dp) +ws (i+7Dp)P2
(i+Dp) =Wo (i+2Dp) +W1 (i
+ 3Dp)・α10W2 (1+4Dp)・α
2+W5 (i + 5Dp)・α'+W4(i+6D
p)・α 10Ws(i+7Dp)・α”' −(21 The parity symbol Q1 . of the Q parity code is given by
Q2 is Ql(,i) = Wo (j +2Dq) 10W1(
j +3DQ) +W2(j+4Dq)+Ws (j+
5Dq)+W4(j+6DQ)+W5 (j+7Dq)
+P1 (j+8Dq)+P2 (j+9Dq) Q2 (j+DQ)=Wo (j+21)q)+VN
(j+3Dq)・α+W2(j+4Dq)・α+W
3(j+5Dq)α +W4(j+6DQ)α +Ws
(j+7Dq) α 10P1 (j+3I)q ) α1F2
It is given by (j+9DQ)α7□(3). Here, WQ, Wl, . . . , W6 are data symbols (8 bits). Here, (.) indicates the time relationship between frame transmission and reception.

In decoding, all error detection is first performed by decoding R parity, but the error in the valley block is generated by the generator polynomial G0)=χ16+
This is performed by dividing χ12+χ5+1. A flag is stored in a register such as '1' for a block in which an error has been detected and '10' for no error.

The P parity code is decoded without fail, and the symbols with the R parity flag set are corrected as erasures. In this way, up to two erasures in one code word of P parity are corrected. Up to one error missed by the R parity code can be corrected. The corrected R parity flag is cleared to 'θ'. Next, decoding of the Q parity code is performed. The 4-parity code also corrects up to 2 erasures. Furthermore, there was a method of correcting errors using P parity, Q parity, and decoding.

However, this conventional method had the following drawbacks.

It is shown below.

FIG. 4 shows an example of an error pattern that cannot be corrected by repeated decoding of P parity and Q parity.

In FIG. 4, (I is an error symbol, α is an R parity encoding direction, (14 is a P parity encoding direction, and a is a Q parity encoding direction. In the conventional system, as shown in the figure, P, If 3 erasures occur in the Q parity code, it cannot be corrected, and no matter how many times decoding is repeated, no improvement can be achieved.

[Summary of the invention]

The present invention was made for the purpose of improving such drawbacks, and provides a decoding system that corrects residual errors by providing R parity with detection ability and correction ability.

[Embodiments of the invention]

By the way, there is a prior art technique for correcting this residual error called IA erasure estimation decoding. This will be explained below.

FIG. 5 shows its configuration block diagram. In Figure 5,
QQ is a transmission path, Qη is a reception input terminal, and Taku is a decoding control circuit (19 is a clearing output terminal, Dj, D2. D3
゜..., Dk is Taniya P decoder, Q decoder, P decoder.

. . . is a P or Q decoder (k is an appropriate number of repetitions), (to) is a residual erasure estimation circuit, Q is a residual erasure correction circuit, (2) is a decoding 1i of division of each decoding
(2) is a data input/output terminal that inputs the V information to the residual erasure estimation circuit (to), and (2) is an input/output terminal that transfers data from the residual erasure estimation circuit to the residual erasure correction (b) path; (to) (2) is the input/output terminal for erasure information, respectively for erasure information of P parity,
Transfer Q parity erasure information to the R decoder.

Information entered manually from the decoding side input terminal αη is sent to the P decoder D1.
．． Q decoder D2. 'P decoder D3..., P decoder D3..., P decoder or Q decoder Dw sequentially decodes and filters the remaining 9 error patterns.During decoding, 11V information regarding the remaining error patterns is used to estimate the residual erasure. Output to circuit (a). This state is called filtering mode. In this invention, DI.

D2. . . . is also called a Dk-'ii filtering symbol.

Residual erasure estimation circuit 1dEstimates nine residual error patterns from the decoding information obtained in the decoding stages from D1 to Dk, and uses them as erasures during decoding in the residual erasure correction circuit Qυ.

The residual erasure correction circuit (to) is a grid-like array of erasures 7 estimated by the residual erasure booster circuit (2).
The symbols are sequentially decoded and predetermined data is output.

Application examples of this invention will be considered below using specific examples. In the digital format of this invention, the R parity part is not aRc but the Galois field GF(2) with d=3 (12, 10, 3)
The only difference is that it is marked RE. The parity check symbol of the R parity code is the parity check matrix HR.

It is encoded based on . α is χ8+χ4+χ3+
χ2+1=root of O. Paritikunpol Ri.

R2 is given by the following formula.

Rt (k) = Wo (k) + VIN (k) + ・+
P+ (k) + P2(k) +Q1(k)+Q2(k
) R2(k) = W O(k) +W 1 (k)α+
w2@) α +-,, + w5 (k) α5hiP1(k
) α6 + P2 (k) α' + Qt (k) α8 + Q2 (k)
α □ (5) Decoding first begins with calculation of R parity syndrome S1°S2.

ν Here, q is rr=(rr,, rrl,...,σi
,...

qn-1) is an element of the reception vector.

+71 is the transmission vector (No, Wl, W2.
Pl, P2゜Ql, Q2) and noise vector 42 (θ
0. θ1. ....

θ. -4) on the Galois field (however, n
= 12).

That is, when both Sl and S2 are all Q patterns, there is no error (strictly speaking, no error was detected), and in other cases, an error is detected (an error is detected and the error is detected), and the R flag is set. Teru. It is the same as the prior art that the R flag is used to sequentially correct errors in the P parity code, Q parity code, P parity code, and so on.

However, even in the case of this invention, the error pattern mainly shown in FIG. 4 remains. However, since it is now possible to correct 9 errors using the R parity code, correct decoding results can be obtained by correcting 1 error or 2 erasures for each valley block. P decoding, QU during Filkling decoding
By using the syndrome information of the L code, up to two erasures can be corrected in the R decoding of the R parity code.

FIG. 6 is a decoding flowchart 6By of the decoding system according to the present invention, and FIG. 6A is a block diagram of a residual erasure estimation circuit mainly consisting of a RAM memory peripheral circuit.

The operation will be explained below.

In Figure 6, (c) is the start point, @ is the routine that moves one segment worth of data to RAM memory, @
is the R flag creation routine, Di is the P decoding routine, D2
is the Q decoding routine, D3 is the P decoding routine, ..., D
k is P or QOI routine.

aU is the R decoding routine, and @ is the transmission end determination routine.

(7) is a strafe point.

First, one segment of information is transferred to the RAM in routine (c). In the next R flag creation routine (c), error detection is performed for each block by calculating the syndrome of the R parity code. The result is R flag Regis g -C
It is memorized in 3υ.

Next, filtering decoding is started, first P decoding routine D
In step 1, error correction is performed using the R flag information.

The flag corresponding to the corrected symbol is cleared. Similarly, filtering decoding is executed by repeating nine decodings one after another, such as Q decoding in routine D2 and P decoding in routine D3,
After performing P or Q decoding in routine Dk, routine t
Correct remaining errors by performing R decoding in 2D. In routine (2), it is checked whether the transmission is finished, and if not, the next segment data is decoded.

In Figure 1, 0υ is the R flag register, (to) is R
AM memory, 03 is the RAM cheater terminal.

(Corporate) is the RAM data out terminal, (To) is the mode switch, 0 [9 is the RAM address control cape circuit, (To) is R
7 lag detection circuit, DI is P decoder, D2 is Q decoder,
@ is the R flag register system cape signal human output terminal, @ is the R flag detection circuit system human output terminal, DI is the P decoder control signal input/output terminal, f41 is the q decoder control signal human terminal, 1υ
is the mode changeover switch full Idl signal input terminal.

63 is a relay terminal that transfers the RAM data to the R decoder Qυ in FIG.
(Relay terminal for transferring to decoder (211), (c) Relay terminal for transferring erasure 1a information of tiQ decoder D2 to fR decoder QIl, Rx is a control input/output terminal to R decoder t2D.

Hd is a RAM addressable signal output terminal.

In FIG. 8, Qυ is an R decoder, (11 is a data output terminal. The data digitally demodulated on the receiving side detects a 5YNC pattern and is stored in the RAM memory 03 for one segment for each valley block. The mode switch (G) is turned ON to the A terminal side, and an error is first detected by the R parity code error detection circuit (T) using the phalanx of the αυ decoding control circuit, and an R flag is created. The R flag is stored in the R flag register 0υ by the command from the decoding control circuit Cod. Next, the P decoder D1 is stored in the R flag register O by the command from the decoding control circuit QB.
1; Use erasure information to connect the data out terminal (
Data passing through (goods)? Read and decode. The result is input from the data-in terminal (c) to F) [RAM memory C (Q). The flag that has been corrected is cleared to θ'. Next, Q decoder D2 performs error correction in the same way. .In this way, the P or Q decoders perform corrections one after another,
After decoding is repeated several times, there remains a force that cannot be completely corrected. According to the command of the decoding control circuit (Is), multiple mode changeover switch control signals are input to the terminal @υ and sent to the switch CI!19t-B terminal side.In this way, the mode changes from the filtering mode to the Nishibo erasure correction mode. The R decoder υ corrects the remaining error 'ft according to a command from the decoding circuit and outputs the decoded data from the terminal.

〔Effect of the invention〕

As described above, the present invention 4'j, R parity code not only performs error detection but also d14J) correction, making it possible to efficiently correct remaining errors.

Of course, instead of using the R parity code twice for error detection and total correction as in the present invention, it is also possible to use a separate error detection code and a separate error detection code.

However, doing so will increase the hardware tri.

Furthermore, although the P parity, Q parity, and R parity codes have been described using R8 codes with the minimum distance d=3 for convenience, it goes without saying that general error correction codes can be used. At that time, the number of check symbols increases, but it is easily applicable. Further, the difference between the prior art and the present invention is that the prior art uses hard decision decoding without using Ruscia for filtering decoding, but the present invention uses soft decision decoding using erasure. Further, in the prior art, P parity and Q parity used in filtering decoding are also used for residual erasure correction, but the present invention differs in that R parity is used for correction.

[Brief explanation of drawings]

Figure 1 shows the data block format, Figure 2 shows the data block format.
The figure shows the data segment format, Figure 3 shows the interleague delay time 9F,f between data blocks on the RAM memory, Figure 4 shows the remaining error pattern, and Figure 5 shows the remaining error pattern. Figure 6 is a block diagram of residual erasure estimation decoding using the 9L technology, Figure 6 is a decoding flowchart of the decoding system of the present invention, Figure 7 is an explanatory diagram of the residual erasure estimation circuit of the present invention, and Figure 8 is the present invention. FIG. 2 is an explanatory diagram of a residual erasure correction circuit of FIG. In the figure, D1 is a P decoder, D2 is a Q decoder, (l is a decoding control circuit, (a)
is a residual erasure estimation circuit, Qυ is a residual erasure correction circuit, @ is an R flag detection circuit, 0υ is an R flag register, C32 is a RAM memory, (c) is a mode switch, and (to) is an address control circuit. In the drawings, the same or corresponding parts are indicated by the same reference numerals. Agent Masuo Oiwa Figure 1 @ 2 Figure @ 3 Figure 111 -1 Figure 6 Figure 7

Claims (1)

[Claims] In a decoding system in which digital information such as a product code is repeatedly encoded and transmitted multiple times, and the transmitted digital information is decoded on the receiving side, the digital information is repeatedly P-decoded and Q-decoded in a filtering decoding mode. P decoder and. A decoder, and an R decoder that decodes residual error information that has not been completely corrected while repeatedly decoding the P decoder and the Q decoder in a residual erasure correction mode. A decoding system characterized by correcting errors by switching the mode between two modes: a filtering decoding mode and a residual erasure correction mode.